JPS6247872A - Time base correcting circuit - Google Patents

Abstract

PURPOSE:To reduce the scale of a time base correcting circuit by making this circuit use a processor in common which rearranges data to eliminate the variance of the time base. CONSTITUTION:A time base correcting circuit 1 delivers the SYNC pulse through a SYNC detecting circuit 1-2 which detects the SYNC information on the data train. Then the circuit 1 forms a write address with said SYNC pulse and the clock synchronizing with the reproduction data word. Then the order of write data is exchanged with that of the read data. A memory 1-1 can work at high speed and therefore the another kind of data can be read out of the memory 1-1 for a period from the writing of data to the writing of the next data. Furthermore the constitution of a read or write address generating circuit 1-4 or 1-3 which is necessary for exchange between orders of data by carrying out this exchange at every frame is simplified. Thus the rearrangement of data is carried out at every frame by a memory. This omits a rearrangement circuit needed in a reproduction mode and therefore reduces the scale of a time base correcting circuit.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to rearrangement of data necessary as pre-processing for correcting burst errors occurring during digital magnetic recording and reproduction using frame-by-frame error detection/correction codes. In particular, the present invention relates to a circuit that performs this operation also as a conventional time base correction circuit.

[Background of the invention]

In the case of digital VTRs that convert video signals into digital signals and record and play them back on magnetic tape, signal dropouts can occur due to dust or scratches on the magnetic tape.
A data coding error occurs.

Therefore, it is necessary to correct data in which a code error has occurred using digitized video signal data and an error detection/correction code generated from this video signal data.

In particular, in devices such as VTRs that repeatedly record and reproduce magnetic tape, the number of burst errors caused by scratches on the tape increases little by little each time the tape is used.
The length of the code error is also uncertain.

To deal with these code errors, the burst error correction method described in Japanese Patent Application Laid-Open No. 53-66306 uses a circuit that randomly rearranges the code arrangement during recording and reproduction.
We have proposed a method that uses error correction codes to perform correction after dispersing the effects of burst errors that occur during recording and reproduction.

Here, FIGS. 1A and 1B show examples of input signal formats for the arrival method.

One frame is composed of a frame synchronization signal (SYNC), a data signal (d, d2...d,), and a shortened cyclic code (CRCC) as an error detection code for each frame. In Figure 1 (B), 1°D-2・
. . . is a data frame, P-, , P, , is an error correction parity frame, and these will be collectively called a correction block. Here, m indicates the number of the corrected block.

Next, an example of the operation of the conventional method is shown in FIGS. 1(C) and 1(D).

The input digital signal string has the signal format shown in FIG. 1(B).

First, during recording, each frame has a different delay amount, for example, 0 frames for D1□, 6 frames for D, and 12 frames for D. A delay amount of one frame is given to perform frame-by-frame rearrangement, and the code string shown in FIG. 1(C) is created and recorded on a magnetic tape.

At the time of playback, 12 frames for the played Dl,
Give a delay amount of 6 frames to D12 and 20 frames to Dl3, and reverse rearrange the frame units so that the total amount of delay given during recording and playback is always a constant amount. Let's do it.

If a burst error of the length shown by the black line at the top of the digital signal string shown in FIG. 1(C) occurs, if the above conversion is performed, the digital signal string of FIG. 1(C) will be 1
The signal is converted as shown in Figure (D), and burst-like code blocks are distributed in the portion indicated by the black line at the top of the digital signal string.

As a result, the length of the code error in the correction block is reduced,
Correction using error correction code parity becomes possible.

Error correction for burst errors is performed as described above, but in this case, a delay memory for delaying a predetermined number of frames is required in the recording and reproducing circuit.

In this way, a dedicated delay memory has conventionally been required to rearrange the order of data obtained from a magnetic tape.

[Purpose of the invention]

The purpose of the present invention is not to provide a new dedicated memory for rearranging the order of data from a magnetic tape, but to eliminate the time axis fluctuations that data from a magnetic tape inevitably accompanies. It is an object of the present invention to provide a new circuit configuration in which a conventionally used time axis correction circuit is also used for processing the data rearrangement, thereby reducing the circuit scale.

[Summary of the invention]

The time axis correction circuit consists of a memory section, a write address specifying section that specifies where in this memory data is to be written, and a read address section that specifies where in this memory data is to be retrieved. Furthermore, the write address section operates in synchronization with the write clock,
The read address section operates in synchronization with the read clock.

Therefore, the order of the input data string (which involves time axis fluctuations because it is reproduced data from a magnetic tape) and the output data (VT
Since the data is read using a clock oscillated by the R circuit system, there is no time axis variation. ) can be realized by simply changing the order of the write addresses and the order of the read addresses of this time axis correction circuit.

[Embodiments of the invention] The present invention will be explained in detail below using examples.

The data is rearranged in the order shown in FIG. 1(C) and recorded on a magnetic tape, and the time axis correction circuit 1 according to the present invention shown in FIG.
Error correction can be effectively performed by rearranging the data order and dispersing dropouts that occur on the magnetic tape.

The time axis correction circuit 1 in FIG. 2 is an SMMC detection circuit 1- which detects the 5YNC information of the data string shown in FIG. 1(A).
2, a S Y N'C pulse is generated, and this pulse and a clock synchronized with the reproduced data word constitute the write address. For the sake of simplicity, FIG. 3 shows addresses in frame units together with the data order, where (E) is the write order and (D) is the read order. As shown in FIGS. 3(E) and 3(F), the data order is changed and returned to the original order (B) at the time of recording.

The memory 1-1 is a high-speed memory, and is configured such that after writing one data, another data can be read from the memory 1-1 before writing the next data.

As shown in FIG. 3, the memory capacity is required for 24 frames. This is because the recording side shown in FIG. 1(B) has a structure as shown in FIG. 1(C) in which the signal for three correction blocks is expanded and distributed to a range of four correction blocks (24 frames).

Note that FIG. 3 shows an example in which a conventional case is applied to the method of changing the order on the recording side. but,
It goes without saying that methods other than the conventional method may be used for changing the order on the recording side.)

In addition, if the order is changed in units of one frame, there is no need to convert the address for each data in one frame, so the read Azores generation circuit 1-4 or the write address circuit 1-3 necessary for the change is The circuit configuration is simplified.

FIG. 4 shows another embodiment of the present invention, in which the time axis correction circuit 2 is of the so-called shift register type, and while three memories are sequentially switched and data is written to one memory, This means reading from another memory.

In this format, the order can only be changed within the range of data written in two memories, so as shown in Figure 1, the data of three correction blocks can be changed in order within the range of four correction blocks. Replacement method is not available.

FIG. 5 shows another example of rearranging the data order suitable for the time base correction circuit of FIG. 4.

First, the time axis correction circuit 2 suitable for the present invention shown in FIG. 4 will be explained.

The write control circuit 2-4 detects the synchronization signal (S Y NC) added to each frame during recording, and uses the position information (ad in FIG. 5(G)) to write the data to the memory 2-1. memory 2
-2. Specify the selection and write address of the memory 2-3, and write the data signal (dl, d, . . . ) following the position information.
...) is written to memory. Each memory has a capacity that is an integral multiple of the frame, and when the memory is filled with data signals, the read control circuit 2-5 sequentially starts from each memory.
Reading is performed, and data from which time axis fluctuations have been removed is output to the output terminal 2-7.

The input signal format (G) in FIG. 5 is the conventional format shown in FIG. 1 (A) with position information (ad) added. The capacity of each memory of the time axis correction circuit is 3 correction blocks (18 frames).

First, during recording, continuous 18
Data is rearranged into frames (3 correction blocks) in units of frames. The rule for rearranging at this time is that the adjacent frames after rearrangement are frames that constitute different correction blocks before rearrangement, that is, the first frame after rearrangement is the frame shown in FIG. ), if the frame D11 constitutes the first correction block,
The second frame D! constitutes the second correction block. !
, the third is frame D3 constituting the third correction block.
Set to 1. Data ordering is thus performed within the three correction blocks.

When such rearrangement is performed, the digital signal string shown in FIG. 5(I) is obtained. The digital signal sequence shown in Fig. 5 (T) is recorded on the magnetic tape, and during playback, the digital signal sequence shown in Fig. 5 (,
). The means for rearranging at this time is performed using the time axis correction circuit shown in FIG. 3 mentioned above. Fifth
Frame D ttt D21 in Figure (I). D3
1...P and 2 are assigned to addresses 1, 7, and 18 of the memory 2-1 of the time axis correction circuit 2, respectively, according to the position information (ad) constituting each frame. Write to. Furthermore, while writing to another memory 2-2.2-3, the memory read control circuit
Transfer the data in memory 2-1 to addresses 1, 2, 3, etc.
. . . Data is read in order from address 18. As a result.

A digital signal train having the same signal form as in FIG. 5(J), ie, FIG. 51) is obtained at the TBC output.

Here, when a burst error of one correction block length occurs as shown by the black line at the top of the digital signal string shown in FIG. 5(I), the code error occurring in each correction block is It is distributed and has a length of 2 frames. At this time, if the correction ability of parity P, 1°P, 2 is capable of correcting up to 2 frame lengths, all burst errors shown by black lines can be corrected. FIG. 6 shows a block diagram of a circuit for converting the signal format of FIG. 5(H) to FIG. 5(1) on the recording side of the second embodiment.

01.04, 05, 06 are data selectors, 02.03
is a memory (RAM) that stores 18 frames of data,
07 is a RAM address conversion ROM.

08.09 is an address counter, and 10 is a flip-flop.

The operation will be explained below according to this block diagram. First, input data consisting of a synchronization signal, position information, image data, and error detection/correction code is passed through a data selector 01 and written into a memory 02. At this time, the memory write address is the output 20 and 1 of the counter 08 of one frame period.
It is designated by the output 16 of the counter 09 with a period of 8 frames. Also, in order to synchronize the memory write address and the input data, the counter is set to 0 at the first frame of the input data.
8. Clear the counter 09 and flip-flop 10 with a clear signal. At this time, the period of the clear signal is an even number multiple of the frame length that can be stored in the memories 02 and 03.

When the writing of 18 frames worth of data to the memory 02 is completed, the states of the output signals 14 and 15 of the flip-flop 10 are inverted by the carry signal 13 outputted by the counter o9, and in response to this, the data selector 01 selects the input data 1.
1 to the memory 03, and at the same time, the data selector 04 writes the output data 12 to the memory o2.
The data selector 05 selects the output 17 of the address conversion ROMO 7 and prepares to read data from the memory 02.

Here, the read address of the memory 02 is rearranged in units of frames based on data 17 obtained by converting the output data 16 of the counter 09 by the address conversion TOMO 7 and the output 20 of the counter 08.

The write address to the memory 03 is specified by the data selector 06 using the output 16 of the counter 09 and the output 20 of the counter 08. By repeating the above operations, the signal format of the output data 12 is created as shown in FIG.
).

FIG. 7 is a detailed block diagram of a time axis correction circuit that performs reverse sorting in the second embodiment.

21 is a latch circuit, 22 is a ROM that converts position information into a memory write address, 23 is a ROM that converts a memory write address into next input position information, 24.
28 and 29 are data selectors, 25, 26 and 27 are 18
A memory 30 is an address counter for storing one frame's worth of data.

First, by latching the input data 31 reproduced from the tape with the synchronization detection signal 32, position information 33 subsequent to the synchronization signal is obtained.

Further, the position information 33 is converted into a memory write address 34 by the ROM 22. At this time, in order to prevent the position information 34 from becoming incorrect data due to dropouts or the like and being converted to an incorrect memory address, the ROM 23 predicts the subsequent position information from the address written last time and compares it with the position information 33. By doing this, the memory write address is protected.

Memory write address information 34 is sent to data selector 24
- Specify the write memory using 28, and write the input data 31 to the specified memory.

In the read operation, the read memory is sequentially designated by the output 36 of the address counter 30, and the memory contents are read out. As a result, the signal format of output 37 is:
The data is the same as the data 11 before being rearranged during recording.

In the above embodiment, the memory address designation during writing is rearranged based on the position information and the ROM 22, and the address designation during reading is performed regularly using the counter 30, realizing reverse rearrangement in frame units. Similar results can be obtained by specifying write addresses regularly and read addresses using a rearrangement ROM.

Note that if the contents of the ROM 22 are set to be written in the order of data from the tape, regardless of the position information 33,
Needless to say, the operation is the same as that of a conventional time axis correction circuit.

〔Effect of the invention〕

According to the present invention, frame-by-frame rearrangement is performed in the memory of the TBC, eliminating the need for a rearrangement circuit during playback and improving the ability to correct burst errors.

Furthermore, if the frame-by-frame rearrangement is performed based on the position information inserted for each frame, the reliability will be higher than when the rearrangement is performed simply based on the 5YNC pulse.

In other words, when the 5YNC pulse is erroneously generated for some reason, the writing location of the time axis correction circuit's memory will be shifted by one position based on the 5YNC pulse, and this malfunction will continue until writing to one memory is completed. does not recover.

On the other hand, if the position information for each frame is used, as shown in Figure 7, the position information can be checked for each frame (by comparing the previously written address with the current address, the current address may have a code error, etc.). (to protect against errors), it is highly reliable.

Furthermore, regarding the range of frame-by-frame reordering, if at least one frame of data is moved to a different correction block, the effects of consecutive code errors (dropouts) occurring in the tape head system can be eliminated. It has a mitigating effect.

[Brief explanation of the drawing]

Claims (1)

[Claims] 1. In a time axis correction circuit that uses a memory to output a data string with time axis fluctuations as a data string without time axis fluctuations, the order of the input data is different and the output data is output. A time axis correction circuit characterized by its configuration. 2. The time axis correction circuit according to claim 1, characterized in that a frame unit consisting of a plurality of data words is used as a unit for changing the order between input and output. 3. In claim 2, when changing the order between input and output, frame position data inserted into the input data string is used in units of frames each consisting of a plurality of data words. time axis correction circuit. 4. The time axis correction circuit according to claim 2, wherein the range in which the order of input and output is changed is greater than or equal to the number of frames necessary for a correction operation.