JP3079615B2 - Multimedia data playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for reproducing multimedia data for games, education, and the like.

[0002]

2. Description of the Related Art At present, video data having a frame structure for games, education, etc. and audio data synchronized therewith are subjected to encoding for compressing the amount of data and edited for combination using a CD-ROM. A multimedia data recording / playback system that records and plays back audio and video is under development.

Conventionally, a sector interleave method has been known as a method for recording video data and audio data on a CD-ROM while synchronizing them. In this sector interleaving method, there is a problem that various restrictions such as the number of channels of audio data and the relationship between the compression ratio of video data and the compression ratio of audio data arise when trying to improve the utilization efficiency of the sector.

According to a patent application of the present applicant entitled "Multimedia data editing method", encoding for compression is performed while adding a time code to moving image data having a frame structure, and the encoded data is stored in a memory, and is stored in a memory. Decoding for compression is performed while adding a recording start time code only to the head of the data, and the result is stored in a memory, and is added to video data for one frame from the bit rate of the audio data and the frame rate of the video data. A new method that calculates the bit amount of audio data to be processed and combines the video data and audio data in frame units based on the time code included in the video data header of each frame while separating the audio data from the beginning with this calculated bit amount A synchronous recording method is disclosed.

[0005]

The technical problem to be solved by the present invention is to provide a novel reproduction for reproducing multimedia data recorded in accordance with the above-mentioned novel synchronous recording method while maintaining its synchronization. It is to provide a device.

[0006]

SUMMARY OF THE INVENTION A multimedia data reproducing apparatus according to the present invention performs hybrid coding combining discrete cosine transform, quantization, and variable length coding on video data having a frame structure, and performs frame number coding. What is claimed is: 1. A reproducing apparatus comprising: a video decoder for reproducing recorded multimedia data while synchronizing with audio data by addition; and an audio decoder. A frame memory pair that can be alternately switched between the display side for displaying video data, a frame number holding register that is switched in synchronization with the frame memory pair and holds a frame number of a frame being reproduced, and a frame register. The frame number of the held frame and the frame number of the frame to be displayed In the case of collation and collation match, a switching control circuit for switching the frame memory pair on condition that the writing of the reproduced video data to the writing frame memory is completed, and in the case of collation matching, the writing frame If the writing of the reproduced video data to the memory is not completed, a stop signal generating means for stopping the operation of the audio decoder until the writing is completed is provided.

[0007]

FIG. 1 is a block diagram showing a configuration of a multimedia data reproducing apparatus according to an embodiment of the present invention, where IN is an input terminal of multimedia data to be reproduced, 1 is a demultiplexing section, Is a video buffer, 3 is a variable length code decoder (VLD), 4 is an inverse quantizer (Q ^-1 ), 5 is an inverse discrete cosine transform (DCT ^-1 ), 6, 7 are selectors, and A and B are A frame buffer having two banks, an eight video sequencer, a memory clear unit 9, and a reproduced video output terminal VO. Furthermore, 10 is an audio buffer, 1
1 is an audio decoder, 12 is a frame pulse (F
P) A generating unit, A0 is a reproduction audio output terminal, and SYN is a frame pulse output terminal.

As shown in FIG. 2, the multimedia data read from the CD-ROM at a constant speed and supplied to the input terminal IN is composed of frames of video data. This is a 2-byte start code added to the head. “DT” is 1-byte information that specifies a data type, and includes a data type (moving image / still image / audio), a channel number, and a link bit indicating whether or not subsequent data exists in the frame. . “DL” is a data length and indicates the total number of bytes of data. “DATA” is compressed variable-length video data or audio data. "

Video data A fixed-length header added to the head of the video includes a time code (TC), a video type (T) indicating whether the video data is a moving image or a still image, and a frame (Y signal). ), And a quantization table (QY, QC) for recording a quantization table applied to each of the Y signal and the C signal in block scanning order. ing. When performing quantization in hybrid coding, a quantization table that can be changed in block units is applied. At the time of decoding, an inverse quantization table is generated for each block from the quantization table, and inverse quantization corresponding to the quantization applied at the time of encoding is performed. The time code (TC) is time data indicating the elapsed time from a reference point at the start of recording in hours, minutes, and seconds, and a serial number (hereinafter, referred to as a “frame number”) continuously assigned to a frame to be compressed.
).

[0010] The multimedia data to be reproduced, which is supplied to the input terminal IN, is separated into video data and audio data by the demultiplexer 1, and written into the video buffer 2 and the audio buffer 10, respectively. The video data to be reproduced written in the video buffer 2 is
The data is converted into a fixed-length code by a variable-length code decoding (VLD) unit 3, dequantized by an inverse quantization (Q ^-1 ) unit 4, and converted into display data by an inverse discrete cosine transform (DCT ^-1 ) unit 5. Then, the data is written to one of the two-bank frame memories A and B selected as the write side by the selector 6.

The video sequencer 8 notifies the VLD unit 3 of the frame number of the frame being reproduced and finishes writing the reproduction data from the DCT ^-1 to the frame memory (end of the reproduction of one frame of video data). In response to the notification and the frame pulse FP from the frame pulse generator 12, the switching of the selectors 6 and 7 is controlled, and the reproduction synchronization signal Z to be supplied to the audio decoder 11 is generated. The audio data to be reproduced written in the audio buffer 10 is reproduced by an audio decoder 11 that operates according to the synchronization signal Z, and is supplied from an output terminal AO to an output unit.

The video sequencer 8 includes a control memory 21, a state register 22, a decoder 23, selectors 24 and 25, frame number registers a and b, a frame counter 26, and a comparison circuit 27, as shown in the block diagram of FIG. It is composed of

The frame number registers a and b in FIG.
1 are provided corresponding to the frame memories A and B. When the corresponding frame memory is selected as a new reproduction data writing side, the selector 24 writes the currently reproduced or reproduced frame number. Selected for retention. The frame number registers selected for writing and holding are reset pulses RA and R almost simultaneously when selected.
After the reset by B, the frame number of the currently reproduced frame decoded by the variable-length code decoding unit 3 in FIG. 1 is written. The written frame number is supplied to the frame counter 26 and one input terminal of the comparison circuit 27 via the selector 25.

The frame counter 26 is provided with the selector 2
5 are stored in frame memories A and B.
In addition to loading in synchronization with the load pulse L appearing at the time of switching, the load value advances in synchronization with the frame pulse FP. The comparison circuit 27 compares the frame number (α) of the currently or already written frame output from the selector 25 with the frame number (β) output from the frame counter 26, and outputs only when β ≧ α. Raise X high. Prior to the rise of this output X,
Alternatively, in a normal operation in which writing to the frame memory is completed by the time when the next frame pulse FP is output, the memory switching output from the decoder 23 is synchronized with the frame pulse appearing immediately after the rising of the output X. The signal S0 is inverted, switching between the frame memories A and B on the reading side (display side) and the writing side, switching of the associated frame number registers a and b, loading of the frame number into the frame counter 26, etc. Is performed.

That is, the frame number (β) incremented in synchronization with the frame pulse in the frame counter 26 indicates the display time of the frame of the frame number (α) output from the selector 25, and the frame number (β) The frame memory in which the moving image data of α) has been written is switched to the reading (display) side in synchronization with the display start time specified by β ≧ α, whereby the display is synchronized.

The control states managed by the control memory 21 are, as shown in FIG. 4, four states S0 to S3 belonging to a steady state and four states S0 belonging to an initial state.
4 to S7. Four states S0, S2, S4, and S6 to which even-numbered numbers are added are states in which the frame memory A is being selected as a reading side, and conversely, four states S1 and S6 to which odd-numbered numbers are added. S3
S5 and S7 are states in which the frame memory B is being selected as the reading side. In a state where both the frame memories A and B are being selected as the writing side, whether the reproduction data is being written,
It is either stopped after the end of this writing.

The eight states S0 to S7 shown in FIG.
As shown in the state transition diagram of FIG. 5, an occurrence event (event)
According to "a" to "ta", transition is made between them. Occurrence events "A" to "K" that cause state transition in steady state
The elements of (A) are the end of the writing of the reproduction data to the frame memory on the writing side. (B) β ≧ α (X is high). (C) The appearance of the frame pulse (FP). The correspondence between the event and the event is as follows. "A" and "E": (A) and (B) and (C) "I" and "O": (A) "U" and "K": (B) and (C)

On the other hand, the events that cause the state transition in the initial state are “ki”, “ku”, “ke”, “sa”, “shi”, “su”, respectively: generation of a system reset pulse. "," Set ": End of clearing of frame memory" so ": (A)" ta ": (C).

When recording multimedia data to be reproduced, data compression by frame thinning is also used for moving image data having a frame configuration to be compressed. This frame thinning is performed every other frame, every two frames,
In addition to dropping performed in accordance with a predetermined rule such as every other frame, if the data amount after compression per frame exceeds a predetermined value, this frame is subject to dropping irregularly. Is also used. Therefore, it is necessary for the reproducing apparatus to reproduce while accurately grasping what kind of frame thinning has been performed during recording based on the frame number included in the time code.

On the other hand, for audio data, no thinning is performed at the time of recording, and only data compression at a predetermined magnification is performed. When reproducing the audio data, the audio data is reproduced at a constant speed while undergoing expansion of the time axis corresponding to the compression ratio at the time of recording. As described above, since the audio data has a constant data amount per unit time and can be reproduced at a constant speed, no time code is added to the video data. However, if the display timing is shifted due to any abnormality such as reading from the CD-ROM or instantaneous interruption of data transfer on the video playback system side,
Synchronization with audio data reproduced at a constant speed is lost. In order to prevent such a loss of synchronization, a signal β ≦ α indicating the normality of the operation of the video decoder side is supplied from the comparison circuit 27 to the audio decoder, and under a high state indicating that this is true, Only the operation of the audio decoder is continued.

FIG. 6 is a time chart for explaining how to reproduce compressed data in which the above-mentioned regular frame thinning and irregular frame thinning are combined. In this example, in addition to the regular thinning-out in which even-numbered frames are dropped, the frame to be reproduced is skipped because the compressed data amount of the # 9 frame exceeds a predetermined value and is thus thinned out irregularly. # 1, # 3, # 5, # 7, #
It is 11. The signal β ≦ α indicating the normality of the operation of the video decoder continues to maintain a high state indicating that this is true.

FIG. 7 shows the case where the frames to be reproduced are # 1, # 3, # 5, # 7 and # 11 as in FIG. An example is shown in which the signal β ≦ α becomes a low state indicating that the signal is false. In the example of FIG. 7, instantaneous interruption of transfer data or the like occurs during reproduction of frame 5, so that the end of reproduction of frame 5 (end of writing of reproduction data to frame memory A) is delayed by about three frames. doing. With this delay, the signal β becomes low, indicating that the signal β ≦ α is false, and the operation of the audio decoder 11 is interrupted over this period, thereby achieving synchronization with the video reproduction system.

[0023]

Since the multimedia data reproducing apparatus according to the present invention is configured as described above, it has an effect of realizing synchronization of video data and audio data.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a multimedia data reproducing apparatus according to an embodiment of the present invention.

FIG. 2 is a data format diagram illustrating a configuration of multimedia data to be reproduced;

FIG. 3 is a block diagram showing an example of a configuration of a video sequencer 8 of FIG.

FIG. 4 is a conceptual diagram illustrating types of control states by the video sequencer 8 of FIGS. 1 and 3;

FIG. 5 is a state transition diagram illustrating a state of transition of a control state by the video sequencer of FIGS. 1 and 3;

FIG. 6 is a timing chart illustrating a state of control by the video sequencer of FIGS. 1 and 3;

FIG. 7 is a timing chart illustrating a state of control by the video sequencer of FIGS. 1 and 3;

[Explanation of symbols]

IN Input terminal of multimedia data to be reproduced 1 Demultiplexer 3 Variable length code decoder (VLD) 4 Inverse quantizer (Q ^-1 ) 5 Inverse discrete cosine transform (DCT ^-1 ) A, B Frame buffer pair 8 video sequencer VO playback video output terminal 11 audio decoder 12 frame pulse (FP) generator, A0 playback audio output terminal SYN frame pulse output terminal

Claims (1)

(57) [Claims] 1. Multimedia recorded by performing hybrid coding that combines discrete cosine transform, quantization, and variable length coding on video data having a frame structure, and synchronizing with audio data by adding a frame number. What is claimed is: 1. A reproducing apparatus comprising: a video decoder for reproducing data; and an audio decoder, wherein the video decoder is a frame which can be alternately switched between a writing side of reproduced video data and a reading side for displaying reproduced video data. A memory pair, a frame number holding register which is switched in synchronization with the frame memory pair and holds a frame number of a frame being reproduced, a frame number held in the frame number holding register, and a frame number of a frame to be displayed. If the match is found, the data is written back to the writing-side frame memory. On the condition that the writing of the video data is completed, a switching control circuit that switches the pair of frame memories, and in the case of the collation match, if the writing of the reproduced video data to the writing-side frame memory is not completed, And a stop signal generating means for stopping the operation of the audio decoder until the operation is completed.