JPS63280586A - Correction device for time base fluctuation - Google Patents

Abstract

PURPOSE:To contrive to reduce the number of components by utilizing an idle area of a memory to eliminate the need for a memory for externally mounted data delay. CONSTITUTION:An unused area (idle area) writing means is used to write image data in the idle area (nonuse area) not relating to the storage of a video signal in a frame memory 10 and the image data is transferred to the operating area after a prescribed time from the idle area to retard the image data by a data transfer means 11. Thus, passing-ahead/behind control is applied without externally mounted line memory to reduce the number of components and miniaturize said device.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a time axis fluctuation correction device for correcting time axis fluctuation (jitter) of a video signal, and in particular, to a time axis fluctuation correction device for correcting time axis fluctuation (jitter) of a video signal. This invention relates to a time axis fluctuation correction device suitable for performing the overtaking and overtaking control necessary for the above.

[Conventional technology]

Traditional time! The overtaking/overtaking control method in the IB fluctuation correction device is as described in "Television Society of Japan ASSS Vol. 4 No. 4 P, 278-279". This was done by delaying the omitted data by several lines.

Hereinafter, a conventional time axis fluctuation correction device and its overtaking/overtaking control system will be explained using FIGS. 6 to 6.

Fig. 6 is a block diagram showing the configuration of a conventional time fluctuation correction device. The extracted signal is the video synchronization signal, and 1B is the output video data 2 that has been improved by correcting the temporal fluctuation of the input video signal, and the writing position of the video writing data 1 is
Write clear signal indicating the beginning of the screen, 13
1 is a write clock generation unit that generates a write clear signal 2 from the video synchronization signal 11; 14′ is a write control unit that controls writing of video write data 1; 10 is a frame memory that stores image information for one screen; Wd'
is the data written in the frame memory 10, Wz' is the write address indicating the writing position of the omitted data W', and 15 is the reference signal for obtaining one day of output video data from the 7-frame memory 1D. 3 is a readout clear signal indicating that the readout position of the output video data 18 is at the top of the screen; 16 is a readout control unit that controls the readout of the output video data 18; 17' is a readout clock generator that generates a readout clock; , a memory control unit that controls the read/write timing of frame memo January 0.

Further, FIG. 4 is a block diagram showing in more detail the aging control section 14' of the time axis correction device shown in FIG. 6, which is a part that controls overtaking and overtaking.

In FIG. 4, 19 is a line delay unit that delays the video write data 1 and the write clear signal 2 in units of one horizontal period, and 7 is a line delay unit that compares the phases of the write clear signal 2 and the read clear signal 6, and a phase comparison section that detects phase difference;
20 and 21 are selectors that select the amount of delay between the video omitted data 1 and the write clear signal 2, and 22 is a write address generation unit that generates a write address WcL'.

5 and 6 are explanatory diagrams for explaining the overtaking/overtaking control method in FIG. 4.

The configuration of a conventional time axis correction device is shown in FIG. 3. When a video signal has jitter, such as in a VTR, the video synchronization signal 11 separated from this video signal also has jitter. do. but.

Since there is a temporal relationship between the video signal and the video synchronization signal, the convolution clock generation unit 16 generates a write clock based on the fluctuating video synchronization signal 11, and the video is written in accordance with this. When data 1 is written into the frame memory 10 through the write control section 14', it is stored in the frame memory 10 as a jitter-free video signal. By reading this as output video data 1B from the frame memory 10 according to a fixed clock generated by the read clock generation section 15, a stable video signal is obtained.

However, the writing and reading timings of the frame memory 1 are not synchronized because they are generated using separate clocks, and the video signal obtained as an output may differ from the current data by one frame due to the jitter of the input video signal. Since the previous data is mixed (hereinafter referred to as mixing of old and new data), it is necessary for the write control unit 14' to perform overtaking control to avoid this.

Hereinafter, conventional overtaking/overtaking control will be described with reference to FIG. 4, assuming that the jitter of the video signal is within one horizontal period.

When the phase comparator 7 detects that the time interval between the omitted clear signal 2 and the read clear signal 3 is separated by one horizontal time or more, the selectors 20 and 21 select the video write data 1.
and the write clear signal 2 are selected so as to directly convey the write clear signal 2. As a result, as shown in FIG. 5 (α), the timings for reading and writing address 9 in the frame memory 10 are separated by more than one horizontal period, so that mixing of old and new data does not occur.On the contrary, the write clear signal 2 and When the time interval of the read clear signal 3 becomes one horizontal period or less, as shown in FIG. Mixing of data occurs.

Therefore, in order to avoid this, in Fig. 4.

When the phase comparator 7 detects that the phase difference between the clear signals is one horizontal period or less, the selectors 20 and 21 select a signal that has passed through the line delay 19 of the video omitted data 1 and the omitted clear signal 2. , delaying the entire write signal. As a result, as shown in FIG. 6, the writing timing to the frame memo January 0 is delayed and the reading timing is forcibly advanced to avoid mixing of old and new data due to jitter.

[Problem that the invention seeks to solve]

In the above-mentioned conventional technology, in addition to a frame memory that stores image data for one frame, it is necessary to add a line memory that stores and delays data for one horizontal period. Sara K again. There was a problem in that the capacity of the line memory had to be changed depending on the amount of jitter in the video signal.

An object of the present invention is to be able to perform overtaking and overtaking control without having an external line memory.

It is an object of the present invention to provide a time axis variation correction device that can reduce the number of parts and be made smaller.

[Means for solving problems]

The above purpose is to write image data to an unused area (an unused area in the frame memory that is not involved in storing video signals) using an unused area (empty area) writing means, and to write image data to an unused area (an unused area that is not involved in storing video signals) in the frame memory, and to This is achieved by delaying the image data by transferring the image data to the used area after a certain period of time.

[Effect]

The unused area (empty area addition means) writes data into the empty area (unused area) of the frame memory (after a certain period of time has elapsed).

Transfer image data from empty area to used area.

As a result, not only one image data is not lost, but also memory for line delay, which was required in the past, is not required.

〔Example〕

An embodiment of the present invention will be described in detail below with reference to FIGS. 1 and 2. For convenience of explanation, the amount of jitter in the video signal is
One horizontal period or less.

FIG. 1 is a block diagram showing one embodiment of the present invention.
In FIG. 1, the same numbers as those in the conventional example are given the same numbers. In addition, 4 is a write address generation unit indicating a normal write position, and 5 is a write address generator for a normal write address.
A delayed write address generation unit indicates a write position delayed by one horizontal period; 6 is an empty area address generation unit indicating a position not involved in storing a video signal in the frame memo 1J10; 8 is a delayed write address and an empty area A selector 9 switches between a normal write address and an address selected by the selector 8, and a selector 11 switches data between a used area and an unused area in the frame memory 1o. a data transfer unit 12 for controlling the data transfer unit 11;
1 is a write control section, and 17 is a memory control section.

Furthermore, FIG. 2 is an explanatory diagram for explaining the operation of the write control section in FIG. 1, where d represents image data in the current frame, and tt' represents image data of 1% of one frame. shall be. Further, m represents the address of an area (used area) that is uniquely involved in storing image data in the frame memory 10, and ru represents an area (unused area, empty area) that is not involved in storing image data. It represents the address of the area).

Hereinafter, this embodiment will be explained in detail using FIG. 1.

First, the empty area of the frame memory 10 is calculated.

In order to store one frame of the video signal of the NTSC system, which is the current standard for broadcasting in Japan, the sampling frequency must be set to 4fsc (fsc: color subcarrier -3, 58MF-12
), 910 dots x 525 books 477,750
Bits are required. Frame memory 10, 2! If MK pit RAM is used, this can be achieved with two per plane.

At this time, the empty area that does not store the video signal is approximately 45 bits (51 lines), of which 1 line (910
The area corresponding to 2 bits will be used for data delay.

Describe below the operation of overtaking/overtaking control that utilizes this empty area.

When the phase comparator 7 detects that the phase difference between the write clear signal 2 and the read clear signal 6 is one horizontal period or more, the selector 9 selects the normal write address generator 4, and accordingly the frame memory Video write data 1 is written as write data Wα in the used area 10 (address 77!). At this time, the data transfer section 11 and the data transfer control section 12 are unrelated. In this case, the timing of reading and writing address m in the frame memory 10 is separated by more than one horizontal period, so
Mixing of old and new data does not occur.

Next, the phase difference between the clear signals 2 and 3 is 1 in the 1 phase comparator 7.
The case where the period is detected to be below the horizontal period will be described. The selector 9 selects the output of the selector 8, the selector 8 switches the write address according to the data transfer control section 12, and performs overtaking and overtaking control through the data transfer section 11. The detailed operation will be explained using FIGS. 2(α) and (b).

Same, as video writing data 1, now '9s I
is written into the frame memory 10.

First, as video write data 1, data d written one horizontal period ago is read from the address indicated by the empty area address generation unit 6. Similarly, here, it is assumed that the selector 9 has already switched to the selector 8 side one horizontal period ago, and the data d read here is the operation (3) in Fig. 2 ψ) described later. This was written to the empty area address rLl one horizontal period ago. However, if this readout occurs immediately after the selector 9 is switched, the empty area address of the frame memory 10 will be read.

There is no data, or even if there is, it is unknown what kind of data it is, but this will not cause any problems due to the control described later (other empty area addresses) ,. The same goes for Sono. ) Next, the read data d is temporarily stored in the data transfer unit 11, and is written to the address m1 indicated by the delay saving address 5, and is written to the address m1 shown in the cylinder 2 diagram (f of 41).
l), t2+ operation) Next, video write data 1
46. is written to the address - indicated by the empty area address generator 6 (operation (3) in FIG. 2(b)), and the contents of the delayed write address 5 and the empty area address generator 6 are added. Then, reading is performed from the frame memory 10 using a stable clock, and output video data 18 is obtained. For example, if the read address from the read control unit 16 is 1, then the data 'o +
It will output t. ((4) in Figure 2 (A)
)) By repeating the above operations, it is possible to realize control for writing data into the frame memory 10 that has been subjected to overtaking and overtaking control.

That is, by writing the video write data 1 once in the empty area of the frame memory 10 and transferring it to the used area after one horizontal period, the timing of writing the video write data 1 to the used area is substantially delayed. Therefore, mixing of old and new data due to jitter can be avoided.

By the way, as mentioned above, immediately after switching the selector 9,
Either there is no data in the empty area address, or even if there is, it is unknown what kind of data it is. Therefore, even if these unknown data are transferred to the used area of the frame memory and then output as output video data 18, it is necessary to prevent them from being displayed on the screen.

Therefore.

In reality, the period during which the unknown data is output is exactly the vertical blanking period of the video signal (the period when it is not displayed on the screen).
The switching timing of the selector 9 is controlled so that.

Now, in this embodiment, the jitter of the input video signal is described as being one horizontal period or less, but it goes without saying that it can be expanded to the empty area of the frame memory 10, that is, about 51 horizontal periods, and the jitter in actual use is is said to be 2 to 3 horizontal periods, so it can be said that it is within a practically sufficient range.

According to this embodiment, by utilizing the empty memory area, there is no need to have an external data delay memory, and the number of parts can be reduced.

〔Effect of the invention〕

According to the present invention, in order to perform overtaking and overtaking control, K
, there is no need to have external data delay memory. For example, if we consider replacing the data write control part with a gate array, in the conventional method, when incorporating data delay memory inside the gate array, 2800 gates are required per plane to obtain one horizontal time delay. On the other hand, in the present invention, there is no need to incorporate a data delay memory inside the gate array, and the increase in the number of gates by about several hundred gates can be achieved, which is very effective in reducing the number of gates.

As described above, the number of parts can be reduced and the device as a whole can be made smaller.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram for explaining the operation of the cooling control section in FIG. 1, and FIG. 6 is a conventional time fluctuation correction device. 1. FIG. 4 is a block diagram showing the configuration of the write control section in FIG. 3, and FIGS. 5 and 6 are explanatory diagrams for explaining the operation in FIG. 4.・Video input data 2...Drawing clear signal 3...Reading clear signal 7...Phase comparator 10...Frame memory 18...Output video data Fig. 2/α) Fig. 5 So-a-s L clear body No. 7 -”-1-111 book! Shire V
Clearai No. 5 - [] Temporary n

Claims (1)

[Scope of Claims] 1. An image storage means, a write control means, and a read control means, the image data obtained from a video signal having time-axis fluctuations is written into the video signal by the write control means. Writing the written image data into a normally used area in the image storage means based on a synchronized write signal, and causing the readout control means to write the written image data into a normally used area in the image storage means based on a readout signal synchronized with a certain clock signal. In the time axis variation correction device for reading from a region to obtain a video signal whose time axis variation has been corrected, the write control means includes a phase difference detection means for detecting a phase difference between the write signal and the read signal; unused area writing means for writing the image data into an unused area other than the normally used area when the phase difference satisfies a certain condition; A time axis fluctuation correction device comprising: data transfer means for transferring image data written in an unused area of the storage means to the normally used area of the image storage means after a predetermined period of time has elapsed.