JPS59228485A - Printer device of television receiver - Google Patents

Abstract

PURPOSE:To take a copy of a picture on a television screen automatically by storing the gradational density signal of the image in an RAM temporarily on page mode access basis and reading and printing it out. CONSTITUTION:A counter 3 counts a clock 2 while an enable signal (a) is inputted. Write data 1a-1d are inputted to shift registers 4 where the gradational density signal of a TV receiver is inputted at the timing of the clock 2. A multiplexer 5 outputs the output signal of the counter 3 selectively. A video memory 6 is stored with the gradational density signal of the picture to be printed out. A row and column address strobe signal control circuit 7 supplies a row or column address signal to the memory 6. An address counter 8 outputs the high-order row address signal and low-order column address signal. An address switching circuit 9 switches the output signals according to a switching signal (b). Then, an address control circuit 12 consists of the circuit 7, counter 8, circuit 9, etc. A control circuit 13 reads the gradational density signal out of the memory 6 and outputs it to a printer 14.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a printer device for a television receiver.

Generally, when a cooking program is being broadcast on a television receiver, you may want to write down the menu list and ingredients displayed on the screen. This was extremely inconvenient as the person had to take notes on the menu list, ingredients, etc. while looking at the screen each time. Furthermore, if the cooking program mentioned above is recorded on a VTR, it can be played back again, but even in that case, it is necessary to search for the necessary screen and play it back statically, which is cumbersome. Ta.

This invention was made in consideration of the above-mentioned problems in the conventional technology, and it is possible to make a hard copy of the image displayed on the screen of a television receiver with one white key, and to obtain a normal image at that time. The purpose of the present invention is to provide a printer device for a television receiver that can be used as a printer.

First, in explaining the present invention in detail, the present invention will be explained in detail.

When trying to make a hard copy of the video from a television receiver, the normal copying speed is extremely slow compared to the video scanning speed, so the video signal is converted into a gradation density signal, which is digital data, and then stored in RAM. storage, the RAM
It is necessary to read it out and print it out on a printer. When storing the gradation density signal in the RAM, a possible method is to input the gradation density signal into a shift register and simultaneously write it into four RAMs for a plurality of pixels, for example, four pixels at a time.

However, with this writing method, when looking at one field of video, for example, if one scanning line is sampled at 1671 seconds, the number of pixels on one scanning line becomes 280 pixels, and since there are 284 scanning lines, the 16th bit R
Since there are four AMs and each pixel has 16 gradations, it is necessary to provide 4 AMs for 16 gradations, that is, 4 sets, and as a result, a 16-step RAM is required, resulting in high cost.

By the way, there is a so-called page mode access method as a RAM access method. This means that Ji first sets the row address strobe signal (hereinafter referred to as the RAS signal) to "'1".
”, one row address signal is given, t, for the row address, a column address strobe signal (hereinafter referred to as CAS signal) is periodically set to "1", and each time it becomes "1", a column address signal is given. This method specifies the address of the column by using If you write using the 64-bit RAM, it is possible to store the gradation density signal of one field of video in the 64-bit RAM, compared to the above method of writing 4 pixels at a time to 4 RAMs. te4 (1i!it's RA
M is sufficient, and cost reduction can be achieved. However, in this access method, the time when the RAS signal is “θ” is 10μ
There is also a constraint that if the column address exceeds address 256 in the bit RAM 64, the row address changes and a new row address signal must be given. Therefore, the RAS signal must be set to "1" several times within one scanning line of the video, and data cannot be written while the RAS signal is "1". If you write the data, read it out, and print it out, the pixels of the data that cannot be written will be missed and normal pixels will not be obtained.

Therefore, the present invention temporarily stores a video gradation density signal in a RAM using a page mode access method, reads it out and prints it out, and at that time inputs the gradation density signal to a shift register, Within one scanning line of video, each time a row address signal is generated, an output signal delayed by the RAS signal time from the previous output signal is selected from the shift register and applied to the RAM. This allows the image from the receiver to be automatically printed out, and also allows normal images to be obtained.

Next, a practical example of the present invention will be explained with reference to the drawings.

FIG. 1 shows a printer device for a television receiver according to an embodiment of the present invention. In the figure, 1a to 1d are serial write data that is a 4-bit grayscale signal of the video, 2 is a clock whose period is 167 nSeC, and 8 is a counter that counts clock 2 while the counter enable signal a is input. , 4 are four shift registers into which write data 1a to 1d are input at the timing of clock 2, and 6 is provided corresponding to each shift register 4, with parallel outputs QA, QB,
This is a multiplexer that selectively outputs a signal from the output corresponding to the count value of the counter 8 among the QC. Note that the shift register 4 and multiplexer 5 to which write data tctld is input are omitted from illustration.

Reference numeral 6 denotes a video memory for storing the gradation density signal of the video to be printed out, and the video memory 6 is composed of four 64-bit dynamic RAMs.

7 is a RAS signal (row address strobe signal) and a CAS signal (column address strobe 1 word) in the video memory 6.
RAS, which gives an address switching signal and generates an address switching signal.
- CAS control circuit; 8 is an address counter that counts up clock 2 and generates an 8-bit row address signal as the north address and an 8-bit column address signal as the lower address; 9 is an address switching signal; 10 is an address decoder to which a column address signal is input and outputs a signal "1" every time 82 column addresses are output; 11 is an address The signal “I 1” is synchronized with the next clock 2 by the signal “1” of the decoder 10.
The flip-flop outputs 1, and the signal "1" of the flip-flop 11 is the counter disable signal 4j3c to the address counter 8 and the RAS-CAS
This becomes a control signal d to the control circuit 7.

In the figure, a write address control circuit 12 is constituted by a portion surrounded by a one-dot chain line, and this circuit 12 controls the row address signal for the address of the same row of the video memory 6, and the first and 10μ% of the row. The column address signal is applied sequentially at every time interval that does not exceed the time interval, and the column address signal is applied while counting up except for the time when the row address signal is applied. Further, 18 is a readout control circuit for reading out the gradation density signal in the video memory 6, 14 is a printer for printing out the read signal, 15 is a row address bus, and 16 is a column address bus.

Next, the operation will be explained using FIG. 2. Here the second
The figure shows the timing of input and output signals of each part of this device.

When the copy key (not shown) is turned on in the ice bag rd, the write data 1a to 1 of the first scanning line of the video is first written to the shift register 4 at the timing of clock 2.
d is input, multiplexer 5 transfers shift register 4
QA input/output is selected, and data 1a to 1d with no delay from the QA input/output are output to the video memory 6 (
(See Figure 2(c)). On the other hand, write address control circuit 1
In 2, when the above copy key is turned on, first RAS-CA
The RAS signal is applied from the S control circuit 7 to the video memory 6 (see FIG. 2(a)), and the address switching circuit 9 switches the row address bus 15 in response to the address switching signal from the RAS-CAS control circuit 7. The row address signal from the address counter 8 is added to the video memory 6 in synchronization with the fall of the RAS signal. When the row address signal is given, the RAS-CAS control circuit 7
The CAS signal is added to the video memory 6 from (
(see FIG. 2(b)), the address switching circuit 9 selects the column address bus 16 in response to the address switching signal, and while the column address signal from the address counter 8 is counted up at the timing of clock 2, the CAS signal is The column address is added to the video memory 6 in synchronization with the falling edge of the column address (A in FIG. 2(b)).
(see), the data 1a to I'd from the multiplexer 5 with no delay are written.

Further, the column address signal from the address counter 8 is also input to the address decoder 10, and is also input to the video memory 6.
When the 82nd column address signal is applied to the 82nd column address signal and the 82nd data 1a to 1d are written, the signal of the address decoder 10 is set to "1" by the 82nd column address signal.
(see FIG. 2(e)), the signal "1" is input to the flip-flop 11, and is added to the counter 8 as a counter enable signal a, so that the counter 8 counts the clock 2, and the multiplexer 5 In response to this count value, the QB ratio output of the shift register 4 is selected with a 1-bit delay (see Fig. 2 ω)), and the video memory 6 now receives write data 1a to 1-bit delayed with a 1-bit delay from before.
1d is added (see Figure 2(g)). At this time, in the write address control circuit 12, the flip-flop 11 outputs the signal "1" in synchronization with the next clock 2 in response to the "1" signal from the address decoder 10 (see FIG. 2(f)), and the signal "1" is output in synchronization with the next clock 2. ” is counter disable signal C
The address counter 8 stops counting after counting the clock 2.

At the same time, the signal "1" of the flip-flop 11 is applied as a control signal d to the RAS-CAS control circuit 7,
A RAS signal is applied to the video memory 6 from the RAS-CA S @ control circuit 7, and the RAS-CA
The address switching circuit 9 selects the row address bus 15 in response to the address switching signal S from the control circuit 7, so that the video memory 6 is given the same row address signal as the first one. Thereafter, the CAS signal and the column address signal are applied to the video memory 6 in the same manner as described above, and the memory 6
This time, data 1a to 1d delayed by 1 bit, that is, the time during which the row address signal is applied, is written. In this way, every time 82 pieces of data 1a to 1d are written, the RAS signal becomes "1" and the row address signal for the row is given, and thereafter data 1 is delayed by 1 bit from before.
A to 1d will be written.

When the data 1a to 1d are written to the last address 255 of the addresses θ to 255 in the first row of the video memory 6, the address signal of the 255th address (this is the 256th address and is an integer multiple of 82) ), the signal of the address decoder 10 becomes "1", the signal of the flip-flop 11 becomes "1" at the next clock 2, the address counter 8 stops its counting operation at the same time as it counts 256, and At the same time as the stop, the RAS signal is added to the video memory 6, and the second
The row address signal for the second row is applied, which causes this second
The remaining data 1a of the first scanning line is placed at the address of the row.
~1d is written.

Furthermore, when the scanning line to be written changes, the output selected by the multiplexer 5 each time returns to the QA output of the shift register 4, and the data 1a to 1d of this scanning line are also written to the video memory 6 in the same manner as above. It will be.

When the data 1a to 1d of one field of the video image has been stored in the video memory 6, the readout control circuit 18 reads out the data of the one field, and the data is printed out by the printer 14.

With the device as described above, which is one example of this practical example, a hard copy of the television screen can be obtained, which is very convenient for viewers. In addition, each time a row address signal is generated, the output signal of the shift register delayed by the time of the strobe signal for providing the row address signal is selected and written to the memory, so that all gradation densities are The signal can be stored serially and in the correct location in memory, resulting in a normal image. Further, since writing can be performed in real time, the number of RAMs may be smaller than in the above-described method of converting into parallel data of a plurality of pixels and writing, and the cost will not be high.

Note that the present invention is not limited to the above embodiments, and various modifications and changes are possible. For example, if the RAS signal is
The time for "" may be a time for a plurality of bits instead of one bit. Also, the gradation density of the image may be other than 16 gradations.

As described above, according to the printer device for a television receiver according to the present invention, a hard copy of a television screen can be obtained, which is very convenient for viewers. Moreover, when obtaining the hard copy, we focused on the fact that data could be written in real time using the page mode access method, and input the gradation density signal of the picture of the television receiver into the shift register. , within one scanning line of the video, every time a row address signal is generated, an output signal delayed from the previous output signal by the strobe signal time for giving the row address is selected from the shift register and stored in the video memory. Since the gradation density signal is read out from the video memory and printed out, the image obtained as a hard copy will also be a normal image as shown on the TV screen.
Furthermore, the number of RAMs is small and the cost is low.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a printer device for television reception according to an embodiment of the present invention, and FIG. 2 is a diagram for explaining the operation of the device. 4...Shift register, 5...Multiplexer-1
6... Video memory, 12... Storage address control circuit, 18... Readout control circuit, 14... Printer. Agent Masuo Oiwa

Claims (1)

[Claims] (1) A shift register into which the gradation density signal of the video of the television receiver is input, a video memory that stores the gradation density signal of the video to be printed out, and a row address signal and a column address signal in the video memory. and a write address control circuit which sequentially applies the row address signal to the first address of the row and every address beyond the row, and counts up the column address signal except for the time when the row address signal is applied. , a strobe for supplying the output signal of the shift register to the video memory, and for supplying the row address from the previous output signal every time the row address signal is generated within one scanning line of the video; A multiplexer for outputting an output signal delayed by a signal time to the video memory, a readout control circuit for reading out the gradation density signal in the video memory, and a printer for printing out the sequentially output signals. A television receiver printer device featuring: