JPS59228483A - Printer device for television signal - Google Patents

Abstract

PURPOSE:To print out the picture of a television receiver automatically and obtain a normal picture by storing the gradational density signal of the picture in an RAM temporarily on page mode access basis, and reading and printing it out. CONSTITUTION:A counter 3 counts a clock 2 while a counter enable signal (a) is inputted. Four shift registers 4 input write data 1a-1d at the timing of the clock 2. Multiplexers 5 select the outputs of the shift registers 4 corresponding to the counter 3. A video memory 6 is stored with the gradational density signal of a picture to be printed out. A control circuit 7 for row and column address strobe signals S generates an address switching signal (b). An address switching circuit 9 supplies a row or column address signal to the memory 6. When the writing to the memory 6 is completed, a readout control circuit 13 reads an outputs data to a printer 14.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a printer device for television signals.

Generally, when a cooking program is being broadcast on a television receiver, you may want to write down the menu list and ingredients displayed on the screen. This was extremely inconvenient as the person had to take notes on the menu list, ingredients, etc. while looking at the screen each time. In addition, if the cooking program mentioned above is recorded on a VTR, it can be played back again, but even in that case, it is necessary to search for the necessary screen and play it back statically, which is a cumbersome operation. .

This invention was made in view of the conventional problems as described above, and provides a television that can automatically make a hard copy of the image displayed on the screen of a television receiver, and that also provides a normal image at that time. The purpose is to provide a signal printer device.

First, in explaining the present invention in detail, the present invention will be explained in detail.

When attempting to hard copy images from a television receiver, the normal copying speed is extremely slow compared to the scanning speed of the image, so the image signal is converted into a gradation density signal, which is digital data, and then stored in RAM. and store it in the RA
It is necessary to read it from M and print it out on a printer.

When storing the gradation density signal in the RAM, a possible method is to input the gradation density signal into a shift register and simultaneously write it into four RAMs for a plurality of pixels, for example, four pixels at a time. However, with this writing method, when looking at one field of video, for example, one scanning line is 167 n Se
When sampling with c, the number of pixels on one scanning line is 28
Since there are 0 pixels and 234 scanning lines, 16
In addition, since each pixel determines the gradation density of 16 gradations, this must be provided for 16 gradations, that is, 4 sets, and in the end, 16 RAMs are required. This results in high costs.

By the way, there is a so-called page mode access method as a RAM access method. First, the row address strobe signal (hereinafter referred to as the RAS signal) is set to ``1'' to generate one row address signal, and for that row address, the column address strobe signal (hereinafter referred to as the CAS signal) is periodically set to ``1''. 1", and each time it becomes "1", a column address signal is given to specify the address of the column. In this page mode access method, once the attached address is given, the column address is specified. Since it is possible to write in real time, if you write using this method, bit R will be set to 64.
It is possible to store a 17-yield gradation density signal of an image with 4 A M units, and compared to the above method of writing 4 pixels to 4 RAMs at the same time, only 4 RAMs are required, resulting in lower cost. can be achieved. However, with this access method, the time for which the RAS signal is 1to'' cannot exceed 10 μsec, and if the column address exceeds address 255 in the 64-bit RAM, the row address changes, so a new row address signal must be given. Therefore, the RAS signal must be set to °'1'' several times within one scanning line of the video, and the RAS
Data cannot be written while the signal is ``1'', so if you simply write data using this page mode access method, read it out, and print it out, the pixels with the data that cannot be written will be missed and normal pixels will be replaced. I can't get it.

Therefore, the present invention temporarily stores a video gradation density signal in a RAM using a page mode access method, reads it out and prints it out, and at that time inputs the gradation density signal to a shift register, Within one scanning line of video, each time a row address signal is generated, an output signal delayed by the RAS signal time from the previous output signal is selected from the shift register and applied to the RAM. This allows the image from the receiver to be automatically printed out, and also allows a normal image to be obtained.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a printer device for a television receiver according to an embodiment of the present invention. In the figure, 1a to 1d are serial write data that is a 4-bit gradation density signal of an image;
2 is a clock whose period is 167 n sec, 8 is a counter that counts clock 2 while the counter enable signal a is input, and 4 is four shifts to which write data 1a to 1d are input at the timing of clock 2. A register 5 is provided corresponding to each shift register 4, and parallel outputs QAe QB,
This is a multiplexer that selectively outputs a signal from the output corresponding to the count value of the counter 8 among the QC. Note that the shift register 4 and multiplexer 5 to which write data Ic and ld are input are omitted from illustration.

Reference numeral 6 denotes a video memory for storing the gradation density signal of the video to be printed out, and the video memory 6 is composed of four 64-bit dynamic RAMs.

Reference numeral 7 denotes a RAS signal which supplies the RAS signal (row address strobe signal) and CAS signal (column address strobe signal) to the video memory 6 and also generates an address switching signal.
CAS control circuit 8 counts up clock 2,
An address counter 9 generates an 8-bit row address signal as an upper address and an 8-bit column address signal as a lower address, and 9 supplies a row address signal or a column address signal to the video memory 6 in response to an address switching signal. An address switching circuit 10 receives a column address signal;
An address decoder that outputs a signal "1" every time 82 column addresses are output, 11 is a signal of the address decoder 10.
1", the flip-flop outputs a signal "1" in synchronization with the next clock 2. The signal +1" of the flip-flop 11 is a counter disable signal C to the address counter 8 and the RAS-CAS control circuit 7.
This becomes the control signal d for the control signal d. In the figure, the write address control circuit 12 is configured by the part surrounded by the dashed line,
The circuit 12 transmits the row address signal for addresses in the same row of the video memory 6 to the first and 10 μm addresses of the row.
It is applied sequentially at time intervals not exceeding sec, and the column 7 address signal is applied while counting up, except for the time when the row address signal is applied. Further, 18 is a readout control circuit for reading out the gradation density signal in the video memory 6, 14 is a printer for printing out the read signal, 15 is a row address bus, and 16 is a column address bus.

Next, the operation will be explained using FIG. 2. Here the second
The figure shows the timing of input and output signals of each part of this device.

When a copy key (not shown) is turned on in this device, first, write data 1a to 1d of the first scanning line of the video is stored in the shift register 4 at the timing of clock 2.
is input, the multiplexer 5 selects the QA input/output of the shift register 4, and the completely undelayed data 1a to 1d of the QA input/output are outputted to the video memory 6 (second
(See figure (c)). On the other hand, in the write address control circuit 12, when the copy key is turned on, the RAS signal is first applied from the RAS-CAS control circuit 7 to the video memory 6 (see FIG. 2(a)), and the RAS-CAS control circuit 7 The address switching circuit 9 selects the row address bus 15 in response to the address switching signal from the address counter 8, and the row address signal from the address counter 8 is added to the video memory 6 in synchronization with the fall of the RAS signal. When the row address signal is applied, a CAS signal is applied from the RAS-CAS control circuit 7 to the video memory 6 (second
(See Figure (b)), the address switching circuit 9 selects the column address bus 16 in response to the address switching signal, and while the column address signal from the address counter 8 is counted up at the timing of clock 2, the CAS signal rises. It is added to the video memory 6 in synchronization with the downlink, and the video memory 6
When the column address is determined (see A in FIG. 2(b)), the data 1a to 1d from the multiplexer 5 with no delay are written.

Further, the column address signal from the address counter 8 is also input to the address decoder 10, and is also input to the video memory 6.
When the 82nd column address signal is applied to the 82nd column address signal and the 82nd data 1a to 1d are written, the signal of the address decoder 10 is set to "1" by the 32nd column address signal.
(see FIG. 2(e)), the signal "1" is input to the flip 70 knob 11, and is added to the counter 8 as a counter enable signal a, so that the counter 8 counts the clock 2, and the multiplexer 5 selects the 1-bit delayed QB output of the shift register 4 according to this count value (see FIG. 2(d)), and the video memory 6
This time, the write was delayed by 1 bit compared to before, and it became 1a overnight.
~1d is added (see Figure 2Q)). At this time, in the write address control circuit 12, the flip 70 block 11 outputs the signal ``1'' in synchronization with the next clock 2 in response to the 1'' signal from the address decoder lo (see FIG. 2(f)), and the signal 1” is counter disable signal C
The address counter 8 stops counting after counting the clock 2. At the same time, the above flip 70 knob 11
The signal "°1" is applied to the RAS-CAS control circuit 7 as a control signal d, and the RAS-CAS control circuit 7 is stored in the video memory 6.
The RAS signal is applied from the control circuit 7, and the address switching circuit 9 selects the row address bus 15 in response to the address switching signal from the RAS-CAS control circuit 7, so that the video memory 6 stores the same data as the first one. row address signals are provided. Thereafter, the CAS signal and the column address signal are applied to the video memory 6 in the same manner as described above, and this time the memory 6 contains data 1a to 1a delayed by 1 bit, that is, the time during which the row address signal is applied. 1
d is written.

In this way, every time 82 pieces of data 1a to 1d are written, R
When the AS signal becomes "1", the row address signal for the row is given, and after that, data 1a~ which is delayed by 1 bit from before is transmitted.
1d will be written.

When the data 1a to 1d are written to the last address 255 of the addresses θ to 255 in the first row of the video memory 6, the address signal of the 255th address (this is the 256th address and is an integer multiple of 82) ), the signal of the address decoder 10 becomes °1", and the next clock 2
Then, the signal of the 7-lip flop 11 becomes °1'', the address counter 8 counts 256, and at the same time stops its counting operation.At the same time as the counting stops, the RAS signal is added to the picture frame memory 6, and this time, A row address signal for the second row is applied, and thereby the remaining data 1a to 1d of the first scanning line are written to the second row address.

Furthermore, when the scanning line to be written changes, the output selected by the multiplexer 5 each time returns to the QA output of the shift register 4, and the data 1a to 1d of this scanning line are also written to the video memory 6 in the same manner as above. It will be.

When the writing of the data 1a to 1d of one field of video into the video memory 6 is completed, the read control circuit 18 reads out the data of the one field, and the data is printed out by the printer 14.

With the apparatus of this embodiment as described above, a hard copy of the television screen can be obtained, which is very convenient for the viewer.

In addition, each time a row address signal is generated, the output signal of the shift register delayed by the time of the strobe signal for providing the row address signal is selected and written to the memory, so that all gradation densities are The signal can be stored serially and in the correct location in memory, resulting in a normal image. Also, writing can be done in real time, so 1. Compared to the above-described method of converting into parallel data of a plurality of pixels and writing the data, the number of RAMs may be smaller, and the cost will not be high.

Note that the present invention is not limited to the above embodiments, and various modifications and changes are possible. For example, when the RAS signal is
'' may be the time for multiple bits instead of one bit. Also, the gradation density of the image may be other than 16 gradations, and if the number of gradations is 2n, then the RA of the image memory 6
It is possible to form M with n pieces.

As described above, according to the printer device for a television receiver according to the present invention, a hard copy of a television screen can be obtained, which is very convenient for viewers. Moreover, when obtaining the hard copy, we focused on the fact that data could be written in real time using the page mode access method, and input the gradation density signal of the image from the television receiver into a shift register. Within one scanning line of the video, each time a row address signal is generated, an output signal delayed from the previous output signal by the strobe signal time for giving the row address is selected from the shift register and stored in the video memory. Since the gradation density signal is read out from the video memory and printed out, the image that can be used as a hard copy will be a normal image as it is on the TV screen.
Furthermore, the number of RAMs is small and the cost is low.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a printer device for television signals according to an embodiment of the present invention, and FIG. 2 is a diagram for explaining the operation of the device. 4...Shift register, 5...Multiplexer-1
6... Video memory, 12... Write address control circuit, 18... Read control circuit, 14... Printer. Agent Masuo Oiwa

Claims (1)

[Claims] (1) A shift register into which the gradation density signal of the video based on the television signal is input, a video memory consisting of a plurality of RAMs that stores the gradation density signal of the video to be printed out, and a It provides an address signal and a column address signal, and for addresses in the same row, the row address signal is given at the beginning of the row and thereafter at time intervals not exceeding a predetermined time, excluding the time when the row address signal is given. a write address control circuit that applies a column address signal while counting up;
The output signal of the shift register is supplied to the video memory, and each time the row address signal is generated within one scanning line of the video, a strobe is used to supply the row address from the previous output signal. A multiplexer that outputs an output signal delayed by a signal time to the video memory, a readout control circuit that reads out the gradation density signal in the video memory, and a printer that prints out the read signal, A television signal printer apparatus characterized in that when the number of gradations of the gradation density signal is 20, the bran in the video memory is formed by n pieces.