JPS59228486A - Printer device of television receiver - Google Patents

Abstract

PURPOSE:To take copy of a picture on a television screen automatically by storing the gradational density signal of the picture in an RAM temporarily on page mode access basis and reading and printing it out. CONSTITUTION:A counter 3 counts a clock 2 while an anable signal (a) is inputted. Write data 1a-1d are inputted to shift registers 4 at the timing of the clock 2. A multiplexer 5 output the output signal of the counter 3 selectively. A video memory 6 is stored with the gradational density signal of the picture to be printed out. A row and column address strobe signal control circuit 7 supplies a row or column address signal to the memory 6. An address counter 8 outputs the high-order row address signal and low-order column address signal. An address switching circuit 9 switches the output signals according to a switching signal (b). A control circuit 13 reads the gradational density signal out of the memory 6 and outputs it to a printer 14.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a printer device for a television receiver.

For example, when a cooking program is being broadcast on a TV receiver, you may want to write down the menu list and ingredients displayed on the screen. On the receiver, viewers had to look at the screen each time and take notes on the menu, ingredients, etc., which was extremely inconvenient. Also, if you record the cooking program on the 2nd VTR mentioned above, you can play it again, but in that case, you have to search for the necessary screen and select this? This required operations such as static playback, which was complicated.

This invention was made in view of the problems of the conventional technology, such as the overhang.
To provide a printer device for a television receiver, which can make a hard copy of the video image displayed on the screen of the television receiver at its own command, and can obtain a normal image at that time.

'First, in giving a detailed explanation of the present invention, a detailed explanation of the present invention will be given.

When trying to make a kevert copy of a video from a TV receiver, the normal copying chain is extremely slow compared to the video scanning speed, so it is necessary to convert the video signal into a gradation density signal, which is all digital data, first. Store in RAM and use the RAM
It is necessary to read it from M and print it out on a printer.

When storing the signal for increasing the gradation density in the RAM, a method can be considered in which the 1 gradation density signal is input into a shift register and written to four RAMs at the same time for n% determined pixels, for example, 4 pixels at a time. However, with this writing method, when looking at one field of video, for example, one scanning line i167 n5ec
When sampling with , the number of pixels on one scanning line is 280.
Since it is a pixel and has 284 scanning lines, it has 24 16-bit RAMs, and each pixel has a gradation density of 16 gradations. Therefore, it would be difficult to provide 16 gradations, that is, 4 sets, and a 16-round RAM would be required, resulting in high costs.

By the way, there is a so-called page mode access method as a RAM access method. First of all, this is the row address strobe signal (hereinafter referred to as the RAS signal). One row address signal is given as "1". For the row address, the column address strobe signal (hereinafter referred to as CAS signal) is periodically set to "1" and a column address signal is given each time it becomes "1". This is a method of carrying out an addressing meeting for nuclear arrays. In this page mode access method, once an address is given λ, all that is needed is to give a column address n, so real-time writing is possible.
If you use it and write 7 lines, it will be 64)
RAM 4 Gradation density signal of one field of video in Ran? It is possible to memorize the above four pixels at the same time.
Compared to the method of writing to 1 RAM, only 4 RAM is required.
Cost per animal? It can be achieved. However, in this access method, the RAS signal 975 (“O” time is 10 μsec
There is a restriction that if the column address exceeds address 255 in the RAM, the row address changes and a new row address signal must be given. Therefore, the RAS signal must be set to "1" several times within one scanning line of the video, and the
Data cannot be written while the AS signal is ``1'', so data is simply written using this page mode access method.

that? When reading and printing, pixels of data that cannot be written are omitted and normal pixels cannot be obtained.

Therefore, the present invention utilizes a video gradation density signal t page mode access method to temporarily store it in RAM, and then
R is read out and printed out, and at that time, the above-mentioned gradation S degree signal is input to the shift register. Within one scanning line of the video, every time a row address signal is generated, the nth previous signal is read out from the shift register. By selecting the output signal that is delayed by the time of the RAS signal and feeding it to the RAM, it is possible to automatically print out the image from the TV receiver, and also to obtain a normal image. This is what I did.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a printer apparatus for a television receiver according to an embodiment of the present invention. In the figure, %13 to 1d are serial write data, which is a 4-bit gradation density signal of the image.
2 is a clock with one cycle of 167 n5ec, and 8 is a clock 2? while the counter enable signal a is input. A counter for counting, 4 are four shift registers into which write data 13 to 1d are input at the timing of the clock 2, 5 is provided corresponding to each shift register 4, and a parallel output of the shift register 4 is provided. QAIQ.

This is a multiplexer that selects and outputs all signals from the outputs corresponding to the count value of the counter 8 among B, QC, . . . . Note that the shift register 4 and multiplexer 5 to which write data 1c+1d are input are omitted from illustration.

Reference numeral 6 denotes a video memory for storing the gradation density signal of the video to be printed out, and the video memory 6 is composed of four 64-bit dynamic RAMs.

Reference numeral 7 denotes a RAS signal which supplies a RAS signal (row address strobe signal) and a CAS signal (column address strobe signal) to the video memory 6 and also generates an address switching signal.
CAB control circuit 8 counts up clock 2,
An 8-bit row address signal that is an upper address, an 8-bit column address signal that is a lower address, and an address counter 9 that generates a total address signal provide a row address signal or a column address signal to the video memory 6 in response to an address switching signal. λ address switching circuit, 10 receives a column address signal;
An address decoder outputs a signal 1'' every time a column address is outputted 82sI, and 11 is a flip-flop that outputs a signal 1'' in synchronization with the next clock 2 in response to a signal 11'' from the address decoder 10. 11
The signal "'1" is the counter disable signal C to the address counter 8 and the RA S , CA
This becomes the control signal d to the S1lilj control circuit 7. In the figure, a write address control circuit 12 is constituted by a portion surrounded by a dashed line, and this circuit 12 is connected to the video memory 6.
For addresses in the same row, that row address signal sounds.

The column address signal is applied sequentially at the beginning of the row and at time intervals not exceeding 10 μsec, and the column address signal is applied while counting up except for the time when the row address signal is applied. 14 is a printer that prints out the readout signals; 15 is a row address bus; and 16 is a column address bus.

Next is the second figure? The operation will be explained using Here the second
The figure shows the timing of the human output signals of each part of the device.

When the copy key (not shown) is turned on in this device, first, the shift register 4 writes data 13 to 1d of the first scanning line of the video at the timing of clock 2.
is input 11, multiplexer 5 is input to shift register 4
QA small output is selected, and data 1a to 1d of the QA small output that are not delayed at all are output to the video memory 6 (
(See Figure 2(c)). On the other hand, write address control circuit 1
In 2, when the above copy key is turned on, -i SRA E
When the RAS signal is applied from the l-CAS control circuit 7 to the video memory 6 (see FIG. 2(a)), the RAS
, the address switching circuit 9 selects the row address bus 15 in response to the address switching signal from the OA8 control circuit 7, and the row address signal from the address counter 8 is transferred to the video memory 6 in synchronization with the fall of the RAS signal. Add. When the row address bus is applied, the CAs signal is applied from the RAS and CAS control circuit 7 to the video memory 6 (see FIG. 2(b)), and the address is changed in response to the address switching signal. The switching circuit 9 selects the column address bus 16, and the column address signal from the address counter 8 counts up at the timing of the clock 2 while the above CAs
The column address is added to the video memory 6 in synchronization with the falling edge of the signal.
b), data 1a to 1d from the multiplexer 5 with no delay are written.

Further, the column address signal from the address counter 8 is also input to the address decoder 10, and is also input to the video memory 6.
When the 82nd column address signal is given to λ and the 82nd column address is written, the above 82
The address decoder 10 is activated by the 0Mth column address signal.
If the signal is @1.V (see Fig. 2(e)), the signal “
1” is input to the flip-flop 11, and
Added to counter 8 as counter enable signal a
Then, the counter 8 counts clock 2, and the multiplexer 5 selects the QB output delayed by 1 bit from the shift register 4 according to this count (see FIG. 2(d)). Write data 1a to 1d delayed by 1 bit from before are added (Fig. 2(g)).
reference). At this time, in the write address control circuit 12, the flip-flop 11 is set to 11'' of the address decoder 10.
The signal “1” is synchronized with the next clock 2 by the signal.
i output (see FIG. 2(f)), and the signal "'1# is sent to the address counter 8 as a counter disable signal C.
In addition to n%, the address counter 8 stops counting after counting the clock 2. At the same time, the signal "1" of the flip-flop 11 is the control signal d.
As RA8. The RAS signal is applied to the video memory 6 from the RAS and CAB control circuit 7, and the address switching circuit 9 changes the row address in response to the address switching signal from the RAS and CAS control circuit 7. Bus 15? As a result of this selection, the same row address signal as at the beginning is given to the video memory 6. Thereafter, the CAB signal and the column address signal are added to the video memory 6 in the same manner as described above, and the memory 6 is now delayed by 1 bit, that is, the time during which the row address signal is applied. Data 1a to 1d are written. In this way, every time data 18 to 1d are written, the RAS signal becomes 1'' and a fixed row address signal is not given.After that, data 18 to 1d delayed by 1 bit from before is written. That will happen.

When the data 1a to 1d are written to the last address 255 of the addresses O to 255 in the first row of the video memory 6, the address signal of the 255th address (n is the 256th address and is an integer of 82) is written. ) by address decoder 100 signal 75! At the next clock 2, the signal of the flip-flop 11 becomes '1',
Is address counter 8 256? At the same time as counting, the counting operation is stopped, and at the same time as the counting is stopped, the RAS signal is applied to the interposed memory 6.
This time, a row address signal for the second row is applied, and the remaining data 1a to 1d of the first scanning line are written to the second row address by IL.

Furthermore, when the scanning line to be scanned changes, the output selected by the multiplexer 5 each time returns to the QA high output of the shift register 4, and the data 1a to 1d of this scanning line are also written to the video memory 6 in the same manner as above. It will be abducted.

When the writing of the data 13 to 1d of one field of video to the video memory 6 is completed, the readout system circuit 1
Is 8 the data of the 1 field? The readout will be printed out by the printer 14.

With the device of the present embodiment as described above, a hard copy of the television screen can be obtained, which is very convenient for viewers.

Also, every time a row address signal is generated, the corresponding row address signal? Since all the output signals of the shift register delayed by the time of the strobe signal to be given are selected and written to the jLl memory, all gradation density signals? It can be stored serially and in the correct location in memory,
A normal image is obtained. Further, since writing can be performed between the central portions, the number of RAMs may be smaller than in the above-described method of converting into parallel data of a plurality of pixels and writing, and the cost will not be high.

Note that the present invention is not limited to the above-mentioned embodiments, and various modifications and variations are possible.For example, if the RAS@ number is "1"
The time `` may be the time for one or more bits instead of one bit. Further, the gradation density of the image may be other than 16 gradations.

As described above, depending on the printer installation cost of the television receiver according to the present invention, it is difficult to obtain a hard copy of the television screen.
It is very convenient for Ls viewers. And that hard copy? When obtaining the page, use the page mode access method.
Focusing on the fact that it is possible to write data in real time, we decided to create a gradation density signal for the video of a television receiver. Every time a row address signal is generated within one scanning line of the image, the output signal from the shift register is changed from the previous output signal to the row address signal. Select all the output signals delayed by the strobe signal time to give them, and then '
i Store it in the video memory, and get the gradation density signal from the video memory? Since the image is read out and printed out, the image obtained as a hard copy is also a normal image as seen on a television screen, and furthermore, the number of RAMs is small and the cost is low.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a printer device for a television receiver according to an embodiment of the present invention, and FIG. 2 is a diagram for explaining the operation of the device. 4...Shift register, 5...Multiplexer-1
6... Video memory, 12... Write address control circuit, 18... Read control circuit, 14... Printer. Agent Masuo Oiwa

Claims (1)

[Claims] A shift register to which a digital signal corresponding to the video signal of the television is input, a video memory for storing the gradation density signal of the video to be printed out, and a row address signal and a column address signal to the video memory. a write address control circuit for providing the row address signal; and a multiplexer for outputting to the video memory an output signal that is delayed by the strobe signal time for providing an upper travel address from the previous output signal every time the row address signal is generated. - A readout control circuit that reads out the gradation density signal in the video memory and the readout signal? A printer device for a television receiver, characterized by being equipped with a printer for printing out.