JPS63224538A - Synchronizing control circuit - Google Patents

Abstract

PURPOSE:To prevent out of synchronism by providing a channel address generating circuit applying the frame synchronization detection in its own device synchronously with the frequency of an opposite device in response to a channel address. CONSTITUTION:A synchronizing control circuit 20 receives a data DT forming a frame by plural channel data and sent from an opposite device at a frequency f' and converts it into a data signal synchronously with the frequency (f) of its own device. A frame synchronization detection circuit 15 is operated at the frequency f' and applies frame synchronization to the data DT'. An address generating circuit 16 is operated at the frequency f' and generates a channel address corresponding to a channel data. A data address shifter section 21 shifts in the channel addresses corresponding to the channel data after the frame synchronization establishment and the said data in pairs synchronously with the frequency f' and shifts out synchronously with the frequency (f) and sends the result to a buffer memory 14. Thus, out of synchronism is prevented.

Description

[Detailed Description of the Invention] [Summary] A synchronization control circuit that receives data from a partner device in its own device and reproduces the data in accordance with the frequency of its own device, and detects frame synchronization within its own device. This is done in synchronization with the frequency of the other device, and after establishing frame synchronization, each channel data and the channel address corresponding to each channel data are paired and accessed to the data buffer memory, and each channel data is transferred to the corresponding channel. The data is stored sequentially at the address specified by the address, which eliminates the occurrence of synchronization and eliminates the need for synchronization and correction even if data is lost. .

[Industrial application field]

The present invention relates to a synchronization control circuit, and particularly to a synchronization control circuit for data transferred between two devices.

If there is a partner device and the own device, and the frequencies between these devices are completely synchronized with each other by slave synchronization, etc., there will be no problem even if data from the other device is imported into the own device as is. There isn't. However, for example, if both devices are installed far apart, it becomes difficult to perform dependent synchronization, and so-called independent synchronization is performed.

However, under independent synchronization, frequency deviation between devices is unavoidable, and data slips may occur when data is imported from the other device to the own device, requiring resynchronization.

A synchronous control circuit minimizes this problem.

[Prior Art] FIG. 3 is a diagram showing an example of a conventional synchronous control circuit. In this diagram, the other party's device (
data DT' (frequency f
') is passed through the synchronization control circuit 10 provided at the input stage of the own device, converted into data DT synchronized with the frequency f of the own device, and then taken into the own device. Note that the own device is represented by a dashed-dotted line frame in the figure. The data DT' transmitted from the other party's device is once buffered in the data buffer memory 14 as channel data, and then sent out within the own device as data DT of frequency f. In order to convert ' into data DT synchronized with the frequency f, the clock extraction circuit 11 first extracts a clock from the received data DT'. This clock is equal to frequency f'. And this clock (f′)
For example, serial data DT' is converted into parallel data. This is a serial/parallel converter (S/
P) 12. This parallel data is further taken into a first-in-first-out memory (FIFO) 13. That is, the frequency f' extracted from the clock extraction circuit 11 is divided into f'/8 by the l/8 frequency divider 18.
The converter (S/P) uses a clock signal with a frequency divided by
The parallel data from 12 is shifted into FIFO 13 (Sl).

Note that the 1/8 frequency divider 18 receives serial received data DT'
This is provided to handle the data as 8-bit parallel data. Thus, the received data DT' is continuously sent into the FIFO 13 at its own frequency (f'/8). Then, this sent data is synchronized with the frequency f of the own device and F! Shifted out from F013. That is, the oscillator 17 within the device itself oscillates at a frequency f, and a clock signal having a frequency divided by f/8 by the 1/8 frequency divider 19 is applied to the shift out terminal (So) of the FIFO 13.

Here, channel data of frequency f is sequentially sent out from the FIFO 13 and temporarily buffered in the data buffer memory 14. At this time, the address generation circuit 16 that generates a channel address to specify which address in the data buffer memory 14 should be stored is driven, but the channel address from this address generation circuit 16 is The output is incremented by one. A certain timing is when frame synchronization is established, and for this purpose a frame synchronization detection circuit 15 is provided. Normally, multiple pieces of channel data are transferred in frame units, so it is transferred to the buffer 14 after confirming that the predetermined frame pattern matches the frame pattern detected from each received frame and that frame synchronization is achieved. Start a store. Therefore, the frame synchronization detection circuit 15 detects that the above-mentioned frame synchronization has been established, performs a mask reset (MR) on the FIFO 13, resets the address generation circuit 16 (R), and further resets the data buffer memory 14 in chip select mode. (CS) to initialize these. From this initialization, the original
Synchronous control at own device frequency f starts.

In this case, the synchronization control in the frame synchronization control circuit 15 is performed in synchronization with the own device frequency r, and the operation of the address generation circuit 16 is also performed in synchronization with the own device frequency f.

[Problem that the invention seeks to solve]

In the conventional synchronous control circuit described above, it is inevitable that a so-called data slip occurs due to a frequency deviation (positive or negative) between frequencies f and f'. This data slip is first-in-first-out memory (FIF).
O) Appears as an overflow or underflow in the amount of data in 13, resulting in data loss. If such data is missing, the frame synchronization detection circuit 15 will lose frame synchronization. In this case, the above-described initialization is performed in order to re-establish frame synchronization, and the data stored in the data buffer memory 14 is wasted. Furthermore, re-establishing the synchronization takes a considerable amount of time, effectively halting data transfer. Such problems occur quite often. This is because, unless an expensive atomic oscillator or the like is used, the above-mentioned frequency deviation appears more or less constantly.

The present invention was made in view of the above problems, and is designed to prevent frame synchronization from occurring in principle.
Even if the FIFO overflows or underflows due to frequency deviation, this will have no effect on the FIFO.
The purpose of this is to provide a synchronization control circuit that only applies to the data stored in the channel O, and allows other channel data to still be effectively transferred.

[Means for solving problems]

FIG. 1 is a principle block diagram of the synchronization control circuit according to the present invention. In this figure, data DT' from the other device is input to the frame synchronization detection circuit 15 and also to the data/address shifter section 21. Ru. Further, a channel address corresponding to each channel data is output from the address generation circuit 16 which is reset upon establishment of frame synchronization.

The address is also input to the data/address shifter section 21.

The frame synchronization detection circuit 15 and the address generation circuit 16 operate after the frequency f' of the data DT'. Further, the data/address shifter section 21 shifts in the channel data and the channel address as a pair and in synchronization with the frequency f'.

Each pair of channel data and channel address that has been shifted in is shifted out at the frequency f of the own device and applied together to the data buffer memory 14, and each channel data is designated by the channel address that is paired with it. Store to address.

[Function] The difference between the synchronous control circuit 20 of the present invention and the conventional synchronous control circuit 10 is that even if data DT' from the other device enters the own device, the frequency f of the own device is used. Frame synchronization is established without changing the frequency f' of the other party's device, and a channel address is also generated. Therefore, since the frequency f is not involved at all in the steps up to this point, the desynchronization due to the frequency deviation described above cannot occur in principle.

Therefore, no slip occurs between the channel data and the corresponding channel address. Furthermore, these channel data and channel addresses are shifted into a pair into the data/address shifter section 21. In this way, even if the FIFO overflows or underflows due to a frequency deviation between the frequency (f') and the frequency (f), there is no need to resynchronize, and the data stored in the FIFO is discarded. However, it does not stop the transmission of other channel data. In this way, the inconvenience of needlessly discarding data stored in the data buffer memory 14 is eliminated, and the inconvenience of stopping data transfer for a long time and resynchronizing is also eliminated.

〔Example〕

FIG. 2 is a diagram showing an embodiment of the synchronous control circuit according to the present invention. Note that components similar to those described above are designated with the same reference numbers or symbols. When compared with the conventional synchronous control circuit 10, the synchronous control circuit 20 shown in the figure has the following characteristics:
The conventional PIFO 13 becomes the data section in the data/address shifter section 21 of the present invention, and the conventional FIFO 13
Furthermore, a FIFO (address section) for channel addresses is integrated into the system, and both the frame synchronization detection circuit 15 and the address generation circuit 16 operate at the frequency f' of the other device. I understand. In this embodiment, the data/address shifter section 21 is configured with a FIFO, but in addition to this, a RAM (random access
It is also possible to configure it with 5 sensors.

〔Effect of the invention〕

As explained above, according to the present invention, loss of synchronization cannot occur in principle, so it is almost possible to stop data transfer for a long time and resynchronize. Alternatively, even if an underflow occurs, the data in the data buffer memory 14 may not be discarded, but only the data stored in the FIFO may be invalidated.

[Brief explanation of drawings]

FIG. 1 is a principle block diagram of a synchronous control circuit according to the present invention, FIG. 2 is a diagram showing an embodiment of the synchronous control circuit according to the present invention, and FIG. 3 is a diagram showing an example of a conventional synchronous control circuit. DESCRIPTION OF SYMBOLS 11... Clock extraction circuit, 14... Data buffer memory, 15... Frame synchronization detection circuit, 16... Address generation circuit, 17... Oscillator, 20... Synchronization control circuit, 21...・Data/address shifter section, DT, DT
'...Data, f, f'...Frequency. Procedural amendment February 1988/I Date Kunio Ogawa, Commissioner of the Japan Patent Office1, Indication of the case, Patent Application No. 57916 of 19882, Name of the invention Synchronous control circuit 3, Person making the amendment Related Patent applicant name (522) Fujitsu Ltd. 4, agent address 105 IO-5, Toranomon-chome-8, Minato-ku, Tokyo.
Drawing to be amended (Fig. 1) 6゜Contents of correction The drawing (Fig. 1) will be corrected as shown in the attached sheet, and f at the left end of the drawing will be corrected to f'. 7. List of attached documents

Claims (1)

[Claims] 1. Receive data (DT') that is transmitted from the other party's device at frequency (f') and form a frame of multi-channel data, and synchronize the data (DT) with the frequency (f) of the own device. In the synchronous control circuit that converts the data (DT
a frame synchronization detection circuit (15) that performs frame synchronization with respect to the frequency (f'); and an address generation circuit (16) that operates at the frequency (f') and generates a channel address corresponding to each of the channel data. , Pair the channel data after frame synchronization is established with the channel address corresponding to the channel data, and shift it in in synchronization with the frequency (f'),
Data that is shifted out in synchronization with the frequency (f).
an address shifter section (21), and data for temporarily storing the channel data shifted out from the data/address shifter section (21) at an address specified by the channel address shifted out as a pair with the channel data. Buffer memory (14)
A synchronous control circuit comprising: