JP2859241B2 - ATM switch resynchronization establishment circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a means for preventing cell discard at the time of system switching in a redundant ATM switch, and more particularly to a resynchronization establishing circuit when synchronization is lost at the time of switching.

[0001]

2. Description of the Related Art FIG. 6 shows a duplex communication path 2A, 2B.
FIG. 3 is a diagram for explaining control of system switching of a communication path unit of a duplex ATM switch in a conventional technique including a communication line unit 1A and an output line unit 5A. In the figure, the system switching between the communication path units 2A and 2B is performed by the frame synchronization establishing means 3A monitoring the phases of the frame synchronization signals of both systems, and when there is a difference in the cell input timing, the phases are adjusted. Switching is performed when the phases match, thereby eliminating cell discarding and duplication. (JP-A-5-560
No.65)

However, in the case of the configuration shown in FIG. 3, the selector 4 for receiving the cell shown in FIG.
If the phase of the clock is shifted instead of the frame synchronization in A, there is a possibility that the data of the clock fluctuation cell is destroyed. As described above, in the conventional technology, there is a possibility that data in a cell may be destroyed when clock switching of a line unit cannot be performed during system switching of a communication path unit.
Therefore, at the time of system switching of the redundant ATM switch, it has been attempted to switch the system while establishing synchronization between the two systems. Therefore, there is a problem that the circuit scale is increased in order to establish the frame synchronization between the two systems in the communication path unit because the system switching is performed without instantaneous interruption while the synchronization is established.

According to the present invention, when a system of a redundant ATM switch is switched, the switching is asynchronously performed while the synchronization is temporarily removed, and the synchronization is re-established, thereby not only discarding or duplicating cells but also destroying cell data. It aims to prevent the possibility.

[0003]

The resynchronization establishment circuit of the present invention loses synchronization of high-speed serial communication when switching the input clock of the line section during system switching, and it takes time to establish resynchronization. And re-synchronization is established by transmitting a pseudo cell before transmitting a valid cell. Specifically, means for intentionally de-synchronizing the high-speed serial communication unit (17 in FIG. 2)
And means for transmitting a pseudo cell shorter than 53 bytes to establish resynchronization (18 in FIG. 2).

When switching the system of the input clock of the line section,
By stopping the transmission of the cell synchronization signal, the serial signal receiving section of the high-speed serial communication section enters a synchronization establishment waiting state. According to the present invention, resynchronization can be established only by receiving the cell synchronization signal without being affected by the fluctuation of the input clock.

[0005] By adding a pseudo cell transmitting circuit to the transmission control section, a pseudo cell shorter than 53 bytes can be transmitted to the line section. For this reason, resynchronization can be easily established in the line section, and cells shorter than 53 bytes are discarded in the receiving FIFO, so that undefined cells are not transmitted to the network.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, in a preferred embodiment of the present invention, there is confounding between a communication path unit 1 and a line unit 8 in a duplicated ATM switch. The present invention relates to a system switching operation of the communication path unit 1. FIG. 1 shows a high-speed operation of the transmitting side of the communication path unit 1 and the receiving side of the line unit 8 of the new working system which has newly become the active system due to system switching. It is configured by a serial communication unit 7.

The communication path unit 1 includes a transmission control unit 2 and a transmission-side FIF.
O3, a serial signal transmission unit 4. The transmission control unit 2 performs a function of performing cell transfer in a 54-byte cycle, a function of accumulating cells in the transmission-side FIFO 3 at the time of system switching, and a synchronization control of the high-speed serial communication unit. The transmission FIFO 3 stores cells at the time of system switching,
The serial signal transmitting unit 4 converts the 8-bit ATM cell from parallel to serial, adds synchronization information to the head of the cell, and transmits the cell to the line unit 8.

The line section 8 comprises a serial communication receiving section 9, a receiving control section 10, a receiving FIFO 11, and a clock control section 12. The serial signal receiving section 9 has a function of converting a serial signal received from the communication path section into an 8-bit ATM cell, and a function of selecting a serial signal from both communication path sections. The reception control unit 10 has a function of determining the synchronization information at the head of the input cell and a function of monitoring the synchronization of the high-speed serial communication unit. Receiver F
The IFO 11 has a cell discard function.

[0009] A series of operations at the time of system switching of the communication path section are as follows.
After the old active communication path unit has transmitted all cells to the line unit 8, transmission of the cells stored in the transmission FIFO 3 of the new active communication line unit 1 to the line unit 8 is started. I do.

[0010] Normal control of the communication path section is performed by a transmitting FIFO.
The information written in 3 is read by the cell synchronization signal A5. The transmission side FIFO 3 transmits a cell n hours after the cell synchronization signal A5 is input. Since the high-speed serial communication unit 7 adds synchronization information for s time to the head of the cell, the serial signal transmission unit 4 In this case, cells of the time n + s are input. For this reason, the cell synchronization signal B6 to be output n hours after the cell synchronization signal A5 is subtracted from the s time, and is output from the transmission control unit 2 ns time later, thereby enabling cell transfer.

[0011] The control at the time of system switching of the communication path unit 1 of the new active system is performed by stopping the cell synchronization signal A5, and simultaneously stopping the cell synchronization signal B6. After the cell transmission from the old working system is completed, the transmission control unit 2 sends out the cell synchronization signal B6. Next, the cell synchronization signal A earlier than the normal cycle
By transmitting 5, the pseudo cell is transmitted to the line section 8. In the normal cell transfer of the line section 8, the serial signal receiving section 9 determines the data of the s time indicated by the cell synchronization position indication signal 13 with respect to the reception control section 10 so that the cell is in a state where synchronization is established. Recognizing that there is, the cell is transferred by transmitting the cell synchronization signal C16 to the receiving FIFO 11. Even if the synchronization is established, if the synchronization information does not match, the cell synchronization signal C16 is not transmitted.

The control at the time of system switching of the line unit 8 is performed after all cells from the old working system are received, and then the serial signal receiving unit 9 is controlled.
The clock control unit 12 switches between the communication path system and the clock system. At this time, since the cell synchronization signal B6 is not transmitted in the communication channel unit 1 of the new active system, the synchronization control signal 15 is transmitted from the reception control unit 10 to the serial signal reception unit 9. Next, when a pseudo cell is received, the serial signal receiving unit 9
Transmits a synchronization state notification signal 14 to the reception control unit 10. Receiving control unit 10 receiving synchronization state notification signal 14
Releases the synchronization wait signal 15 and resets the high-speed serial
Is established. Since the pseudo cell is shorter than the normal cycle, it is discarded by the receiving FIFO 11.

Next, the operation of the embodiment of the present invention will be described with reference to FIG.

FIG. 3 is a flowchart for explaining the operation at the time of system switching of the communication path unit, and simultaneously shows the synchronous relationship between the communication path unit (old working system and new working system) and the line unit.

When the old active system S1 completes cell transmission to the line unit S2, the communication path unit switches to the system switching S3.
Perform The new active system in the communication path unit at the time of system switching performs cell accumulation S6 and stops the synchronization signal for the line unit.
6, the communication path unit and the line unit are in the asynchronous state S3 even after the system switching is completed. Next, a pseudo cell is transmitted from the new working system S7 of the communication path section to the line section S4 to establish resynchronization, and the new working system S8 of the communication path section is switched to the line section S5.
To start sending cells to.

Next, details of the embodiment of the present invention will be described with reference to FIG.

The communication path section shown in FIG. 1A includes a transmission control section 2, a transmission FIFO 3, and a serial signal transmission section 4.

The transmission control unit 2 includes a cell synchronization signal transmission circuit 17
The cell synchronizing signal transmitting circuit 17 transmits a cell synchronizing signal A5 of one pulse in a 54 clock cycle, and transmits a cell synchronizing signal B6 nine clocks later. At the time of system switching, transmission of the cell synchronization signal A5 and the cell synchronization signal B6 is stopped, and cells are stored in the transmission FIFO3. At this time, the pseudo cell transmitting circuit 18 transmits a synchronization signal of one clock pulse when the system switching signal 19 is input. 27 clocks later, the cell synchronization signal transmission circuit 17 starts operating. This gives 27
The pseudo cell having a short byte is transferred to the serial signal transmitting unit. Immediately after this, the cells stored in the transmission FIFO start to be read.

The line section (B) includes a serial signal receiving section 9,
Reception control unit 10, reception FIFO 11, clock control unit 1
2 is comprised.

The reception control unit 10 is composed of a cell determination circuit 20 and a synchronization monitoring circuit 21. The reception control unit 10 verifies the synchronization information of the first byte of the input 54-byte cell, and if valid, transmits a cell synchronization signal C16. If invalid, the cell synchronization signal is not transmitted. When the synchronization state notification signal 14 transmitted from the serial signal receiving unit 9 is in an asynchronous state, the synchronization monitoring circuit 21 stops the operation of the cell determination circuit 20 and does not transmit the cell synchronization signal C16. When the synchronization state notification signal 14 changes from the asynchronous state to the synchronous state, the synchronization monitoring circuit 21 releases the synchronization wait signal 15. The serial signal receiving unit 9 from which the synchronization waiting signal 15 has been released can perform cell transfer. The cell discard processing circuit 19 in the receiving FIFO 11 discards a cell for which the cell synchronization signal C16 has not been transmitted or a pseudo cell shorter than 53 bytes, which is determined as an invalid cell by the cell determination circuit 20. The clock control unit 12 receives the clocks 26 from the communication path units of both systems, and the selector 22
5, the same system as the serial signal 24 is selected.
When the clock system is switched, the output clock 27 of the PLL 23 fluctuates, and the fluctuating clock 27 is input to the serial signal receiving unit 9, so that the operation becomes unstable.

The operation of the embodiment of the present invention will be described in detail with reference to FIGS.

Referring to the time chart of the communication path section of FIG. 4A, the transmission control section 2 of FIG.
53 bytes are transmitted 10 times after the cell synchronization signal A5 is transmitted for 54 clock cycles for 54. Since the cell synchronization information is inserted into the first one byte in the serial signal transmitting unit 4, it is necessary to shift the head of the cell data and the cell synchronization signal B6 by one clock. Therefore, the cell synchronization signal B is transmitted 9 clocks after the cell synchronization signal B6 in a 54 clock cycle. At the time of system switching, first, the cell synchronization signal B6 is transmitted to the serial signal transmission unit 4, and thereafter, the normal cell synchronization signal A5 and the cell synchronization signal B6 are transmitted within 54 clock cycles within a time shorter than 53 clock cycles. , A pseudo cell is transmitted to the line unit.

Referring to the time chart of the line section in FIG. 4B, since the cell synchronization signal B7 of the communication path section of the new active system is stopped at the time of system switching, the serial signal receiving section 9
And the system selection signal 25 input to the clock control unit 16
Changes, and the synchronization state notification signal 14 is released. After that, the new active communication path unit 1 starts cell transfer.
When the synchronization position display signal 13 starts to be input, the synchronization waiting signal 15 is released and synchronization is established. At this time, the reception control unit 10 enters a synchronized state by receiving the pseudo cell.

Next, a second embodiment of the present invention is shown in FIG.

Each configuration is the same as that of the preferred embodiment, and the synchronization status notification signal 14 output from the serial signal receiving section 4 in the line section is input to the transmission control section 2 in the communication path section to establish synchronization. If not, the transmission of the cell synchronization signal A5 is stopped to prevent the cell transfer from the communication path section to the line section. Further, the cell synchronization signal B6 transmitted from the transmission control unit 2 in the communication path unit to the serial signal transmission unit 4 is always output, and pseudo cells are not transmitted at the time of system switching.

As a result, if synchronization has not been established, the communication path unit does not transfer cells to the line unit. If the synchronization at the time of system switching is lost, it takes an indefinite time to establish resynchronization, but cell data is not lost.

[0027]

The first effect is that it is easy to establish resynchronization at the time of system switching of an ATM switch using high-speed serial communication. As a result, the time required for system switching is reduced.

The reason is that if the clock system is switched while the synchronization is established, clock fluctuations occur, and it takes time for the clock system to stabilize. Therefore, the clock system is switched while the synchronization is released, and the pseudo cell is transmitted. This is because re-synchronization can be established instantaneously.

The second effect is that cell transfer is not performed when synchronization is not established. Thereby, cell discard at the time of system switching can be prevented.

The reason is that it is difficult to detect the fluctuation of the clock, and the timing for performing the cell transfer must be set to a fixed value. Therefore, there is no guarantee that the data is always synchronized and the data of the cell is not destroyed.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an embodiment of a resynchronization establishment circuit of the present invention.

FIG. 2A is a configuration diagram showing in detail an embodiment of a resynchronization establishment circuit for a communication channel unit according to the present invention. FIG. 3B is a configuration diagram showing in detail an embodiment of a resynchronization establishment circuit for a line unit according to the present invention.

FIG. 3 is a flowchart showing the operation of the embodiment of the resynchronization establishment circuit of the present invention.

FIG. 4A is a time chart showing the operation of the embodiment of the resynchronization establishing circuit of the communication path unit according to the present invention. (B)
4 is a time chart showing the operation of the embodiment of the resynchronization establishing circuit of the line section of the present invention.

FIG. 5A is a configuration diagram of a communication path unit according to another embodiment of the present invention. (B) is a configuration diagram of a line unit according to another embodiment of the present invention.

FIG. 6 is a configuration diagram of a communication path unit showing a conventional serial communication circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Communication part (new working system) 2 Transmission control part 3 Transmission FIFO 4 Serial signal transmission part 5 Cell synchronization signal A 6 Cell synchronization signal B 7 High-speed serial communication part 8 Line part 9 Serial signal reception part 10 Reception control part 11 Receiving FIFO 12 Clock control unit 13 Synchronization position display signal 14 Synchronization status notification signal 15 Synchronization wait signal 16 Cell synchronization signal C 17 Cell synchronization signal transmission circuit 18 Pseudo cell transmission circuit 19 System switching signal 20 Cell determination circuit 21 Synchronization monitoring circuit 22 Selector 23 PLL 24 Serial signal 25 System selection signal 26 Clock from communication path unit 27 Output clock 1A Input line unit 2A Communication path unit (1) 2B Communication path unit (2) 3A Frame synchronization establishing unit 4A Selector 5A Output line unit S1 Cell transmission S2 Cell reception S3 Switching S4 Synchronization establishment S5 Cell Shin S6 cell storage synchronizing signal stop S7 pseudo cell transmission S8 cell transmission

Claims (1)

(57) [Claims] In a system switchover of a duplexing ATM switch having confounding between a communication path section and a line section, system switching is performed by removing synchronization between the communication path section and the line section. A resynchronization establishment circuit characterized in that a resynchronization is forcibly established by sending a pseudo cell from a mobile station to a line unit, thereby preventing cell discarding and shortening the time required for system switching.