JPH09162880A - Cell phase synchronization protection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To protect cell phase synchronization even if the lack of one cell and the overlap of the calls occur, to restore synchronization after a protection period terminates and to reduce the occurrence of fluctuation at cell intervals by means of re-synchronization by receiving the output of a cell comparison means and controlling the phase synchronization of the cells in a cell phase synchronization means. SOLUTION: The cells of a '0' system and a '1' system, which are outputted from the cell phase synchronization part 1, are inputted to the cell comparison part (1) 2, and data of the cells of the both systems are compared. Then, whether they are matched or not is judged. The output is inputted to an output selection part 3 and either output is outputted as a present system output and the other as a standby system output with output system selection signals from outside. The cell comparison part (2) 11 compares the output cell of the standby system and the output cell obtained by delaying the output cell of the active system by one cell in a cell buffer 12. The output is inputted to a read control part 10 in the cell phase synchronization part 1 and the read control part 10 receives the output and executes a processing for restoring synchronization within the synchronization protection period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell phase synchronization protection circuit, and more particularly to a switching control cell phase synchronization protection circuit for a duplex package of a device having a redundant configuration or a reception package when switching between transmission lines. Regarding

[0002]

2. Description of the Related Art When a cell phase synchronization loss is detected in a phase synchronization unit for switching without interruption in a duplex system, a synchronization control unit in the phase synchronization unit advances the main signal input for resynchronization. Since the delay inserted in the delaying system is removed and the delay is inserted in the proceeding system, the cell interval of the delaying system fluctuates each time.

FIG. 5 is a diagram showing a configuration example of a conventional circuit.
In the figure, reference numeral 1 is a cell phase synchronization unit for inputting 0-system cells and 1-system cells to synchronize the cell phases, and 1a is a cell phase control unit provided in the cell phase synchronization unit 1. Reference numeral 2 is a cell comparison unit for performing phase comparison between 0-system cells and 1-system cells, and 3 is an output selection unit for selecting an active system in response to an output system selection signal from the outside. Reference numeral 4 is a protection counter for counting the non-coincidence signals from the cell comparison unit 2, and the output thereof is input to the cell phase synchronization unit 1. The operation of the circuit configured as described above will be described below.

The cell transmitted from the transmitter is branched into a 0 system and a 1 system. Since the 0-system and the 1-system take different paths, the phases of the cells of both systems entering the cell phase synchronization unit 1 are not necessarily the same. In this circuit, if the protection counter 4 is not provided, the synchronization control unit 1a in the cell phase synchronization unit 1 performs the resynchronization operation each time a phase mismatch occurs between cells of both systems. That is, the delay inserted in the advanced system is removed, and the delay is newly inserted in the advanced system. Therefore, in this case, the cell interval of the system in which the cell delay is performed fluctuates every time cell asynchronization occurs. This is a problem if this system is the current system.

The protection counter 4 is used for forward protection and outputs an out-of-synchronization detection signal when a cell mismatch occurs n times in a row. Synchronization control unit 1a
Performs resynchronization processing when this out-of-synchronization detection signal is generated.

FIG. 6 is an explanatory diagram of synchronization protection by a conventional circuit. (A) shows the operation when there is a cell data error in the backup system, and (b) shows the operation when there is a cell sequence inversion in the backup system. First, (a) will be described. First, the synchronization is established. When a mismatch occurs, the synchronization protection period starts. The synchronization protection period is 7 steps. First, the data D of the standby system (1 system) should be D, but D'becomes a data error. However, since the subsequent cells match within the synchronization protection period, synchronization is reestablished at the end of the synchronization protection period, and fluctuation due to resynchronization does not occur.

Next, (b) will be described. First, the synchronization is established. When a mismatch occurs, the synchronization protection period starts. In this case, the spare cells D and E are reversed, and a mismatch occurs twice in a row. However, since the cells of the active system and the standby system start to coincide with each other again within the synchronization protection period, synchronization is reestablished at the end of the synchronization protection period, and fluctuation due to resynchronization does not occur.

FIG. 7 is an explanatory diagram when synchronization protection cannot be performed by a conventional circuit. (A) is a case where the standby system (1 system) cell is missing, and (b) is a case where the standby system cell is duplicated.
(A) will be described. In the figure, cell D is missing. For this reason, during the synchronization protection period, they all do not match and the synchronization is lost. Therefore, in this case, the synchronization is always lost and the resynchronization is performed.

In the case of (b), there is a duplicate cell in the backup system cell, and also in this case, there is no match during the synchronization protection period, and the synchronization is lost. Therefore, in this case, the synchronization is always lost and the resynchronization is performed.

[0010]

As described above, in the conventional circuit, when one cell is lost or duplicated in the standby system, the synchronization is always lost and the cell interval fluctuates.

The present invention has been made in view of the above problems, and protects the cell phase synchronization even when one cell is lost or duplicated in the standby system in the hitless switching of the redundant configuration. An object of the present invention is to provide a cell phase synchronization protection circuit capable of recovering synchronization after the end of the protection period and reducing fluctuations in cell spacing due to resynchronization.

[0012]

FIG. 1 is a block diagram showing the principle of the present invention. The same components as those in FIG. 5 are denoted by the same reference numerals. In the figure, 1 is a cell phase synchronization means for receiving cell inputs of 0 system and 1 system to perform cell phase synchronization control, and outputting cells as an active system and a standby system, and 2 is a first for comparing cells of both systems. A cell comparing means, 12 is a cell delaying means for delaying a cell by receiving an active system output of the output of the cell phase synchronizing means 1, and 11 is an output of the cell delaying means 12 and the cell phase synchronizing means 1. It is a second cell comparison means for comparing the outputs of the standby system among the outputs. Reference numeral 10 is a read control means for receiving the output of the second cell comparison means 11 and for controlling the phase synchronization of the cells by the cell phase synchronization means 1.

According to the structure of the present invention, when the read control means 10 is missing a cell, the read operation is stopped in the backup system, and in the case of cell duplication, one read cell is read out so as to be discarded. Take control. As a result, even if one cell is lost or duplicated in the backup system, synchronization can be restored after the synchronization protection period ends, and fluctuations in cell spacing due to resynchronization can be reduced.

In this case, the cell delay means 12
Is the read control means 10 which receives the output of the second cell comparison means 11 by delaying the output of the active system by one cell.
Is characterized by protecting the synchronization by reading or discarding the spare cells after the end of the synchronization protection period according to the comparison result during the synchronization protection period.

As a result, even if one cell is lost or duplicated in the backup system, synchronization can be restored during the synchronization protection period, and the occurrence of cell interval fluctuation due to resynchronization can be reduced.

Further, there is provided a first CRC calculation unit for performing a CRC calculation for the working system output and a second CRC calculation unit for performing a CRC calculation for the standby system output, and these first and second CRC calculation units are provided. The output of the unit is compared by the second cell comparison means.

According to the structure of the present invention, by performing the CRC operation on both cells of the cell comparing means, the number of bits of the cell comparing means can be reduced and the hardware of the cell delay means can be reduced. .

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 2 is a block diagram showing an embodiment of the present invention. The same parts as those in FIGS. 1 and 5 are designated by the same reference numerals. In the figure, reference numeral 1 denotes a cell phase synchronizing unit which receives a 0-system cell input and a 1-system cell input and performs phase synchronization and outputs the cell. A reference numeral 10 denotes a second comparing means provided in the cell phase synchronizing unit 1. A read control unit as a read control unit that receives the output of the cell comparison unit 11 and controls the phase synchronization of the cell in the cell phase synchronization unit 1 as the cell phase synchronization unit. 2 receives the output of the cell phase synchronization unit 1 and performs a phase comparison between the 0-system cell and the 1-system cell (hereinafter referred to as cell comparison unit 1). 3 receives the output of the cell comparison unit 1. 0 according to the output system selection signal
It is an output selection unit that outputs either the system or the 1 system as the active system.

Reference numeral 12 designates a 1-cell buffer as a cell delay means for delaying the active system output of the output selector 3 by 1 cell, and 1
Reference numeral 1 is a second cell comparing section (hereinafter referred to as cell comparing section 2) as a cell comparing means for performing cell phase comparison between the output of the cell buffer 12 and the output of the spare system output from the output selecting section 3. The output of the cell comparator 2 is the read controller 1
0 has been entered. Reference numeral 4 is a protection counter that counts the mismatch output of the cell comparison unit 1, and the output thereof is output as an out-of-sync detection signal. The operation of the circuit thus configured will be described as follows.

The 0-system cell and the 1-system cell enter the cell phase synchronization unit 1. The cell phase synchronization unit 1 performs cell phase synchronization so that the same cell is input to the cell comparison unit 1. The cells of both systems output from the cell phase synchronization unit 1 enter the cell comparison unit 1. The cell comparison unit 1 compares data of cells of both systems,
Determines whether they match or not. If the result of determination is that they do not match, a mismatch signal is output to the protection counter 4. The protection counter 4 has an initial value of 0 and starts counting from 1. The output of the cell comparison unit 1 enters the output selection unit 3, and either the 0 system or the 1 system is output as the active system in response to an output system selection signal from the outside. The rest is output as a backup system.

The cell comparison unit 2 compares the output cell of the standby system with the output cell of the active system delayed by one cell in the cell buffer. The output of the cell comparison unit 2 enters the read control unit 10 in the cell phase synchronization unit 1. The read control unit 10 receives the output of the cell comparison unit 2 and performs processing for recovering synchronization within the synchronization protection period (details will be described later).

FIG. 3 is an explanatory diagram of the synchronization protection operation of the present invention. (A) shows the case where there is a missing cell in the standby system. Here, 0 system is the active system, 1 is the output system selection signal.
The system is used as a backup system. Initially synchronization was established,
The cells A to C are synchronized. Here, assuming that the cell D of the spare system is missing, the working system becomes D and the spare system becomes E, the phases do not match, the cell comparison unit 1 outputs a mismatch signal, and the synchronization protection period starts.

On the other hand, the current system output is delayed by one cell by the one cell buffer 12 and is output. The output of the one cell buffer 12 is compared with the standby system output, and as a result, the cell comparison unit 2 does not match. . The read control unit 10 receives the outputs of the cell comparison unit 1 and the cell comparison unit 2, and when both the cell comparison units 1 and 2 do not match during the synchronization protection period, the read control unit 10 reads to the standby system. Stop and add a delay. In (a), a delay of one cell is added at the cell K. As a result, cells output after the cell synchronization protection period has elapsed are output in order from K in both the active system and the standby system, and synchronization can be achieved. According to this embodiment, it is possible to recover synchronization after the synchronization protection period ends, and reduce the occurrence of cell interval fluctuation due to resynchronization.

(B) shows a case where the backup system has overlapping cells. Here, the 0 system is the active system and the 1 system is the standby system according to the output system selection signal. Initially, synchronization is established, and cells A to C are synchronized. here,
Assuming that the spare cell C is duplicated, the active cell is D,
The backup system becomes C, the phases do not match, the cell comparison unit 1 outputs a mismatch signal, and the synchronization protection period starts.

On the other hand, the current system output is delayed by one cell by the one cell buffer 12 and is output. As a result of comparing the output of the one cell buffer 12 with the standby system output, the cell comparison unit 2 determines that the synchronization protection period has elapsed. Inside is a match. Read control unit 1
0 receives the outputs of the cell comparison unit 1 and the cell comparison unit 2, and if the cell comparison unit 1 does not match and the cell comparison unit 2 matches during the synchronization protection period, the cell is set to 1 for the standby system. The read control is performed so that the data is discarded. In (b), the spare cell J is discarded. As a result, the cells output after the cell synchronization protection period has elapsed are K in both the active system and the standby system.
Are output in order and are synchronized. According to this embodiment, synchronization is restored after the synchronization protection period ends,
It is possible to reduce fluctuations in cell spacing due to resynchronization.

The protection counter 4 generates an out-of-sync signal when the non-coincidence signal is repeated n times. (A),
As shown in (b), even if one cell is lost or duplicated in the backup system, the mismatch occurs only twice. Therefore, when the number of protection stages n is 3 or more, the number of protection stages is 0 during the forward protection period. Since the cells of the system / 1 system recover the synchronization and the cell phase synchronization loss is not detected, the fluctuation of the cell interval due to the resynchronization does not occur.

FIG. 4 is a block diagram showing a second embodiment of the present invention. The same components as those in FIG. 2 are denoted by the same reference numerals. In the figure, 13 receives the output of the current system and C
A first CRC calculation unit for performing RC calculation, 12a
The 1-cell delay unit as a cell delay unit that delays the output of the CRC calculation unit 13 by 1 cell.

Reference numeral 14 is a second CRC calculation unit that receives the output of the standby system and performs a CRC calculation. 11a is the second CRC
A CRC comparison unit (cell comparison unit 2) that compares the output of the calculation unit 14 and the output of the first CRC calculation unit 13 delayed by the one-cell delay unit 12a and gives the comparison result to the read control unit 10. .

According to this embodiment, the cells processed by the CRC calculation unit are compared without directly comparing the cells. For example, assuming that one cell has 424 bits, the data can be compressed to about 8 bits by performing a CRC operation on this. As a result, the hardware amount of the 1-cell delay unit 12a, which is the cell delay unit, and the hardware amount of the comparison unit 11 can be reduced. Since the cell synchronization recovery operation itself is the same as the circuit shown in FIG. 2, its description operation is omitted.

As described above, according to the second embodiment, the number of bits of the cell comparing means can be reduced by performing the CRC operation on both cells of the cell comparing means.
The hardware of the cell delay means can be reduced.

According to the above-described embodiment, the case where cell synchronization is achieved has been described. However, the present invention is not limited to this, and can be similarly applied to a packet / frame or the like as long as it has a fixed-length data format. Further, in the above-described embodiment, the case where the read control unit 10 is provided inside the cell phase synchronization unit 1 is taken as an example, but the present invention is not limited to this and may be provided outside.

[0032]

As described above in detail, according to the present invention, cell phase synchronization control is performed by receiving cell inputs of the 0-system and 1-system, and cell phases for outputting cells as the active system and the standby system. The synchronizing means, the first cell comparing means for comparing the outputs of the active system and the standby system of the cell phase synchronizing means, and the active system output of the outputs of the cell phase synchronizing means are used to delay the cell. A cell delay means, a second cell comparison means for comparing the output of the cell delay means with the backup system output of the outputs of the cell phase synchronization means, and the outputs of the first and second cell comparison means. By providing read control means for controlling the phase synchronization of cells by the cell phase synchronization means, even if one cell is lost or duplicated in the standby system, synchronization is restored after the synchronization protection period and resynchronization is performed. Fluctuation of cell spacing due to It is possible to reduce the occurrence.

In this case, the cell delay means is
The read control means 10, which delays the output of the active system by one cell and receives the output of the second cell comparison means, controls the read or discard of the spare system cell after the synchronization protection period ends according to the comparison result during the synchronization protection period. By protecting the synchronization by performing the above procedure, even if one cell is lost or duplicated in the backup system, the synchronization can be recovered after the synchronization protection period ends, and the occurrence of cell interval fluctuation due to resynchronization can be reduced.

Further, there is provided a first CRC calculation unit for performing the CRC calculation of the working system output and a second CRC calculation unit for performing the CRC calculation of the standby system output, and these first and second CRC calculation units are provided. By making the second cell comparing means compare the output of the cell, the CRC operation is performed on both cells of the cell comparing means, so that the number of bits of the cell comparing means can be reduced and the cell delay can be reduced. The hardware of the means can be reduced.

As described above, according to the present invention, in the hitless switching of the redundant configuration, the cell phase synchronization is protected even if one cell is lost or duplicated in the standby system, and the synchronization is restored after the protection period ends. As a result, it is possible to provide a cell phase synchronization protection circuit that can reduce fluctuations in cell spacing due to resynchronization.

[Brief description of the drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a block diagram showing a first exemplary embodiment of the present invention.

FIG. 3 is an explanatory diagram of a synchronization protection operation of the present invention.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

FIG. 5 is a diagram showing a configuration example of a conventional circuit.

FIG. 6 is an explanatory diagram of synchronization protection by a conventional circuit.

FIG. 7 is an explanatory diagram when synchronization protection cannot be performed by a conventional circuit.

[Explanation of symbols]

 1 Cell Phase Synchronizing Means 2 First Cell Comparing Means 10 Read Control Means 11 Second Cell Comparing Means 12 Cell Delay Means

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Tomohiro Shinomiya Tomohiro Shinomiya 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Kazuyuki Tajima 1015, Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited ( 72) Inventor Masaki Hirota 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa within Fujitsu Limited

Claims (3)

[Claims] 1. A cell phase synchronizing means for receiving cell inputs of 0 system and 1 system to perform cell phase synchronization control and outputting cells as an active system and a standby system, and an active system and a standby system of the cell phase synchronizing means. Cell delay means for receiving the active system output of the outputs of the cell phase synchronizing means for delaying the cell, and the output of the cell delay means and the cell phase. The second cell comparison means for comparing the outputs of the backup system among the outputs of the synchronization means and the outputs of the first and second cell comparison means receive the outputs of the first and second cell comparison means and perform the phase synchronization control of the cells by the cell phase synchronization means. A cell phase synchronization protection circuit provided with read control means. 2. The cell delay means delays the output of the active system by one cell, and the read control means which has received the output of the second cell comparison means determines the synchronization protection period according to the comparison result during the synchronization protection period. 2. The cell phase synchronization protection circuit according to claim 1, wherein after the completion, the protection system cell is read out and discarded and the synchronization is protected. 3. A first CRC calculation unit that performs a CRC calculation of the working system output and a second CRC calculation unit that performs a CRC calculation of the standby system output, and these first and second CRC calculation units are provided. 3. The cell synchronization protection circuit according to claim 2, wherein the output of the unit is compared by the second cell comparison means.