JP6852909B2 - Instantaneous interruption switching device, instant interruption switching method and program - Google Patents

Description

The present invention relates to a non-instantaneous interruption switching device for data transmission, a non-instantaneous interruption switching method, and a program.

In a data transmission system, in order to ensure high reliability, a plurality of transmission lines may be prepared, one of which may be used as an active system and the rest as a backup system. In such a system, when a failure occurs in the transmission line of the active system, the transmission line is switched to the standby system and data transmission is continued. When switching the transmission line, a non-instantaneous interruption switching device is used so as not to affect the data being transmitted (for example, Patent Documents 1 and 2). The non-instantaneous switching device is already used in transmission lines used by many users, such as transmission networks using SDH (Synchronous Digital Hierarchy) and transmission of media data by TS packets related to broadcasting. However, it is expected to be used in a wider range to improve reliability.

The non-instantaneous interruption switching device disclosed in Patent Documents 1 and 2 is provided with a phase compensation circuit and a delay circuit, and when switching from the active system to the standby system, the delay between the two transmission lines is provided by these circuits. The difference is absorbed and the switching is performed after synchronizing.

Japanese Unexamined Patent Publication No. 9-36826 JP-A-2002-261739

Here, for example, in the method described in Patent Document 2, when switching from the active system to the backup system, the phase of the data of the other transmission line is set as the reference phase of the data with the transmission line having a large delay as a reference. Switching is done at the same time. Therefore, first, which transmission line is delayed is determined, and then phase matching is performed with reference to the data of the transmission line having a large delay. That is, there is a restriction that the phase of the data received via the other transmission line must be matched with the transmission line having a large delay. This also applies to the method of Patent Document 1.

Therefore, an object of the present invention is to provide a non-instantaneous interruption switching device, a non-instantaneous interruption switching method, and a program that solve the above-mentioned problems.

According to one aspect of the present invention, the non-instantaneous interruption switching device uses a synchronization signal detection unit that detects a synchronization signal included in the data and the synchronization signal for each of the data received via a plurality of transmission lines. The transmission is based on the identity determination unit that determines the identity of the data received through each of the transmission lines before reception, the synchronization signal detected for each of the transmission lines, and the determination result of the sameness. e Bei a delay difference calculating unit that calculates a delay relationship and the delay amount between the road and, on the data, the synchronization signal is included for each one or more frames, the identity determining unit has a plurality of the When the synchronization signal is detected in the reference transmission line of the transmission lines, the identity of the frames that have been received by each of the transmission lines is determined before the detection, and the delay difference is calculated. When the frame received by each of the transmission lines is the same, the unit determines that the other transmission lines are delayed with respect to the reference transmission line, and the reference transmission line receives the data. When the frame is not the same as the frame received by the other transmission line, it is determined that the reference transmission line is delayed with respect to the other transmission line.
Further, according to another aspect of the present invention, the non-instantaneous interruption switching device includes a synchronization signal detection unit that detects a synchronization signal included in the data for each of the data received via the plurality of transmission lines. An identity determination unit that determines the identity of the data received via each of the transmission lines before receiving the synchronization signal, and a determination result of the synchronization signal and the sameness detected for each of the transmission lines. The data includes the synchronization signal for each one or a plurality of frames, and the identity determination unit includes a delay difference calculation unit for calculating the delay relationship and the delay amount between the transmission lines. When the synchronization signal is detected in the reference transmission line among the plurality of transmission lines, before the detection, at the timing when the data arriving with a predetermined bit delay from the detection of the synchronization signal is detected. By then, the sameness is determined by whether or not the values obtained by dividing the frames that have been received by each of the transmission lines by a predetermined generation polynomial match, and the delay difference calculation unit serves as a reference for the transmission line. The sameness, provided that, at the timing when the data arriving with a predetermined bit delay from the detection of the synchronization signal is detected, the values obtained by dividing all of the plurality of transmission lines by the generation polynomial are obtained. As a result of the determination by the determination unit, when the frame received by each of the transmission lines is the same, it is determined that the reference transmission line is delayed with respect to the other transmission lines, and the reference is described. When the frame received by the transmission line and the frame received by the other transmission line are not the same, it is determined that the other transmission line is delayed with respect to the reference transmission line.

Further, according to another aspect of the present invention, the non-instantaneous interruption switching method includes a step of detecting a synchronization signal included in the data for each of the data received via the plurality of transmission lines, and the synchronization signal. From the step of determining the identity of the data received through each of the transmission lines before receiving the data, and the determination result of the synchronization signal and the sameness detected for each of the transmission lines, between the transmission lines. possess calculating a delay relationship and the delay amount of the, to the data, the synchronization signal is included for each of one or more frames, the step of determining the identity of a plurality of the transmission path When the synchronization signal is detected in the reference transmission line, the step of determining the identity of the frame that has been received by each transmission line and calculating the delay amount before the detection. Then, when the frame received by each of the transmission lines is the same, it is determined that the other transmission lines are delayed with respect to the reference transmission line, and the reference transmission line receives the data. When the frame and the frame received by the other transmission line are not the same, it is determined that the reference transmission line is delayed with respect to the other transmission line.

Further, according to another aspect of the present invention, the program provides the computer with a step of detecting a synchronization signal included in the data for each of the data received via the plurality of transmission lines, and the synchronization signal. From the step of determining the identity of the data received through each of the transmission lines before reception, and the determination result of the synchronization signal and the sameness detected for each of the transmission lines, between the transmission lines. It has a step of calculating a delay relationship and a delay amount, and the data includes the synchronization signal for each one or a plurality of frames, and in the step of determining the sameness, among the plurality of the transmission lines. When the synchronization signal is detected in the reference transmission line, in the step of determining the identity of the frame that each transmission line has finished receiving and calculating the delay amount before the detection. When the frame received by each of the transmission lines is the same, it is determined that the other transmission lines are delayed with respect to the reference transmission line, and the reference transmission line receives the reception. When the frame and the frame received by the other transmission line are not the same, a process of determining that the reference transmission line is delayed with respect to the other transmission line is executed.

According to the present invention, data transmission can be switched without interruption regardless of the delay relationship between transmission lines.

It is the schematic which shows an example of the transmission system which concerns on one Embodiment of this invention. It is a block diagram of the non-instantaneous interruption switching device which concerns on one Embodiment of this invention. It is the first figure explaining the switching control by one Embodiment of this invention. It is a 2nd figure explaining the switching control by one Embodiment of this invention. It is a figure which shows the minimum structure of the non-instantaneous interruption switching apparatus in one Embodiment of this invention. It is a figure which shows an example of the hardware composition of the non-instantaneous interruption switching apparatus in one Embodiment of this invention.

Hereinafter, a method for switching transmission data without interruption according to an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a schematic view showing an example of a transmission system according to an embodiment of the present invention.
The transmission system 1 includes transmission devices 2 and 4. Transmission devices 2 and 4 transmit and receive data using redundant transmission lines. For example, the transmission line of the 0 system is the active system, and the transmission line of the 1 system is the standby system. The working system is a transmission line currently in use. The backup system is a backup transmission line used when a problem occurs in the working system. In the transmission device 2, the transmission unit 3 transmits data to the transmission device 4 through the transmission lines of the 0 system and the 1 system. At this time, the transmission unit 3 transmits the transmission data including the synchronization signal in each frame. In the transmission device 4, the receiving unit 5 receives the data. At this time, the non-instantaneous interruption switching device 10 monitors whether or not the data transmitted through the transmission line of the 0 system and the data transmitted through the transmission line of the 1 system are normal. If it is normal, the data transmitted through the transmission line of the active system (0 system) is selected and output to the receiving unit 5 as received data. When an abnormality is detected in the data of the active system, the non-instantaneous interruption switching device 10 switches between the active system and the backup system, selects the data received by the newly selected 1 system as the active system, and receives the receiver 5. Output to. In order to improve reliability, the non-instantaneous interruption switching device 10 is required to switch to the standby system transmission line without interruption when an abnormality is detected in the transmission line of the active system. Generally, there is a delay difference in the data transmitted by the 0 system and the 1 system. The non-instantaneous interruption switching device 10 synchronizes the delay difference between the active system and the standby system by using the synchronization signal included in the transmission data, and realizes the non-instantaneous interruption of the transmission line.

(Constitution)
FIG. 2 is a block diagram of a non-instantaneous interruption switching device according to an embodiment of the present invention.
As shown in the figure, the non-instantaneous interruption switching device 10 includes a frame head information detection unit 100, a data synchronization writing unit 110, a memory unit 120, an input error monitoring unit 130, a data reading control unit 140, and a rate monitoring unit 150. And.

The frame head information detection unit 100 detects the synchronization signal included in the frame head packet. Here, the information transmitted by communication is used as data. Data is divided according to a specific rule, and various control information is added to the packet. A frame is a collection of a certain number of packets. In the present embodiment, a 1-bit flag indicating whether or not the packet is the first packet among the packets constituting the frame is provided in the packet control information, and the first packet is "1", other than the first packet. Set "0" for the packet. The frame head information detection unit 100 reads the value of this flag from each packet of the received data. Hereinafter, the value of the flag is described as the head information.
The frame head information detection unit 100 has a frame head information detection unit 101 that detects the head information of the frame transmitted on the 0 system transmission line and a frame head that detects the frame head information transmitted on the 1 system transmission line. It includes an information detection unit 102.

The data synchronization writing unit 110 synchronizes the data of the working system and the backup system and writes the data to the memory unit 120. The data synchronous writing unit 110 includes a generation polynomial calculation unit 111, 113, a delay difference measurement unit 112, a write address synchronization processing unit 114, and a memory write control unit 115, 116.
The generation polynomial calculation unit 111 performs division processing by a predetermined generation polynomial on the data received in the 0 series.
The generation polynomial calculation unit 113 performs division processing by a predetermined generation polynomial on the data received in the first system. As the generation polynomial, one for CRC check of data transmission / reception can be used.
The delay difference measurement unit 112 compares the result of the division processing by the generation polynomial calculation unit 111 with the result of the division processing by the generation polynomial calculation unit 113, and compares the result of the division processing by the generation polynomial calculation unit 113 with the delay relationship of the data received by the 0 system and the 1 system (which is the delay). Do you), measure the amount of delay.
The write address synchronization processing unit 114 generates a write address for the memory unit 120 of the data received by each of the 0 system and the 1 system.
The memory write control unit 115 writes the data received by the 0 system to the address for the 0 system generated by the write address synchronization processing unit 114.
The memory write control unit 116 writes the data received by the 1 system to the address for the 1 system generated by the write address synchronization processing unit 114.

The memory unit 120 temporarily stores the data received by each of the 0 system and the 1 system.
The input error monitoring unit 130 checks the normality of the data received by each of the 0 system and the 1 system. The input error monitoring unit 130 outputs the check result as alarm information to the ActivePort control unit 142, which will be described later.
The rate monitoring unit 150 monitors the write rate of the data received in the transmission line of the active system to the memory 120. The rate monitoring unit 150 outputs the write rate of the working system to the read rate control unit 143.

The data read control unit 140 reads data from the memory unit 120. The data read control unit 140 includes a memory read control unit 141, an active port control unit 142, and a read rate control unit 143.
The ActivePort control unit 142 selects a valid port (0 series or 1 series) based on the alarm information output from the input error monitoring unit 130 and the user's settings. The selected port indicates the active system. For example, it is assumed that the CPU of the non-instantaneous interruption switching device 10 sets the 0 system to the active system by the setting operation of the user. When the alarm information acquired from the input error monitoring unit 130 does not include an abnormality of the 0 system, the ActivePort control unit 142 selects the 0 system as a valid port. The input error monitoring unit 130 outputs the selected valid port to the memory read control unit 141 and the rate monitoring unit 150.
The read rate control unit 143 controls to read the received data at the same rate according to the write rate of the received data to the memory unit 120.
The memory read control unit 141 reads data at a read rate specified by the read rate control unit 143 from the address where the data received in the transmission line of the active system of the memory unit 120 is written.

(motion)
Next, the operation of the non-instantaneous interruption switching device 10 will be described. The general flow of data will be explained. First, the received data is input to the frame head information detection unit 100 and the data synchronization writing unit 110. The frame head information detection unit 100 extracts the head information and outputs it to the data synchronization writing unit 110. The data synchronization writing unit 110 synchronizes the received data of the 0 system and the 1 system and writes the received data to the memory unit 120 by using the time series information of the head information. The data read control unit 140 reads the data received from the memory unit 120 on the transmission line of the active system in cooperation with the input error monitoring unit 130 and the rate monitoring unit 150, and outputs the data to the receiving unit 5 side of FIG. Next, the processing of each step will be described in more detail.

3 and 4 are the first and second views for explaining the switching control according to the embodiment of the present invention, respectively.
3 and 4 show timing charts of processing of received data by the frame head information detection unit 100 and the data synchronization writing unit 110. With reference to FIG. 3, a processing example will be described in which the data received from the transmission line of system 1 is transmitted later than the transmission line of system 0. Through the two transmission lines of the 0 system and the 1 system, frames that are exactly the same ((a) and (c) in FIG. 3) with a delay difference are input to the frame head information detection units 101 and 102. 1, 2, and 3 shown in (a) and (c) of FIG. (3) indicate frames 1, frame 2, and frame 3 in the order of reception. Frames with the same number have the same content.

<1. Data reception and start information extraction process>
First, the 0 system receives the data of frame 1, frame 2, frame 3, .... The first packet of each frame contains the first information "1", and the subsequent packets include the first information "0". The frame head information detection unit 101 extracts the head information, generates time-series information of “1” and “0”, and outputs the time series information to the data synchronization writing unit 110 ((b) in FIG. 3). Received data (received frames 1 to 3 and the like) are sequentially transmitted to the data synchronous writing unit 110 in parallel with (synchronized with) the head information.

The same applies to system 1. FIG. 3 (c) shows how frames 1 to 3 ... Arrived later than the 0 series. The frame head information detection unit 102 extracts the head information of each frame, generates time-series information of the head information, and outputs the time series information to the data synchronization writing unit 110 ((2) in FIG. 3).

<2. Delay amount measurement processing>
In the data synchronization writing unit 110, the generation polynomial calculation unit 111 cuts out each received frame from the received data based on the head information "1" acquired from the frame head information detection unit 101. For example, the received data from the first detection of the first information "1" to the time before the second detection of the first information "1" is recognized as one frame (frame 1 in the example of FIG. 3), and a predetermined generation is performed. Division processing is performed using a polynomial (for example, an expression used to calculate a CRC code). The generation polynomial calculation unit 111 outputs the result of the division processing to the delay difference measurement unit 112. The time-series changes in the division results are shown in Fig. 3 (e). In the "1", "2" ... In FIG. 3 (e), the division results output from the generation polynomial calculation unit 111 to the delay difference measurement unit 112 at each timing are "frame 1" and "frame 2", respectively. It shows that it is the value when "" is divided. As shown in the figure, when the generation polynomial calculation unit 111 finishes receiving the frame 1 and the head information of the next frame 2 is detected, the generation polynomial calculation unit 111 subsequently performs a division process on the frame 1 by the generation polynomial. The division result by the generation polynomial calculation unit 111 does not change until the division processing by the generation polynomial for the frame 2 is performed after the head information of the frame 3 is detected.

The same applies to system 1. The generation polynomial calculation unit 113 performs division processing by the generation polynomial for the frames from the start information "1" to immediately before the next frame start information "1". The generation polynomial calculation unit 113 outputs the division result to the delay difference measurement unit 112. The time series information of the division result is shown in FIG. 3 (f).

The delay difference measuring unit 112 delays the 0 series and the 1 system from the division result by the generated polynomial (FIGS. 3 (e) and (f)) and, for example, the head information of the 0 system frame (FIG. 3 (b)). Calculate the difference. With the 0 system as a reference, the delay difference measurement unit 112 detects when the head information "1" is detected in the 0 system during the period (time T1 or later) in which the division results of the 0 system and the 1 system can be compared. (For example, one bit before), the division results of the frames that have been received by the transmission lines of the 0 series and the 1 series are compared. In the case of FIG. 3, the division result of the 0 system and the 1 system can be compared, and the head information "1" is detected in the 0 system when the head information "1" of the frame 3 is detected. is there. The division results that can be compared at that time are both the division results for frame 1. In this case, since the division targets are the same, the division results of the 0 system and the 1 system are the same. When the division results match, the delay difference measuring unit 112 determines that the 1 system is delayed with respect to the reference 0 system. Further, the delay amount is from the detection of the head information "1" in the preceding 0 system to the first detection of the head information "1" in the 1 system. In this example, the "delay difference A" shown in FIG. 3 is the delay amount. The delay difference measuring unit 112 includes time-series information of the head information output by the frame head information detection unit 101 (FIG. 3 (b)) and time-series information of the head information output by the frame head information detection unit 102 (FIG. 3 (b)). 2) Based on), the delay difference A is calculated. The delay difference measuring unit 112 outputs the delay difference information indicating that the 1 system is delayed by the "delay difference A" with respect to the 0 system to the write address synchronization processing unit 114.

Next, with reference to FIG. 4, a processing example in the case where the data received from the transmission line of the 0 system is transmitted later than the transmission line of the 1 system will be described.
The meanings of the graphs (a) to (g) in FIG. 4 are the same as those described in FIG. Moreover, the standard is set to 0 series. In the case of FIG. 4, the data arrives earlier in the 1st system than in the 0th system. Then, when the head information "1" is detected in the reference 0 system in the period (time T2 or later) in which the division results of the 0 system and the 1 system can be compared (frame 3), the delay difference measuring unit 112 determines. The division results that can be compared at that timing (frame 1 for system 0 and frame 2 for system 1) are compared. Unlike the case of FIG. 3, in the case of FIG. 4, since the data to be divided are different, the division results do not match. If the division results do not match, the delay difference measuring unit 112 determines that the reference 0 system is preceded by the 1 system (the reference 0 system is delayed). Further, the delay amount is from the detection of the head information "1" in the preceding 1 system to the first detection of the head information "1" in the 0 system. In the case of FIG. 4, the “delay difference B” is the delay amount. The delay difference measuring unit 112 calculates the delay amount based on FIGS. 4 (b) and 4 (d). The delay difference measuring unit 112 outputs the delay difference information indicating that the 0 system is delayed by the "delay difference B" with respect to the 1 system to the write address synchronization processing unit 114.

In this way, the delay difference measuring unit 112 generates time-series information ((b) or (d)) of the head information output by the frame head information detection unit 101 or 102 of the reference system. The generation timing of the delay difference information is determined based on the presence / absence of the generated polynomials output by the polynomial calculation units 111 and 113 (whether the division results are calculated in both the 0 system and the 1 system and can be compared). Further, the delay difference measuring unit 112 determines the delay relationship (which of the 0 system and the 1 system is delayed) depending on the division result of the 0 system and the 1 system, that is, whether or not the frames to be divided match. Further, the delay difference measuring unit 112 calculates the delay amount based on the determined delay relationship and the timing charts ((b) and (d)) of the head information of the 0 system and the 1 system. According to this embodiment, it is possible to easily measure the delay difference between transmission lines only from the head information of the frame.

The delay relationship and the calculation timing of the delay amount illustrated in FIGS. 3 and 4 are examples. For example, after detecting the head information "1" of the frame 3 as a reference with the 0 system, the calculation may be performed at a timing delayed by 1 bit. In that case, the determination of the division result and the delay relationship is the opposite of the above explanation. In other words, if the division results match, the 1st system precedes, and if the division results do not match, the 1st system is judged to be delayed.

<3. Data synchronous write processing>
Returning to FIG. 1, the processing after the synchronous writing of data will be described.
The write address synchronization processing unit 114 acquires the delay difference information from the delay difference measurement unit 112. Further, the write address synchronization processing unit 114 acquires the time-series data of the head information of the 0 system from the frame head information detection unit 101, and acquires the time-series data of the head information of the 1 system from the frame head information detection unit 102. Further, the write address synchronization processing unit 114 is notified of information indicating whether the active system is the 0 system or the 1 system. The write address synchronization processing unit 114 synchronizes the 0 system and the 1 system on the write side based on the delay difference calculated by the delay difference measurement unit 112. Synchronization on the writing side means calculating the offset amount of the address when writing the data of the 0 system and the 1 system to the memory unit 120. In calculating the offset amount, the offset amount on the standby system side is adjusted to the working side so as not to affect the data on the working system side. In the example of FIG. 3, assuming that the 0 system is the active system, the 1 system (spare system) is behind the 0 system (active system) by the delay difference A, so the data received by the 1 system is stored in the memory unit 120. By correcting only the delay difference A with respect to the write address of the 1 system, the write data of the 0 system and the write data of the 1 system are synchronized. For example, when no correction is made, it is assumed that the data received by the 0 system at time t1 is written to the address X1 and the data received by the 1 system at the same time is written to the address X2. When the reception of the frame 1 is started in the 0 system at the time t1 and the reception of the frame 1 is started in the 1 system at the time (t1 + delay difference A), the write address synchronization processing unit 114 starts the reception of the frame 1 in the 0 system (active system). , The address information of the data writing position of the received frame 1 is set to the address X1. Further, for the backup system 1, the data received at the time (t1 + delay difference A) is originally written to, for example, an address separated from the address X2 by the "address corresponding to the delay difference A". However, the address X2 corrected (for example, plus or minus with respect to the address X2) for the "address corresponding to the delay difference A" is calculated, and the corrected address X2 is received by the first system in the frame 1. Set as the address information of the data writing position of.

On the contrary, in the case of FIG. 4, since the 1st system is faster than the 0 system by the delay difference B, the write address of the 1st system corresponds to the delay difference B when writing the data of the 1st system to the memory unit 120. By correcting only the address in the opposite direction to the case of FIG. 3 (if it is minus in the case of FIG. 3, it is plus), the write data of the 0 system and the write data of the 1 system are synchronized. The write address synchronization processing unit 114 corrects the write address on the 1st system side, and sets the corrected write address as the address information of the data writing position for the 1st system.
The write address synchronization processing unit 114 outputs the write address information about the 0 system to the memory write control unit 115. The write address synchronization processing unit 114 outputs the write address information for one system to the memory write control unit 116.

The memory write control units 115 and 116 write the received data to the address instructed by the write address synchronization processing unit 114 of the memory unit 120, respectively.

<4. Checking data health>
In parallel with the above processing, the input error monitoring unit 130 acquires the data of the 0 system and the received data of the 1 system, and checks the error of the received frame for each of them. For example, the input error monitoring unit 130 monitors whether or not input frames exist in each of the 0 system and the 1 system. The same method as the check method generally used in the non-instantaneous interruption switching device can be applied to the method of checking the abnormality of the received frame by the input error monitoring unit 130. The input error monitoring unit 130 outputs alarm information including the check results for each of the 0 system and the 1 system to the next data read control unit 140.

<5. Selection / switching of working system>
In the data read control unit 140, the ActivePort control unit 142 acquires the alarm information of the 0 system and the 1 system. The ActivePort control unit 142 selects the active system based on the alarm information. For example, when the 0 system is set as the active system by the user, the ActivePort control unit 142 sets the 0 system as the active system if the alarm information of the 0 system does not include information indicating an abnormality. When the alarm information of the 0 system includes information indicating an abnormality and the alarm information of the 1 system does not include an abnormality, the ActivePort control unit 142 sets the 1 system as the active system. That is, the active system is switched from the 0 system to the 1 system. The ActivePort control unit 142 outputs the information of the selected system to the memory read control unit 141 and the write rate monitoring unit 150.

<6. Write rate monitoring>
The write rate monitoring unit 150 monitors the write rate in the selected system (active system) based on the information of the selected system notified from the ActivePort control unit 142 among the 0 system and the 1 system. For example, when the active system is the 0 system, the write rate monitoring unit 150 monitors the amount of write data per unit time in which the memory write control unit 115 writes the received data to the memory unit 120. The write rate monitoring unit 150 outputs the write rate obtained by monitoring to the data read control unit 140.

<7. Reading received data from memory>
In the data read control unit 140, the read rate control unit 143 acquires the write rate information. The read rate control unit 143 calculates the read rate so as to perform reading at the same rate as the write rate acquired from the write rate monitoring unit 150, and notifies the memory read control unit 141 of the read rate. The memory read control unit 141 reads the received data of the active system written in the memory unit 120 at a specified read rate based on the information of the active system obtained from the ActivePort control unit 142 and the notified read rate. In accordance with the selection of the active system by the ActivePort control unit 142, for example, the read destination may be switched between the 0 system and the 1 system by switching the upper address of the memory. The memory read control unit 141 outputs the read reception frame to the reception unit 5. By this. It is possible to realize highly reliable data transmission while switching between the active system and the backup system by using the transmission lines redundant to the 0 system and the 1 system.

(Action / effect)
The non-instantaneous interruption switching device 10 according to the present embodiment adopts the architecture illustrated in FIG. 2, and can switch between the active system and the backup system by inserting a synchronization signal capable of distinguishing the beginning of a frame into a packet. In addition, the delay difference between the transmission lines required for non-instantaneous switching between system 0 and system 1 is included in the packet control information by 1 bit of the frame start information, and the division result is matched by the generated polynomial. It can be calculated by confirmation. Further, the delay relationship between the 0 system and the 1 system can be dealt with in either case where the 0 system is behind the 1 system or when it is ahead of the 1 system. Therefore, it is not necessary to perform phase matching based on the large delay side used in a general non-instantaneous interruption switching device, and the delay between transmission lines has been a restriction in the case of non-instantaneous interruption switching. It is possible to design the difference more flexibly.

It is also important how much the delay difference between the 0 system and the 1 system is allowed. For example, the capacity of the memory unit 120 is increased, and the head information of the head packet of each predetermined frame (for example, every 2 frames) is increased. By setting "1" for, and setting "0" for other packets even at the beginning of the frame, a longer delay difference can be allowed. Therefore, the non-instantaneous interruption switching device 10 can be applied to a transmission line under various operating conditions.

FIG. 5 is a diagram showing a minimum configuration of a non-instantaneous interruption switching device according to an embodiment of the present invention.
As shown in FIG. 5, the non-instantaneous interruption switching device 20 includes at least a synchronization signal detection unit 21, an identity determination unit 22, and a delay difference calculation unit 23.
The synchronization signal detection unit 21 detects a synchronization signal (starting information “1”) included in the data for each of the data received via the plurality of transmission lines.
The identity determination unit 22 determines the identity of the data received via each transmission line before receiving the synchronization signal.
The delay difference calculation unit 23 calculates the delay relationship and the amount of delay between the transmission lines from the determination result of the sameness as the synchronization signal detected for each transmission line.
In comparison with the configuration of the above embodiment, the synchronization signal detection unit 21 corresponds to the frame head information detection unit 100, and the identity determination unit 22 and the delay difference calculation unit 23 correspond to the delay difference measurement unit 112.

FIG. 6 is a diagram showing an example of the hardware configuration of the non-instantaneous interruption switching device according to the embodiment of the present invention.
The computer 900 includes a CPU 901, a main storage device 902, an auxiliary storage device 903, an input / output interface 904, and a communication interface 905. The above-mentioned non-instantaneous switching device 10 is mounted on the computer 900. Then, some or all of the functions of the frame head information detection unit 100, the data synchronous writing unit 110, the memory unit 120, the input error monitoring unit 130, the data read control unit 140, and the write rate monitoring unit 150 described above are of the program. It is stored in the auxiliary storage device 903 in the form. The CPU 901 reads the program from the auxiliary storage device 903, expands it to the main storage device 902, and executes the above processing according to the program. Further, the CPU 901 secures a storage area in the main storage device 902 according to the program. Further, the CPU 901 secures a storage area for storing the data being processed in the auxiliary storage device 903 according to the program.

In at least one embodiment, the auxiliary storage device 903 is an example of a non-temporary tangible medium. Other examples of non-temporary tangible media include magnetic disks, magneto-optical disks, CD-ROMs, DVD-ROMs, semiconductor memories, etc., which are connected via the input / output interface 904. When this program is distributed to the computer 900 via a communication line, the distributed computer 900 may expand the program to the main storage device 902 and execute the above processing. Further, the program may be for realizing a part of the above-mentioned functions. Further, the program may be a so-called difference file (difference program) that realizes the above-mentioned function in combination with another program already stored in the auxiliary storage device 903.

In addition, all or part of each function of the above-mentioned non-instantaneous interruption switching device 10 uses hardware such as ASIC (Application Specific Integrated Circuit), PLD (Programmable Logic Device), and FPGA (Field-Programmable Gate Array). It may be realized.

In addition, it is possible to replace the components in the above-described embodiment with well-known components as appropriate without departing from the spirit of the present invention. Further, the technical scope of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.

1 ... Transmission system 2, 4 ... Transmission device 3 ... Transmission unit 5 ... Reception unit 10 ... Instantaneous interruption switching device 100 ... Frame head information detection unit 110 ... Data synchronization Write units 111, 113 ... Generated polynomial calculation unit 112 ... Delay difference measurement unit 114 ... Write address synchronization processing unit 115, 116 ... Memory write control unit 120 ... Memory unit 130 ... Input Error monitoring unit 140 ... Data read control unit 141 ... Memory read control unit 142 ... ActivePort control unit 143 ... Read rate control unit 150 ... Write rate monitoring unit 20 ... Instantaneous switching Device 21 ... Synchronous signal detection unit 22 ... Identity determination unit 23 ... Delay difference calculation unit 900 ... Computer 901 ... CPU,
902 ... Main memory,
903 ... Auxiliary storage device,
904 ... Input / output interface 905 ... Communication interface

Claims (8)

For each of the data received via the plurality of transmission lines, a synchronization signal detection unit that detects the synchronization signal included in the data, and a synchronization signal detection unit.
An identity determination unit that determines the identity of the data received via each transmission line before receiving the synchronization signal, and an identity determination unit.
A delay difference calculation unit that calculates the delay relationship and the amount of delay between the transmission lines from the synchronization signal detected for each transmission line and the determination result of the identity.
Bei to give a,
The data includes the synchronization signal for each one or more frames.
When the synchronization signal is detected in the reference transmission line among the plurality of transmission lines, the identity determination unit of the frame that has been received by each of the transmission lines before the detection. Judge identity,
When the frames received by each of the transmission lines are the same, the delay difference calculation unit determines that the other transmission lines are delayed with respect to the reference transmission line, and the delay difference calculation unit determines that the other transmission lines are delayed with respect to the reference transmission line. When the frame received by the transmission line and the frame received by the other transmission line are not the same, it is determined that the reference transmission line is delayed with respect to the other transmission line.
Non-instantaneous switching device. A writing unit that synchronizes the data received via the plurality of transmission lines and writes the data to the memory based on the delay amount.
The non-instantaneous interruption switching device according to claim 1. A monitoring unit for the transmission path that is selected as the working system to monitor the writing rate to the memory of the data received,
A read unit that reads data from the memory at the same rate as the write rate,
The non-instantaneous interruption switching device according to claim 2. The identity determining unit, the determination of the identity, have rows depending on whether a value obtained by dividing the frame by a predetermined generator polynomial is matched,
The delay difference calculation unit obtains a value obtained by dividing all of the plurality of transmission lines by the generation polynomial at the timing when the synchronization signal is detected in the reference transmission line. Calculate the delay relationship and amount of delay between
The non-instantaneous interruption switching device according to any one of claims 1 to 3. For each of the data received via the plurality of transmission lines, a synchronization signal detection unit that detects the synchronization signal included in the data, and a synchronization signal detection unit.
An identity determination unit that determines the identity of the data received via each transmission line before receiving the synchronization signal, and an identity determination unit.
A delay difference calculation unit that calculates the delay relationship and the amount of delay between the transmission lines from the synchronization signal detected for each transmission line and the determination result of the identity.
With
The data includes the synchronization signal for each one or more frames.
When the synchronization signal is detected in the reference transmission line among the plurality of transmission lines, the identity determination unit detects data arriving with a predetermined bit delay from the detection of the synchronization signal. At the timing, before the detection, the identity is determined by whether or not the values obtained by dividing the frames received by each transmission line by a predetermined generation polynomial match.
The delay difference calculation unit divides all of the plurality of transmission lines by the generation polynomial at the timing when data arriving with a predetermined bit delay after the synchronization signal is detected in the reference transmission line is detected. If the frame received by each of the transmission lines is the same as a result of the determination by the identity determination unit on condition that a value is obtained, the reference transmission line is set with respect to the other transmission lines. If it is determined that there is a delay and the frame received by the reference transmission line and the frame received by the other transmission line are not the same, the other transmission with respect to the reference transmission line. Judge that the road is delayed,
Non-instantaneous switching device. The delay difference calculation unit sets the time from the detection of the synchronization signal on the non-delayed transmission line to the detection of the synchronization signal on the first delayed transmission line as the delay amount.
The non-instantaneous interruption switching device according to any one of claims 1 to 5. For each of the data received via the plurality of transmission lines, a step of detecting a synchronization signal included in the data, and a step of detecting the synchronization signal.
A step of determining the identity of the data received via each of the transmission lines before receiving the synchronization signal, and
A step of calculating the delay relationship and the amount of delay between the transmission lines from the synchronization signal detected for each transmission line and the determination result of the identity.
Have a,
The data includes the synchronization signal for each one or more frames.
In the step of determining the identity, when the synchronization signal is detected in the reference transmission line among the plurality of transmission lines, the transmission lines have been received by each of the transmission lines before the detection. Judge the identity of the frame and
In the step of calculating the delay amount, when the frames received by the respective transmission lines are the same, it is determined that the other transmission lines are delayed with respect to the reference transmission line, and the reference is used. When the frame received by the transmission line and the frame received by the other transmission line are not the same, it is determined that the reference transmission line is delayed with respect to the other transmission line.
How to switch without interruption. On the computer
For each of the data received via the plurality of transmission lines, a step of detecting a synchronization signal included in the data, and a step of detecting the synchronization signal.
A step of determining the identity of the data received via each of the transmission lines before receiving the synchronization signal, and
A step of calculating the delay relationship and the amount of delay between the transmission lines from the synchronization signal detected for each transmission line and the determination result of the identity.
Have,
The data includes the synchronization signal for each one or more frames.
In the step of determining the identity, when the synchronization signal is detected in the reference transmission line among the plurality of transmission lines, the transmission lines have been received by each of the transmission lines before the detection. Judge the identity of the frame and
In the step of calculating the delay amount, when the frames received by the respective transmission lines are the same, it is determined that the other transmission lines are delayed with respect to the reference transmission line, and the reference is used. When the frame received by the transmission line is not the same as the frame received by the other transmission line, it is determined that the reference transmission line is delayed with respect to the other transmission line. ,
A program that executes.

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