JPH0563683A - Redundancy system switching device for digital transmission - Google Patents
Redundancy system switching device for digital transmissionInfo
- Publication number
- JPH0563683A JPH0563683A JP24694791A JP24694791A JPH0563683A JP H0563683 A JPH0563683 A JP H0563683A JP 24694791 A JP24694791 A JP 24694791A JP 24694791 A JP24694791 A JP 24694791A JP H0563683 A JPH0563683 A JP H0563683A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- crc
- selector
- switching
- main signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Detection And Prevention Of Errors In Transmission (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、ディジタル伝送用冗長
系切替え装置に係り、特にディジタル伝送システムにお
いて冗長構成をとることにより、装置故障及び保守作業
に対し自動的または強制的に予備系への切替を行い、ト
ラフイックへの影響を抑えるディジタル伝送用冗長系切
替え装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a redundant system switching device for digital transmission, and more particularly to a redundant system in a digital transmission system, whereby a redundant system is automatically or forcibly provided to a standby system in case of device failure and maintenance work. The present invention relates to a redundant system switching device for digital transmission that performs switching to suppress the influence on traffic.
【0002】[0002]
【従来の技術】従来、この種の冗長系切替え装置は、装
置内監視によって検出した装置故障を切替トリガとして
現用系→予備系の切替を行っていた。図2に示すよう
に、入力信号は装置内監視情報挿入部14を通って信号
分岐部2へ入り現用系/予備系からなる2系統の装置内
信号経路(0系信号経路構成部3〜5,及び1系信号経
路構成部6〜8)を経由し、セレクタ13へと接続され
るとともに、0系装置内エラー検出部15、1系装置内
エラー検出部16へと接続されている。2. Description of the Related Art Heretofore, this type of redundant system switching device has switched from the active system to the standby system by using a device failure detected by internal monitoring as a switching trigger. As shown in FIG. 2, the input signal passes through the in-device monitoring information inserting section 14 to the signal branching section 2 and two in-apparatus signal paths (0-system signal path composing sections 3 to 5) consisting of an active system and a standby system are provided. , And 1-system signal path constituent units 6 to 8), and is connected to the selector 13 and to the 0-system device error detection unit 15 and the 1-system device error detection unit 16.
【0003】装置内監視情報挿入部14、は主信号のエ
ラー監視情報(例えばパリティ)をオーバーヘッドに挿
入し、0系/1系の信号経路3〜8を通ってセレクタに
入る直前に主信号のエラー検出を行う0系/1系装置内
エラー検出部15/16にも接続され、エラー検出時は
信号経路を予備系側に切り替える選択を行っていた。The in-device monitoring information insertion unit 14 inserts error monitoring information (eg, parity) of the main signal into the overhead and sends the main signal immediately before entering the selector through signal paths 3 to 8 of the 0 system / 1 system. It is also connected to the error detection unit 15/16 in the 0-system / 1-system device that performs error detection, and at the time of error detection, the signal path is selected to be switched to the backup system side.
【0004】[0004]
【発明が解決しようとする課題】上述した従来の冗長系
切替方式では、装置内の故障発生または保守上の誤操作
に対して、冗長系切替により障害の復旧を行っても、エ
ラーを含んだ主信号はすでに後方へ送出済みである為、
トラフイックを使用中のユーザーに対して悪影響を及ぼ
すという不都合が生じていた。In the above-mentioned conventional redundant system switching method, even if the failure is recovered by the redundant system switching in the occurrence of a failure in the device or an erroneous operation in maintenance, the main error still occurs. Since the signal has already been sent to the rear,
There has been an inconvenience of adversely affecting the user who is using the troughwick.
【0005】[0005]
【発明の目的】本発明は、かかる従来例の有する不都合
を改善し、とくに、主信号の瞬断を伴うことなく障害等
の復旧時に冗長系切替えを行うことのできるディジタル
伝送用冗長系切替え装置を提供することを、その目的と
する。SUMMARY OF THE INVENTION An object of the present invention is to improve the inconvenience of the conventional example, and more particularly, to a redundant system switching device for digital transmission which can carry out a redundant system switching at the time of restoration of a failure without accompanying a momentary interruption of the main signal. The purpose is to provide.
【0006】[0006]
【課題を解決するための手段】入力信号を現用系と予備
系の二系統の信号経路に分岐する信号分岐部と、二系統
の信号経路の各出力側に装備され主信号の1フレーム分
の遅延量を持つ二系統のバファメモリと、信号分岐部の
信号入力側で入力直前のフレームの主信号のCRC演算
を行いオーバーヘッドに演算値を挿入するCRC挿入部
とを有している。そして、必要に応じて現用系と予備系
の切り換え選択を行い外部接続するうセレクタを設ける
とともに、このセレクタに各バファメモリに送り込まれ
る直前の主信号のCRCエラーを検出するCRCエラー
検出部を併設し、セレクタが、CRCエラー検出部の出
力に応じて作動し二系統の信号経路を一方から他方に切
り換えるエラー対応切り換え機能を備えている、という
構成を採っている。これによって、前述した目的を達成
しようとするものである。A signal branching unit for branching an input signal into two signal paths of a working system and a standby system, and one frame of a main signal provided on each output side of the two system signal paths. It has a two-system buffer memory having a delay amount, and a CRC insertion section for performing CRC calculation of the main signal of the frame immediately before input on the signal input side of the signal branching section and inserting the calculated value in the overhead. A selector for switching between the active system and the standby system for external connection is provided as needed, and a CRC error detection unit for detecting a CRC error of the main signal immediately before being sent to each buffer memory is also provided for this selector. The selector has an error-corresponding switching function that operates in response to the output of the CRC error detector to switch the two signal paths from one to the other. This aims to achieve the above-mentioned object.
【0007】[0007]
【発明の実施例】以下、本発明の一実施例を図1に基づ
いて説明する。この図1に示す実施例は入力信号を現用
系と予備系の二系統の信号経路に分岐する信号分岐部2
と、この二系統の信号経路の各出力側に装備され主信号
の1フレーム分の遅延量を持つ二系統のバファメモリ1
1,12と、信号分岐部2の信号入力側で入力直前のフ
レームの主信号のCRC演算を行いオーバーヘッドに演
算値を挿入するCRC挿入部1とを有している。そし
て、必要に応じて現用系と予備系の切り換え選択を行い
外部接続するセレクタ13を設けるとともに、このセレ
クタ13に前記各バファメモリ11,12に送り込まれ
る直前の主信号のCRCエラーを検出するCRCエラー
検出部9,10が併設されている。また、セレクタ13
は、CRCエラー検出部9,10の出力に応じて作動し
前記二系統の信号経路を一方から他方に切り換えるエラ
ー対応切り換え機能を備えている。ここでCRC構成
(CyclicRedundancy Check)とは巡回冗長検査のこ
とをいう。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. In the embodiment shown in FIG. 1, a signal branching unit 2 for branching an input signal into two signal paths, a working system and a standby system.
And a two-system buffer memory 1 equipped on each output side of these two-system signal paths and having a delay amount of one frame of the main signal
1 and 12 and a CRC insertion unit 1 that performs CRC calculation of the main signal of the frame immediately before input on the signal input side of the signal branching unit 2 and inserts the calculated value into the overhead. A selector 13 for switching between the active system and the standby system for external selection is provided as needed, and a CRC error for detecting a CRC error of the main signal immediately before being sent to each of the buffer memories 11 and 12 is provided in the selector 13. The detectors 9 and 10 are provided side by side. Also, the selector 13
Has an error-corresponding switching function that operates in accordance with the outputs of the CRC error detection units 9 and 10 to switch the signal paths of the two systems from one to the other. Here, the CRC configuration (Cyclic Redundancy Check) means a cyclic redundancy check.
【0008】すなわち、入力信号を現用系と予備系から
なる2系統の装置内信号経路に分岐する信号分岐部2、
主信号のフレーム長換算で1フレーム分の遅延量を持つ
2系統のバファメモリ(以後ESと呼ぶ)11,12、
この2系統の信号経路の分離部の手前で直前のフレーム
の主信号のCRC演算を行いオーバーヘッドに演算値を
挿入するCRC挿入部1、上記2系統の信号経路を通っ
てES部11,12に入る直前の主信号のCRCエラー
検出を行い、現用系においてエラー検出時は信号経路を
予備系側に切り替える選択を行うセレクタ13を有して
いる。そして、入力主信号はCRC挿入部1を通って信
号分岐部2へ接続され、2系統の装置内信号経路(0系
信号経路3〜5,1系信号経路6〜8)を経由し、0系
ES部11,1系ES12を通ってセレクタ13へ接続
される。一方、0系ES部11,1系ES12の直前の
主信号はそれぞれ0系CRCエラー検出部9,1系CR
Cエラー検出部10へと接続される。That is, a signal branching unit 2 for branching an input signal into two internal signal paths consisting of an active system and a standby system,
Two-system buffer memory (hereinafter referred to as ES) 11, 12 having a delay amount of one frame in terms of the frame length of the main signal,
A CRC insertion unit 1 that performs a CRC operation on the main signal of the immediately preceding frame and inserts an operation value into the overhead before the separation unit of the two-system signal paths, and the ES units 11 and 12 through the two-system signal paths. It has a selector 13 for performing CRC error detection of the main signal immediately before entering and for selecting a signal path switching to the standby system side when an error is detected in the active system. Then, the input main signal is connected to the signal branching unit 2 through the CRC inserting unit 1, passes through the two system internal signal paths (0 system signal paths 3 to 5, 1 system signal paths 6 to 8), and It is connected to the selector 13 through the system ES unit 11 and the 1-system ES 12. On the other hand, the main signals immediately before the 0-system ES unit 11 and the 1-system ES 12 are the 0-system CRC error detection unit 9 and the 1-system CR, respectively.
It is connected to the C error detection unit 10.
【0009】次に、動作の説明を行う。入力信号はCR
C挿入部1によって主信号のCRC演算を行いオーバー
ヘッドに演算値を挿入した後、信号分岐部2によって2
系統の装置内信号経路に分岐する。仮に、0系/1系の
信号経路の内、0系側で運用中と考える。運用中の信号
経路において障害が発生し、0系エラー検出部9におい
てCRCエラーを検出すると、セレクタ13を1系選択
方向へ切り替え、1系ES部12のデータをセレクタ1
3を通じて送り出す。0系ES11と1系ES12は同
期して書き込み・読み出しを行うため、エラーを含んだ
0系ES11の主信号データは廃棄され、正常な1系主
信号データが採用される。Next, the operation will be described. Input signal is CR
After the CRC calculation of the main signal is performed by the C insertion unit 1 and the calculation value is inserted in the overhead, the signal branching unit 2
Branch to the signal path in the system. It is assumed that the 0 system side is operating in the 0 system / 1 system signal path. When a failure occurs in the signal path in operation and the 0-system error detection unit 9 detects a CRC error, the selector 13 is switched to the 1-system selection direction, and the data of the 1-system ES unit 12 is transferred to the selector 1
Send out through 3. Since the 0-system ES11 and the 1-system ES12 perform writing / reading synchronously, the main signal data of the 0-system ES11 containing an error is discarded and normal 1-system main signal data is adopted.
【0010】[0010]
【発明の効果】以上説明したように、本発明によると、
冗長構成を持つデジタル伝送システムにおいて、故障発
生から切替完了までの間に主信号の瞬断を全く伴わずに
実行でき、また保守作業中に運用中の信号経路構成部を
誤って抜去しても、同様に主信号に全く影響を与えず切
替が可能となり、これによって障害等における復旧作業
に際しても主信号の瞬断を行うことなく冗長系の切替え
を行うことができるという従来にない優れたディジタル
伝送用冗長系切替え装置を提供することができる。As described above, according to the present invention,
In a digital transmission system with a redundant configuration, it can be executed without any interruption of the main signal between the occurrence of a failure and the completion of switching, and even if the signal path component in operation is accidentally removed during maintenance work. Similarly, it is possible to switch without affecting the main signal at all, and thereby it is possible to switch the redundant system without interrupting the main signal even at the time of restoration work in case of a failure etc. A redundant system switching device for transmission can be provided.
【図1】本発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing an embodiment of the present invention.
【図2】従来例を示すブロック図である。FIG. 2 is a block diagram showing a conventional example.
1 CRC挿入部 2 信号分岐部 3ないし5 0系信号経路構成部(30) 6ないし8 1系信号経路構成部(60) 9 0系CRCエラー検出部 10 1系CRCエラー検出部 11 0系バッファメモリ(ES) 12 1系バッファメモリ(ES) 13 セレクタ 1 CRC Insertion Unit 2 Signal Dividing Unit 3 to 5 0 System Signal Path Constructing Unit (30) 6 to 8 1 System Signal Path Constructing Unit (60) 9 0 System CRC Error Detection Unit 10 1 System CRC Error Detection Unit 11 0 System Buffer Memory (ES) 12 1-system buffer memory (ES) 13 Selector
Claims (1)
号経路に分岐する信号分岐部と、前記二系統の信号経路
の各出力側に装備され主信号の1フレーム分の遅延量を
持つ二系統のバファメモリと、前記信号分岐部の信号入
力側で入力直前のフレームの主信号のCRC演算を行い
オーバーヘッドに演算値を挿入するCRC挿入部とを有
し、必要に応じて現用系と予備系の切り換え選択を行い
外部接続するうセレクタを設けるとともに、このセレク
タに前記各バファメモリに送り込まれる直前の前記主信
号のCRCエラーを検出するCRCエラー検出部を併設
し、前記セレクタが、前記CRCエラー検出部の出力に
応じて作動し前記二系統の信号経路を一方から他方に切
り換えるエラー対応切り換え機能を備えていることを特
徴としたディジタル伝送用冗長系切替え装置。1. A signal branching unit for branching an input signal into two signal paths, a working signal line and a backup signal path, and a delay amount for one frame of a main signal, which is provided at each output side of the two signal paths. It has a two-system buffer memory and a CRC insertion unit for performing CRC calculation of the main signal of the frame immediately before input on the signal input side of the signal branching unit and inserting the calculated value in the overhead, and if necessary, to the active system. A selector for switching the standby system and making an external connection is provided, and a CRC error detection unit for detecting a CRC error of the main signal immediately before being sent to each buffer memory is also provided in the selector. A digital circuit having an error-corresponding switching function that operates according to the output of an error detection unit and switches the signal paths of the two systems from one to the other. Redundant system switching device for transmission.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24694791A JPH0563683A (en) | 1991-08-31 | 1991-08-31 | Redundancy system switching device for digital transmission |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24694791A JPH0563683A (en) | 1991-08-31 | 1991-08-31 | Redundancy system switching device for digital transmission |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0563683A true JPH0563683A (en) | 1993-03-12 |
Family
ID=17156109
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24694791A Pending JPH0563683A (en) | 1991-08-31 | 1991-08-31 | Redundancy system switching device for digital transmission |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0563683A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07107076A (en) * | 1993-10-06 | 1995-04-21 | Nec Corp | No-hit data switching device |
JPH07177116A (en) * | 1993-12-16 | 1995-07-14 | Nec Corp | Digital signal transmitter |
FR2721464A1 (en) * | 1994-06-17 | 1995-12-22 | Alcatel Telspace | Parity bit control word correction method e.g. for SDH transmission system |
US6357033B1 (en) | 1998-03-06 | 2002-03-12 | Nec Corporation | Communication processing control apparatus and information processing system having the same |
CN1330103C (en) * | 2003-04-22 | 2007-08-01 | 华为技术有限公司 | Method for implementing redudancy back up |
-
1991
- 1991-08-31 JP JP24694791A patent/JPH0563683A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07107076A (en) * | 1993-10-06 | 1995-04-21 | Nec Corp | No-hit data switching device |
JPH07177116A (en) * | 1993-12-16 | 1995-07-14 | Nec Corp | Digital signal transmitter |
FR2721464A1 (en) * | 1994-06-17 | 1995-12-22 | Alcatel Telspace | Parity bit control word correction method e.g. for SDH transmission system |
US6357033B1 (en) | 1998-03-06 | 2002-03-12 | Nec Corporation | Communication processing control apparatus and information processing system having the same |
CN1330103C (en) * | 2003-04-22 | 2007-08-01 | 华为技术有限公司 | Method for implementing redudancy back up |
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