JPH0522279A - Frame detection protection circuit - Google Patents

Abstract

PURPOSE:To reduce the probability of out of frame synchronism due to an error caused in a transmission line by providing 1st and 2nd algorithms as a multi-point monitor algorithm and selecting either of the algorithms when out of synchronism is detected for a prescribed number of times from the frame synchronization state. CONSTITUTION:A frame synchronization bit is arranged separately at each frame interval length x-bit in the configuration of a multi-frame. The frame synchronization bit is monitored at 8 points (200-207) from S0 to S7. When out of synchronism takes place, the algorithm is restored to the initial stage of S0(200). When the synchronization is detected at the points S0 and S1, then the higher points are sequentially advanced. When the final stage of the point S7 is reached, a synchronization detection signal is sent (208) and the process is restored to the stage of the S4 and the detection is repeated.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to frame detection and protection circuits.

[0002]

2. Description of the Related Art Conventionally, after the bit synchronization is established and the frame synchronization is established, the frame protection method based on the forward protection does not consider the number of forward protection stages to be out of synchronization unless the number of consecutive frame errors is larger than the above, and the frame is not synchronized. Stayed in sync. For example, in the front protection i-stage frame protection system, when the i frame is deviated, the frame synchronization is performed again.

For this reason, if there is a 1-bit error in the frame synchronization bit of one frame over the i-frame,
There is a problem in that even if the frame pattern is a frame pattern, the frame pattern is misaligned because it is regarded as a frame shift and an operation for resynchronization is performed.

That is, in the conventional frame protection system, the frame sync bit causes an error in the transmission path, and when the error exceeds the number of forward protection steps, the frame sync bit is re-established. If the same bit pattern as the frame synchronization bit is present in the data during detection, the pattern of the data is erroneously recognized as normal frame synchronization, and as a result, the number of forward protection stages is exceeded, so frame synchronization is lost and the frame is re-established. Since synchronization is reestablished, there is a problem that it takes a long time to pull in the frame synchronization.

Particularly, the frame synchronization bit pattern having a smaller number of bits has a higher probability that a bit having the same pattern as the frame synchronization bit pattern is generated in the data to be transmitted. Therefore, in the case of a short frame synchronization bit pattern, the number of times of frame synchronization recovery is increased. As a result, there is a problem that the frame synchronization pull-in time is increased.

[0006]

As described above, in the conventional frame protection system, when the frame synchronization is re-established due to the occurrence of an error exceeding the number of forward protection stages, the same pattern as the frame synchronization exists in the data. ,
Since we have to regain frame synchronization,
There is a problem that it takes a long time to pull in the frame synchronization.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to eliminate this problem and provide a frame detection and protection circuit that reduces the probability of out-of-frame synchronization after the initial frame synchronization is established.

[0008]

According to the present invention, in a frame detection protection circuit for monitoring multi-points of distributed frame synchronization bits, there are first and second algorithms as the multi-points monitoring algorithm. When the synchronization loss is detected a predetermined number of times from the normal synchronization state, the algorithm is switched.

[0009]

According to the present invention, in the frame detection protection circuit for monitoring the distributed frame synchronization bits at multiple points, the first and second algorithms are provided as the multipoint monitoring algorithm, and the predetermined number of times from the frame synchronization state is reached. When out-of-sync is detected, the algorithm is switched to enable adaptive detection and protection of frame synchronization.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of a frame detection and protection circuit showing an embodiment of the present invention. The frame detection protection circuit detects a frame synchronization bit by a frame synchronization detection algorithm and sends a synchronization detection signal, and a synchronization detection signal of the frame detection unit 100 is protected by protecting the front three stages and the rear one stage. Whether or not it is in a synchronized state, a load signal is output, and in an out-of-synchronized state, a hunt signal that changes the frame synchronization detection algorithm of the frame detection unit 100 and the output of a synchronization detection signal from the frame detection unit 100. The frame protection unit 110 outputs a protection detection signal for controlling the route switching to a frame detection unit, and a timing unit 120 having a multi-frame counter for sending necessary multi-frame pulses to the frame protection unit 110.

First, the frame synchronization detection algorithm of the frame detector will be described. FIG. 2 is a diagram showing a frame synchronization detection algorithm of the frame detection unit. In this embodiment, the frame synchronization bit is 4 bits, specifically 0010. The frame synchronization bits are distributed and arranged every x bits of the frame interval length in the multi-frame configuration. This frame synchronization bit is monitored at multiple points at eight points (200 to 207) from S0 to S7. When the synchronization is lost, the process returns to the initial stage of the algorithm of S0 (200). And, again, S0 stage (200)
From then on, it is sequentially judged whether or not the frame synchronization is maintained. If synchronization is lost at the stage of S0 (200), S
The step of 0 (200) is repeated and the synchronization detection signal is not transmitted. When synchronization is detected in S0 (200), S1 (2
01) to S2 when synchronization is detected in S1 (201)
Proceed to (202) in sequence to a higher level. When the final stage of S7 (207) is reached, a synchronization detection signal is sent (208) and at the same time the process returns to the stage of S4 (204) to repeat the detection.
Here, if the synchronization is lost in the step of S7 (207), the process returns to the step of S0 and the synchronization detection is repeated. The present invention further provides that when the synchronization is detected in the step S6 (206), the delay circuit 210 may be skipped without the step S7 (207).
After that, the synchronization detection signal can be transmitted at the timing of the synchronization detection signal of S7 (207). Hereinafter, the selection of the synchronization detection signal obtained in S7 will be referred to as "selection of A", and the selection of the synchronization detection signal obtained in S6 will be referred to as "selection of B".

FIG. 3 is a diagram showing specific ROM data storing the frame synchronization detection algorithm. In this figure, addresses are input data to the algorithm ROM, and data are output data from the algorithm ROM. A2 to A0 and D2 to D0 indicate the respective steps S0 to S7 of the algorithm described in FIG. The input A3 data is the frame sync bit (0
010), the steps from A2 to A0 sequentially proceed to higher steps. In addition, even if the level of A2 to A0 is high, the input data of A3 is the frame synchronization bit (0
When it is different from (0101) (1101), the output data of D2 to D0 becomes 0, and the process returns to the first step S0 of FIG. In addition, A4 is a hunt signal input from the frame protection unit, and the synchronization state is "1" and the out-of-synchronization state is "
0 ', D3 and D4 are synchronization detection signals, and D3
Is the output of "selection of A" and D4 is the output of "selection of B".

Next, the operation of the frame protector will be described. FIG. 4 is a diagram showing a state transition diagram in the frame protection unit. First, consider the transition from the synchronization state (400). When the synchronization state 400 that has received the synchronization detection signal is continued three times, the output of the synchronization detection signal is set to "select A" (46).
0). If the synchronization state has not continued three times, the front protection first stage (410) is checked and if the synchronization detection signal is received, the state returns to the synchronization state (400) again. When the front protection first stage (410) has not received the synchronization detection signal, it is further determined whether the front protection second stage (420) has not received the synchronization detection signal. If there is a sync detection signal in the front protection second stage (420), the sync state (40
Return to 0). If the synchronization detection signal cannot be detected in the front protection second stage (420), further front protection third stage (43)
In 0), it is determined whether or not the synchronization detection signal is received. When the synchronization detection signal is received in the front protection third stage, the state returns to the synchronization state (400) again. If the synchronization detection signal is not received even in the forward protection three stages, the hunting state (440) for capturing the frame synchronization is established. In addition, when the sync detection signal is not received in the front protection second stage, the output of the sync detection signal is “select B”.
To effectively utilize the result of the previous stage of the final stage of the algorithm so that the minimum frame synchronization is restored, and transmission interruption due to a long synchronization pull-in time is prevented in advance.

Next, the state transition from the hunting state (440) will be described. When the synchronization detection signal is received in the hunting state, the rear protection first stage (450) determines whether or not the synchronization detection signal is received, and if not received, returns to the hunting state again. When the synchronization detection signal is received, the synchronization state (4
00).

A hunt signal is output by the above frame protection operation. This hunt signal is output to the frame detection section as to whether it is in the synchronization state or the hunting state depending on the protection result, and is used as an input variable of the frame synchronization detection algorithm. Further, a control signal for "selection of A" or "selection of B" for switching the output of the synchronization detection signal as the protection detection signal is input to the frame detection unit.

Next, a specific structure will be described. Figure 5
FIG. 3 is a detailed configuration diagram of a frame detection unit and a frame protection unit. First, the input signal in which the frame synchronization bits are distributedly arranged is the signal input terminal 501 of the frame detection unit 500.
From the frame detection algorithm ROM502
Is input to A3. Frame detection algorithm ROM
Performs the operation described with reference to FIGS. 2 and 3 and outputs the sync detection signals D3 and D4. Since it is an algorithm for detecting only frame synchronization, four x-bit shift registers having the frame synchronization bit interval length (503
506) is the frame detection algorithm ROM 502
It is connected to the. The data D0, D1, and D2 output in the frame detection algorithm are shifted in the frame synchronization bit interval length, and then input to A0, A1, and A2 by changing the algorithm stage. In addition, the hunt signal is sent to the frame protection unit 5 in A4 of the frame detection algorithm.
From 50, a signal indicating a synchronous state or a hunting state is input to change the frame detection algorithm. The output D4 of the frame detection algorithm is the D4 output one frame before by the shift register 506 having the frame synchronization bit interval length. Finally, the synchronization detection signal output from the frame detection unit is input to the frame protection unit after the output of D3 or D4 output from the frame detection algorithm ROM 502 is switched by the switch 509. The switch 509 is switched by a protection detection signal input from the frame protector. Next, the operation of the frame protection unit 550 will be described. The synchronization detection signal output from the frame detection unit 500 is input to the shift register 551. The input synchronization detection signal is selected by the multiplexer 560 in the multi-frame pulse in the synchronous state and the clock in the hunting state, and is shifted by the selected pulse. Value Q0 of shift register 551
A protection detection signal, a hunt signal, and a load signal are output by Q2.

First, the output of the protection detection signal will be described. As the front protection second stage, the values of Q0 and Q1 are inverted through the OR circuit (557) and then input to R of the RS flip-flop circuit 559. Further, the values of Q0 to Q2 are inverted through the NAND circuit 558 and then input to S of the RS flip-flop circuit. That is, when Q0 and Q1 do not continuously receive the synchronization detection signal, R-S
The flip-flop circuit 559 is reset, “L” is output to the switch 509, and the frame detection algorithm R
"Selection of B" which is the output D4 of the OM is performed. Also,
When the synchronization detection signal is received in all of Q0 to Q2, the RS flip-flop circuit 559 is set,
It is output as "H" to the switch 509, and "selection of A" which is the output D3 of the frame detection algorithm ROM 502 is performed.

Next, the output of the hunt signal will be described. First, the shift register 551 has three stages of front protection.
The values of Q0 to Q2 are inverted via the OR circuit 552 and then input to R of the RS flip-flop circuit 554.
The value of Q1 is input to the S flip-flop circuit 554 of the RS flip-flop circuit 554 after being inverted by the inverter circuit 553 as one backward protection stage. That is, Q0 to Q
When the sync detection signal is not received for all the values of 2, the RS flip-flop circuit is reset,
The hunting state is delayed by 1 bit (555), and then input to A4 of the frame detection algorithm ROM 502 of the frame detection unit 500 as a hunt signal. When the value of Q1 receives the synchronization detection signal, R
The -S flip-flop circuit 554 is set, and the fact that it is in the synchronous state is delayed by 1 bit (555) and then input to A4 of the frame detection algorithm ROM 502 as a hunt signal. These hunt signals change the algorithm of the frame detection algorithm ROM 502. In the synchronized state, the multi-frame pulse 561 input to the multiplexer 560 from the timing unit (not shown) is selected, and in the hunting state, the clock 562 is selected. When this clock is selected, the frame synchronization shifted by 1 bit is detected.

Next, the load signal will be described. The hunt signal output from the RS flip-flop circuit 554 is delayed by the delay circuit 563 by the three stages of front protection and one stage of rear protection.
Then, the load signal is output to the timing section via the AND circuit between the value after being delayed and inverted (564) and the value of the hunt signal input one bit later. That is, the load signal is output when the hunting state changes to the synchronization state.

In this way, the frame protection circuit performs forward protection and backward protection, and the frame detection algorithm in the frame detection circuit is changed according to the result of the protection.
In addition, the probability of out-of-frame synchronization is reduced by effectively using not only the final stage of the algorithm but also the previous stage of the final stage, so adaptive frame detection protection can be performed even if the number of frame synchronization bits is small.

[0021]

As described above, according to the present invention, in the frame detection protection circuit for monitoring the distributed frame synchronization bits at multiple points, the multipoint monitoring algorithm includes the first and second algorithms, -When the synchronization loss is detected a predetermined number of times from the frame synchronization state, the algorithm is switched, so that it is possible to reduce the probability that frame synchronization will be lost due to an error that has occurred in the transmission path, and as a result, the data transmission It has the advantage that the occurrence of interruptions can be reduced.

When the number of frame synchronization bits is small, the synchronization pull-in time may be long, which is particularly effective.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of a frame detection protection circuit showing an embodiment of the present invention.

FIG. 2 is a diagram showing a frame synchronization detection algorithm of a frame detection unit in the embodiment.

FIG. 3 is a diagram showing ROM data storing the frame synchronization detection algorithm in the embodiment.

FIG. 4 is a state transition diagram in the frame protection unit in the embodiment.

FIG. 5 is a detailed configuration diagram of a frame detection unit and a frame protection unit in the embodiment.

[Explanation of symbols]

100 frame detection unit 110 frame protection unit 120 timing unit 200 to 207 state of frame detection algorithm 208 selection output from step S7 of frame detection algorithm 209 selection output from step S6 of frame detection algorithm 210 delay circuit 211 switch 212 frames Protection detection signal input from the protection unit 213 Synchronization detection signal 400 Synchronization state 410 Front protection 1 stage 420 Front protection 2 stages 430 Front protection 3 stages 440 Hunting state 450 Back protection 1 stage 460 Selection when synchronization state continues 3 times 470 Selection in the second stage of front protection 500 Frame detection circuit 501 Signal input terminal 502 R in which frame detection algorithm is stored
OM 503 to 506 frame synchronization bit interval length x bit shift register 507 signal output from frame detection algorithm 508 signal output from frame detection algorithm 509 switch 550 frame protection circuit 551 shift register 552 OR circuit 553, 564 inverter 554, 559 RS flip-flop circuit 555,563 Delay circuit 556,562 Clock 557 OR circuit 558 NAND circuit 560 Multiplexer 561 Multi-frame pulse 565 AND circuit 570 input from timing part Sync signal 580 Protection detection signal 590 Hunt signal

Claims (1)

Claim: What is claimed is: 1. A frame detection protection circuit for monitoring multi-points of distributed frame synchronization bits, wherein the multi-points monitoring algorithm includes first and second algorithms, and frame synchronization is performed. A frame detection protection circuit, characterized in that the algorithm is switched when out of synchronization is detected a predetermined number of times from a state.