JPH0630479B2 - Frame synchronization method - Google Patents

Description

DETAILED DESCRIPTION [Overview] When the main synchronization counter is in a synchronization state, the backward protection time of the sub synchronization counter is set to be longer than that of the main synchronization counter, thereby causing an erroneous synchronization detection due to an error in received data. It is something that you should not do.

[Industrial application field]

The present invention relates to an improvement of a frame synchronization system used in a digital communication system such as PCM.

FIG. 5 is a block diagram of a frame synchronization circuit in principle, FIG. 6 (a) is a detection pulse detection state diagram, and FIG. 6 (b) is a synchronization state diagram.

In FIG. 5, the input PCM signal is converted in parallel by the shift register 1, and when the sync pattern is detected by the sync pattern detection unit 2, a sync pattern detection pulse (hereinafter, detected as sync pattern detection pulse) (Abbreviated as pulse) is applied to the synchronization protection unit 3.

Now, the detection pulse is sent from the synchronization pattern detection unit 2 to the synchronization protection unit 3 at the points a, b and f, g, h at the synchronization M determined as shown in FIG. It is assumed that it was not sent in point.

At this time, the synchronization protector 3 has a period M as shown in FIG. 6 (b).
If the detection pulse is continuously detected at, it is in the synchronization state,
The detection pulse is set to be out of synchronization if the detection pulse cannot be detected three times in succession from the synchronization state, and the synchronization state is set to be detected if the detection pulse can be detected twice in succession from the synchronization state. And

Therefore, as shown in FIG. 6 (a), the synchronization protection unit 3 determines that the state is in the synchronization state before e, is in the out of synchronization state from e to g, and is in the synchronization state after g.

It should be noted that c to e are parts of the forward protection that are considered to be in a synchronized state, and f to g
Is a backward protection portion that is regarded as out of synchronization for preventing pseudo synchronization, and e to f are hunting portions waiting for a synchronization pattern.

FIG. 7 shows a block diagram of the frame synchronization circuit.

In the figure, the synchronization pattern of the input PCM signal is detected by the synchronization pattern detection unit 2 which is composed of a shift register, for example. By this detection, the detection pulse sent from the detection unit 2 is added to the main synchronization counter 5 and the sub synchronization counter 6, and the pseudo synchronization detection unit 4 is driven at the timing of the main synchronization counter 5.

The pseudo-synchronization detection unit 4 substitutes, for example, M bits of the PCM signal into a predetermined arithmetic expression to obtain a value, the transmission side obtains the same method, compares with the value sent to the reception side, and does not match. If, for example, 6 times out of 10 times, the main synchronization counter 5 determines that it is in the pseudo synchronization state and outputs its output to the AND circuit 8
Add to.

Since the timing signal of the sub-synchronization counter 6 in the true synchronization state is added to the AND circuit 8, the timing signal of the sub-synchronization counter 6 is written in the main synchronization counter 5 determined to be in the pseudo-synchronization state. Rarely transits from the pseudo sync state to the sync state.

Therefore, the pseudo sync detection circuit 4 also operates at a new timing to determine again whether the next sync is true sync.

The AND circuit 7 prevents the sub synchronization counter 6 from synchronizing with the main synchronization counter 5.

FIG. 8 is another block diagram of the frame synchronization circuit, in which the main synchronization counter 5 is in the pseudo synchronization state and the out of synchronization state,
When the sub-sync counter 6 is in the true sync state, the timing signal of the sub-sync counter is written to the main sync counter 5 to bring it into the true sync state, so that the pseudo sync is prevented and the sync recovery time is shortened. Is.

Since the frame synchronization circuit determines the presence / absence of pseudo-synchronization, for example, by comparing the transmission / reception operation results, it may malfunction when the state of the transmission path is poor and the bit error rate is deteriorated.

Therefore, there has been a demand for a frame synchronization method that is less likely to malfunction even when the error rate is deteriorated.

[Conventional technology]

Generally, the sync pattern is detected by the frame sync circuit shown in FIG. 7 or FIG. 8, but the number of backward protection stages is set by the sub sync counter in the figure, and both the main sync counter and the sub sync counter are 2 It is stepped.

FIG. 9 is a block diagram of the sub-synchronization counter described above.
The figure shows the time chart of FIG.

Therefore, the operation of the sub-synchronization counter shown in FIG. 9 will be described with reference to FIG.

First, a clock is applied to the M-ary counter 10 and the quinary counter 11, and a detection pulse is applied to the gate circuit unit 12.

(1) If frame synchronization is established, quinary counter 1
The output of 1 becomes 1. When the output of the M-ary counter 10 is M: When the detection pulse is input, the output of the quinary counter 11 remains 1.

-If no detection pulse is input, the output of the quinary counter 11 becomes 2 and the front protection state is set.

・ If the detection pulse is not input 3 times or more continuously, 5
The output of the advance counter 11 becomes 4 and the hunting state is set.

In this state, the output of the M-ary counter 11 is fixed at M.

(2) In the hunting state, when a detection pulse is input, the output of the M-ary counter 10 becomes 1, the output of the quinary counter 11 becomes 5, and the rear protection state is entered.

(3) When the output of the quinary counter 11 is 5 and the output of the M-ary counter 10 is M: When the detection pulse is input, the output of the quinary counter 11 becomes 1 and the output of the M-ary counter 10 becomes 1 and is synchronized. Enter the state.

If the detection pulse is not input, the output of the M-ary counter 10 becomes 4 and the hunting state is set.

In order to operate the two counters in this manner, the gate circuit section 12 receives the signals of, and outputs the signals of ~ to perform the following control.

(5) The M-ary counter 10 is counting up by the EN signal except in the hunting state.

(6) The quinary counter 11 is a signal and is always 1 in the synchronous state.
The signal is controlled so that it is always 4 in the hunting state.

The EN signal causes the M-ary counter 10 to count up only when the output is M.

(7) The out-of-sync signal is output when the output of the quinary counter 11 is 4 and 5.

(8) The frame pulse is output when the output of the M-ary counter 10 is M and the output of the quinary counter 11 is 1 to 3.

FIG. 11 shows the state transition diagram of FIG.

The figure shows whether or not the detection pulse is detected.
When not detected, it indicates 0) how the counter operates, and the state shifts in the direction of the arrow for each bit of the input clock.

In the figure, the frame synchronization pattern is sent out in M bit cycles, and there are three stages in the front and two stages in the rear. In the two numbers arranged right, the right side shows the output of the M-ary counter, and the left side shows the output of the 5-ary counter. 1.1-1. M is a synchronous state, 2.1 to 3. M is in a state of forward protection, 4. M is a hunting state, 5.1 to 5.
M indicates the state of backward protection.

FIG. 12 (a) is a detection state diagram of a detection pulse of a conventional frame synchronization circuit using the sub synchronization counter shown in FIG. 9, and FIGS. 12 (b) and 12 (c) are main synchronization counter and sub synchronization counter. FIG.

Here, as described above, the number of front protection stages and the number of rear protection stages of the main and sub synchronization counters are set to three and two, respectively. That is, the number of backward protection steps is the same for both the main and sub synchronization counters.

In the figure, it is assumed that when the error rate of the transmission line is deteriorated, the sync pattern detecting section 2 shown in FIG. 7 outputs a detection pulse as shown in FIG. 12 (a).

Here, A is a detection pulse when a true synchronization pattern is detected, B is a detection pulse when a pseudo synchronization pattern generated in a PCM signal is detected, and M is a period.

The synchronization states of the main synchronization counter and the sub synchronization counter with respect to this detection pulse are shown in FIGS. 12 (b) and 12 (c). That is, (1) The main synchronization counter is synchronized with the output detection pulse A (enters the true synchronization state).

On the other hand, the sub-synchronization counter is in the hunting state because the detection pulse A is not input by the AND circuit 7.

(2) However, the sub-synchronization counter detects the detection pulse B and enters the backward protection state, but since the detection pulse is detected twice consecutively in the cycle M, it enters the synchronization state.

(3) Since the error rate of the transmission line has deteriorated, A
Erroneously determines that the main synchronization counter that is in synchronization with is in the pseudo synchronization state, the timing of the sub synchronization counter is written in the main synchronization counter, and the main synchronization counter enters the pseudo synchronization state.

(4) The sub-sync counter was synchronized with B, but since the main sync counter was synchronized with B, B is not input to the sub-sync counter as in (1). Therefore, the sub-synchronization counter enters the hunting state from the 3-step forward protection.

On the other hand, the main synchronization counter enters the hunting state after the front protection because B is no longer input.

(5) Find the true sync pattern A for both the main sync counter and the sub sync counter.

(6) The main synchronization counter synchronizes with A through backward protection.
However, since the main synchronization counter is synchronized with A, A is not input to the sub synchronization counter and hunting is started again.

[Problems to be solved by the invention]

As described above, since the number of stages of backward protection of the main and sub sync counters is the same (the time of backward protection is the same), for example, when the error rate of the input PCM signal deteriorates, the pseudo synchronization is performed as described above. The detection circuit malfunctions, and the main synchronization counter in the true synchronization state writes the timing from the sub-synchronization counter in the pseudo synchronization state, resulting in the pseudo synchronization state.

[Means for solving problems]

The above problem is to input a sync pattern detection circuit for detecting a sync pattern and a sync pattern detection pulse from the sync pattern detection circuit, and when the pulse is correctly input for a predetermined backward protection time or longer, the sync state is set. When the main sync counter and the sub sync counter which become asynchronous when the pulse is not correctly input for a predetermined forward protection time and the sub sync counter when the pseudo sync of the main sync counter is detected A pseudo sync detection circuit for changing the timing of the main synchronization counter to the timing of the sub synchronization counter, and the backward protection time of the sub synchronization counter is longer than the backward protection time of the main synchronization counter at least in the synchronization state of the main synchronization counter. This is solved by the frame synchronization method of the present invention.

[Action]

The present invention prevents the sub-sync counter from being pulled into a pseudo sync pattern shorter than the back-guard time in the PCM signal by making the number of backward protection stages of the sub-sync counter longer than that of the main sync counter.

That is, when the main synchronization counter is in the true synchronization state, even if the pseudo synchronization detection unit mistakenly recognizes the pseudo synchronization due to the deterioration of the error rate, the main synchronization counter does not write an incorrect timing from the sub synchronization counter. Malfunction due to deterioration of error rate is prevented.

Then, stable frame synchronization is established.

〔Example〕

Hereinafter, the gist of the present invention will be specifically described with reference to the illustrated embodiments. The same reference numerals denote the same objects throughout the drawings.

FIG. 1 shows a block diagram of an embodiment of the present invention, and FIG. 2 shows a time chart.

As shown in the figure, in contrast to the main synchronization counter having two stages of backward protection, the sub-synchronization counter is set to 2 by the backward protection setting signal.
The operation of the sub-synchronous counter shown in FIG. 1 will be described with reference to FIG.

In the figure, the clock is applied to the M-ary counter 10 and the hexadecimal counter 13, and the detection pulse and the backward protection setting signal are applied to the gate circuit unit 14.

(1) If frame synchronization is established, hexadecimal counter 1
The output of 3 becomes 1. Then, when the output of the M-ary counter 10 is M: When the detection pulse is input, the output of the hexadecimal counter 13 remains 1, and the synchronization state is maintained.

-When the detection pulse is not input, the output of the hexadecimal counter 13 becomes 2 and the front protection state is set.

If the detection pulse is not input three times or more in succession, the output of the hexadecimal counter 13 becomes 4 and the hunting state occurs. In this state, the output of the M-ary counter 10 is fixed at M.

(2) In the hunting state, when the detection pulse is input, the output of the M-ary counter 10 becomes 1, the output of the hexadecimal counter 13 becomes 5, and the state of rear protection is entered.

(3) When the detection pulse is input when the output of the hexadecimal counter 13 is 5 and the output of the M-adic counter 10 is M: ・ If the rear protection setting signal is 0 (2 protection stages), 6
The output of the advance counter 13 is 1, and the output of the M-advance counter 10 is 1, which is in a synchronized state.

・ If the rear protection setting signal is 1 (3 protection stages), 6
The output of the advance counter 13 becomes 6 and remains in the rear protection state.

Then, if the detection pulse is not input thereafter, the output of the hexadecimal counter 13 becomes 4 and the hunting state is again established.

However, when the detection pulse is input, the output of the hexadecimal counter 13 becomes 1 and the synchronization state is established.

In order to operate the two counters in this way, the gate circuit section 14 receives the signals of ,,, and outputs the signals of ~ to perform the following control.

(4) The M-ary counter 10 is in the counter-up operation except the hunting state by the EN signal.

(5) The hexadecimal counter 13 is a signal and is always 1 in the synchronized state.
The signal is controlled so that it is always 4 in the hunting state.

The EN signal causes the M-ary counter 10 to count up only when the output is M.

(6) The output of the hexadecimal counter 13 is 4 for the out-of-sync signal.
It is output at 5 and 6.

(7) The frame pulse is output when the output of the M-ary counter 10 is M and the output of the hexadecimal counter 13 is 1 to 3.

(8) The output of the hexadecimal counter 13 is 5, the M-ary counter 1
When the output of 0 is M, the detection pulse is 1, and when the rear protection setting signal is 1, the output of the hexadecimal counter 13 changes from 5 to 6.

When the rear protection setting signal is 0, the hexadecimal counter 13 outputs 5 to 1.

That is, the hexadecimal counter 13 is controlled by the rear protection setting signal.

FIG. 3 shows a state transition diagram.

The figure shows how the counter operates according to the value of the detection pulse, and the state shifts in the direction of the arrow for each bit of the input clock.

Incidentally, 1.1 to 1. M is a synchronous state, 2.1 to 3. M is a front protection state, M is a hunting state, 5.1 to 6. M indicates the state of backward protection.

4 (a) is a detection state diagram of the detection pulse of the frame synchronization circuit using the sub synchronization counter of the present invention, and FIGS. 4 (b) and 4 (c) are synchronization state diagrams of the main synchronization counter and the sub synchronization counter. . Here, A is a detection pulse when a true sync pattern is detected, B is a detection pulse when a pseudo sync pattern is detected, and M is a cycle, and the number of backward protection steps of the main sync counter and the sub sync counter is two and three. Is set to.

In the figure, (1) Since the main synchronization counter is synchronized with A, the sub synchronization counter is in the hunting state and detects the input B. However, since this B is only repeated twice, rearward protection is not completed and the state of hunting is resumed.

(2) Since the main sync counter is synchronized with A, the sub sync counter cannot operate at the timing of A, and the probability of repeatedly entering the backward protection and hunting states and entering sync is low.

(3) Since the sub synchronization counter has a low probability of entering the synchronization state, the main synchronization counter has a high probability of maintaining the synchronization state.

Even in the case of a circuit that does not have the AND circuit 7 and operates the sub-sync counter only when pseudo sync is detected at the timing of the main sync counter 5, the number of backward protection stages of the sub-sync counter (same as the backward protection time). ) Is set to be longer than the number of steps of backward protection of the main synchronization counter to prevent pseudo synchronization.

〔The invention's effect〕

As described above, by increasing the number of backward protection stages of the sub-sync counter to be larger than that of the main sync counter, the probability of malfunction due to the deterioration of the error rate occurring in the transmission path can be reduced, and a stable frame can be obtained. Synchronization is established.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a time chart of FIG. 1, FIG. 3 is a state transition diagram of FIG. 1, and FIG. 4 (a) is a detection state diagram of detection pulses. 4 (b) and 4 (c) are synchronization state diagrams of the main and sub synchronization counters, FIG. 5 is a block diagram showing the principle of the frame synchronization circuit, and FIG. 6 (a) is a detection state diagram of detection pulses. FIG. 6 (b) is a synchronization state diagram, FIG. 7 is a block diagram of a frame synchronization circuit, FIG. 8 is a block diagram of another frame synchronization circuit, FIG. 9 is a block diagram of a conventional example, and FIG. The time chart of FIG. 11 and the state transition diagram of FIG. 9 are shown in FIG. FIG. 12 (a) is a detection state diagram of the detection pulse, and FIGS. 12 (b) and 12 (c) are synchronization state diagrams of the main and sub synchronization counters. In the figure, 2 is a sync pattern detection unit, 4 is a pseudo sync detection unit, 5 is a main sync counter, 6 is a sub sync counter, 10 is an M-ary counter, 11 is a 5-ary counter, 12 and 14 are gate circuits, 13 is Indicates a hexadecimal counter. Reference numerals 7 and 8 denote AND circuits.

Front page continued (72) Inventor Michinobu Ohata 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa, Fujitsu Limited (72) Inventor Takao Moriya 1015, Kamedotachu, Nakahara-ku, Kawasaki, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Toshinari 1-16 Uchisaiwaicho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation (72) Inventor Ikuo Washiyama 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation (56 ) Reference JP-A-59-183544 (JP, A)

Claims (1)

[Claims] 1. A receiving side of a digital transmission system that transmits a synchronization pattern at regular intervals, inputs a synchronization pattern detection circuit for detecting the synchronization pattern, and a synchronization pattern detection pulse from the synchronization pattern detection circuit. Of the main synchronization counter and the sub-synchronization counter, which become synchronous when a pulse is correctly input for a predetermined backward protection time or longer and become asynchronous when a pulse is not correctly input for a predetermined forward protection time or longer A pseudo sync detection circuit is provided for changing the main sync counter to the timing of the sub sync counter when the sub sync counter is in the sync state when the pseudo sync is detected. The backward protection time of the sub-sync counter is longer than the backward protection time of the main sync counter. Frame synchronization method.