JPS6248826A - Frame synchronizing system - Google Patents

Abstract

PURPOSE:To prevent a sub synchronizing counter from being locked to a speudo synchronizing pattern shorter than the backward protecting time in a PCM signal by adopting the design that the number of stages for the backward protection of the sub synchronizing counter is increased more than that of a main synchronizing counter. CONSTITUTION:A clock is fed to an M-adic counter 16 and a 6-adic counter 13 and a detection pulse and a backward protection setting signal are fed to a ate circuit section 14. When the frame synchronization is established, the output of a counter 13 is '1'. When the output of the counter 10 is M and the detection pulse is inputted, the output of the counter 13 remains logical '1' to keep the synchronizing state. When no detection pulse is inputted, the output of the counter 13 is '2', which represents the forward protection. In the state of hunting, when the detection pulse is inputted, the output of the counter 10 is '1', the output of the counter 13 is '5', and the state of the backward protection is obtained. When the output of the counter 13 is '5' and the output of the counter 10 is M and the detection pulse is inputted with the backward protection setting signal at logical '1', the output of the counter 13 is '1' and the output of the counter 10 is '1' to set the synchronizing state.

Description

[Detailed Description of the Invention] [Summary] When the main synchronization counter is in a synchronized state, setting the backward protection time of the sub-synchronization counter longer than that of the main synchronization counter prevents malfunction due to incorrect synchronization detection due to received data error. This is to prevent it from happening.

[Industrial application field]

The present invention relates to an improvement in a frame synchronization method used in a digital communication method such as PCM.

FIG. 5 is a block diagram of the principle frame synchronization circuit, FIG. 6(a) is a detection state diagram of a detection pulse, and FIG. 6 (bl is a synchronization state diagram).

In FIG. 5, an input PCM signal is converted into parallel signals by a shift register 1, and when a synchronization pattern is detected by a synchronization pattern detection unit 2, a synchronization pattern detection pulse (hereinafter referred to as detection (abbreviated as pulse) is applied to the synchronization protector 3.

Now, detection pulses are sent from the synchronization pattern detection section 2 to the synchronization protection section 3 at points a, b, f, g, and h at the synchronization M determined as shown in FIG. Suppose that the point is not sent.

At this time, as shown in FIG. 6(b), the synchronization protection unit 3 is closed!
If the detection pulse is detected continuously at tI]M, the device is in a synchronized state, and if the detection pulse cannot be detected, for example, three times in a row from the synchronized state, it is in an out-of-synchronization state, and if the detection pulse is continuously detected from the out-of-synchronization state. Suppose that the setting is such that, for example, if it is detected twice, it is determined that the synchronization state has entered.

Therefore, this synchronization protection section 3 is
6 x g is out of sync, g
From then on, it is determined that they are in a synchronous state.

Incidentally, c''-e is a forward protection portion and a hunting portion that are considered to be in a synchronous state.

FIG. 7 shows a block diagram of the frame synchronization circuit.

In the figure, a synchronization pattern of an input PCM signal is detected by a synchronization pattern detection section 2 composed of, for example, a shift register. Through this detection, the detection pulse sent from the detection section 2 is added to the main synchronization counter 5 and the sub-synchronization counter 6, and the pseudo-synchronization detection section 4 is driven at the timing of the main synchronization counter 5.

This pseudo-synchronization detection unit 4 calculates a value by substituting, for example, the M bit of the PCM signal into a predetermined arithmetic expression, calculates it in the same way on the transmitting side, and compares it with the value sent to the receiving side, and determines whether there is a discrepancy. If the number of times is, for example, 6 out of 10, the main synchronization counter 5 determines that it is in a pseudo synchronization state, and the output is sent to the AND circuit 8.
Add to.

For example, since the timing signal of the sub-synchronous counter 6 which is in a true synchronous state is added to the AND circuit 8, the timing signal of the sub-synchronous counter 6 is written to the main synchronous counter 5 which is determined to be in a pseudo-synchronous state. Rarely transitions from a pseudo-synchronous state to a synchronous state.

Therefore, the pseudo synchronization detection circuit 4 also operates at a new timing, and again judges whether the next synchronization is a true synchronization.

Incidentally, the AND circuit 7 prevents the sub-synchronous counter 6 from synchronizing with the main synchronous counter 5.

FIG. 8 is another block diagram of the frame synchronization circuit, in which the main synchronization counter 5 is in a pseudo-synchronization state and an out-of-synchronization state,
When the sub-synchronization counter 6 is in a true synchronization state, the timing signal of the sub-synchronization counter is written to the main synchronization counter 5 to bring it into a true synchronization state, thereby preventing false synchronization and shortening the synchronization recovery time. It is.

The above-mentioned frame synchronization circuit judges the presence or absence of pseudo synchronization by, for example, collating the calculation results of transmission and reception, so it may malfunction when the transmission path is in poor condition (and the bit error rate is worsening).

Therefore, there is a need for a frame synchronization method that is less likely to malfunction even when the error rate is worsening.

[Conventional technology]

Generally, the synchronization pattern is detected by the frame synchronization circuit shown in FIG. It is tiered.

FIG. 9 is a block diagram of the above-mentioned sub-synchronization counter, and the 10th
The figure shows the time chart of FIG.

Therefore, the operation of the sub-synchronization counter shown in FIG. 9 will be explained with reference to FIG.

First, a clock (2) is applied to the M-ary counter 10 and the 5-ary counter 11, and a detection pulse is applied to the gate circuit section 12.

+11 When frame synchronization is established, the output ■ of the quinary counter 11 becomes 1. And M-ary counter 10
When the output ■ is M, when the detection pulse ■ is input, the output ■ of the quinary counter 11 remains at 1.

- If the detection pulse ■ is not input, the output ■ of the quinary counter 11 becomes 2, and the forward protection state is entered.

・If the detection pulse does not input 3 or more times in a row, 5
The output of the digit counter 11 becomes 4, which is a re-inching state.

In this state, the output {circle around (2)} of the M-ary counter 11 is fixed at M.

(2) In the hunting state, when the detection pulse ■ is input, the output ■ of the M-adic counter 10 becomes the state 1, and the output ■ of the quinary counter 11 becomes 5, entering the rearward protection state.

(3) When the output ■ of the quinary counter 11 is 5 and the output ■ of the M-ary counter 10 is M, when the detection pulse ■ is input, the output of the quinary counter 11 is ■
becomes 1, and the output ■ of the M-adic counter 10 becomes 1, entering a synchronized state.

, if the detection pulse ■ is not input, the output ■ of the M-ary counter 10 becomes 4, resulting in a hunting state.

In order to operate the two counters in this manner, the gate circuit section 12 receives the signals ①, ②, ② and outputs the signals ② to [phase] to perform the following control.

(Due to the 51EN signal ■, the M-ary counter 10 operates as a count amplifier except in the hunting state.

(6) The quinary counter 11 is always 1 in the synchronized state with the signal ■.
In addition, the signal ■ is controlled so that the value is always 4 in the hunting state.

Further, by the EN signal ■, the count/amplification is performed only when the output ■ of the M-ary counter 10 is M.

(7) Out-of-synchronization signal ■ is output when the output of the quinary counter 11 is 4 and 5.

(8) The frame pulse [phase] is output when the output (2) of the M-ary counter 10 is M and the output (2) of the 5-ary counter 11 is 1-3.

FIG. 11 shows the state transition diagram of FIG.

The figure shows depending on whether or not a detection pulse is detected (1 when detected,
When not detected, O) This shows how the counter operates, and the state shifts in the direction of the arrow for each input bit.

The figure shows a case where a frame synchronization pattern is sent out at an M-bit period, with 3 stages at the front and 2 stages at the rear. 1.1-1. M is a synchronous state, 2.1-3. M is forward protection state; 4. M is the state of hunting, 5.1-5.
M indicates the state of rear protection.

FIG. 12 (al is a detection state diagram of the detection pulse of the conventional frame synchronization circuit using the sub-synchronization counter shown in FIG. 9,
FIG. 12 (bl and (C)) shows a synchronization state diagram of the main synchronization counter and the sub-synchronization counter.

Here, as described above, the number of forward protection stages of the main and sub synchronization counters was set to three stages, and the number of backward protection stages was set to two stages. That is, the number of backward protection stages is the same for both the main and sub synchronization counters.

In the figure, it is assumed that a detection pulse as shown in FIG. 12+al is output from the synchronization pattern detection section 2 shown in FIG. 7 when the error rate of the transmission path is degraded.

Here, A: Detection pulse when the true synchronization pattern is detected B: P
Detection pulse M: indicates the period when a pseudo synchronization pattern occurring in a CM signal is detected.

The synchronization state of the main synchronization counter and the sub-synchronization counter with respect to this detection pulse is shown in FIG. 12 (bl and (C)).

(1) The main synchronization counter is synchronized with the output detection pulse A (in a true synchronization state).

On the other hand, the sub-synchronous counter is in a hunting state because the AND circuit 7 does not input the detection pulse A.

(2) However, the sub-synchronization counter detects the detection pulse B and enters the backward protection state, but since the detection pulse is detected twice in a row with the cycle M, it enters the synchronization state.

(3) Since the error rate of the transmission path has deteriorated, as mentioned above, A
The main synchronization counter that is synchronized with the main synchronization counter is mistakenly judged to be in a pseudo-synchronization state, the timing of the sub-synchronization counter is written to the main synchronization counter, and the main synchronization counter enters the pseudo-synchronization state.

(4) The secondary synchronization counter was synchronized with B, but since the main synchronization counter was synchronized with B, B is no longer input to the secondary synchronization counter as in (1). Therefore, the sub-synchronous counter enters the hunting state from the three-stage forward protection.

On the other hand, since B is no longer input to the main synchronization counter, the main synchronization counter goes through forward protection and enters a hunting state.

(5) Find A, which is a true synchronization pattern for both the main synchronization counter and the sub-synchronization counter.

(6) The main synchronization counter is synchronized with A through backward protection.

However, since the main synchronization counter has synchronized to 8, 8 is not input to the secondary synchronization counter, and hunting starts again.

[Problem that the invention seeks to solve]

As mentioned above, since the number of stages of backward protection of the main and sub synchronization counters is the same (the time of backward protection is the same), for example, when the error rate of the input PCM signal deteriorates, pseudo synchronization is performed as shown above. The detection circuit malfunctions, and the main synchronization counter, which is in a true synchronization state, is written with the timing from the sub-synchronization counter, which is in a pseudo-synchronization state, resulting in a pseudo-synchronization state.

[Means for solving problems]

The above problem is that a synchronization pattern detection circuit detects a synchronization pattern, and a synchronization pattern detection pulse from the synchronization pattern detection circuit is input, and when the pulse is correctly input for a predetermined backward protection time or more, a synchronization state is achieved. The main synchronization counter and the sub-synchronization counter become unsynchronized when the pulse is not correctly input for a predetermined forward protection time, and the sub-synchronization counter becomes synchronized when one pseudo interval of the main synchronization counter is detected. In this case, a pseudo synchronization detection circuit is provided to change the timing of the main synchronization counter to the timing of the sub-synchronization counter, and at least in the synchronized state of the main synchronization counter, the backward protection time of the sub-synchronization counter is set to the backward protection time of the main synchronization counter. This problem is solved by the longer frame synchronization method of the present invention.

[Effect]

The present invention prevents the secondary synchronization counter from being drawn into a pseudo synchronization pattern shorter than the backward protection time in the PCM signal by making the number of backward protection stages of the secondary synchronization counter longer than that of the main synchronization counter.

That is, when the main synchronization counter is in a true synchronization state, even if the pseudo synchronization detection section misidentifies pseudo synchronization due to deterioration of the error rate, an incorrect timing will not be written to the main synchronization counter from the sub synchronization counter. Malfunctions due to deterioration of error rate are prevented.

Therefore, stable frame synchronization is established.

〔Example〕

The gist of the present invention will be specifically explained below with reference to illustrated embodiments. Note that the same reference numerals refer to the same objects throughout the plan.

FIG. 1 shows a block diagram of an embodiment of the present invention, and FIG. 2 shows a time chart.

As shown in the figure, while the main synchronization counter has two stages of backward protection, the secondary synchronization counter has two stages according to the backward protection setting signal ■.
The operation of the sub-synchronous counter shown in FIG. 1 will be explained with reference to FIG. 2.

In the figure, a clock ■ is applied to an M-ary counter 10 and a hexadecimal counter 13, and a detection pulse ■ and a backward protection setting signal ■ are applied to a gate circuit section 14.

(1) When frame synchronization is established, the output ■ of the hexadecimal counter 13 becomes 1. And M-ary counter 10
When the output ■ is M, when the detection pulse ■ is input, the output ■ of the hexadecimal counter 13 remains 1, maintaining the synchronized state.

- If the detection pulse ■ is not input, the output ■ of the hexadecimal counter 13 becomes 2, and the forward protection state is entered.

- If the detection pulse ■ is not input three or more times in succession, the output ■ of the hexadecimal counter 13 becomes 4, resulting in a hunting state. In this state, the output of the M-ary counter 10 is fixed at M.

(2) In the hunting state, when the detection pulse ■ is input, the output ■ of the M-ary counter 10 becomes 1, and 6
The output ■ of the advance counter 13 becomes 5 and enters the rear protection state.

+3 If the detection pulse ■ is input when the output ■ of the hexadecimal counter 13 is 5 and the output ■ of the M-ary counter 10 is M, - If the backward protection setting signal ■ is 0 (the number of protection stages is 2), the output is 6.
The output ■ of the hexagonal counter 13 becomes 1, and the output ■ of the Maryx counter 10 becomes 1, resulting in a synchronized state.

・When the rear protection setting signal ■ is 1 (the number of protection stages is 3),
The output {circle around (2)} of the hex counter 13 becomes 6 and remains in the backward protection state.

If the detection pulse (2) is not input thereafter, the output (2) of the hexadecimal counter 13 becomes 4 and the hunting state occurs again.

However, when the detection pulse ■ is input, the output ■ of the hexadecimal counter 13 becomes 1, resulting in a synchronized state.

In order to operate the two counters in this manner, the gate circuit section 14 receives the signals ■, ■, ■, ■, outputs signals from ■ to [phase], and performs the following control.

(4) Due to the EN signal ■, the M-ary counter 10 operates as a counter amplifier except in the hunting state.

(5) The hexadecimal counter 13 is always 1 in the synchronized state with the signal ■.
In addition, the signal ■ is controlled so that the value becomes exactly 4 in the hunting state.

Further, the count is increased only when the output (2) of the M-ary counter 10 is M by the EN signal (2).

(6) Out-of-synchronization signal ■ indicates that the output of the hexadecimal counter 13 is 4.
Output at 5.6.

(7) The frame pulse [phase] is output when the output (2) of the M-ary counter 10 is M and the output (2) of the hexadecimal counter 13 is 1-3.

(8) Output ■ of hexadecimal counter 13 is 5, M-ary counter 1
When the 0 output ■ is M, the detection pulse ■ is 1, and the backward protection setting signal ■ is 1, the output of the hexadecimal counter 13 changes from 5 to 6.

- When the rear protection setting signal ■ is O, the output ■ of the hexadecimal counter 13 changes from 5 to 1.

That is, the hexadecimal counter 13 is controlled by the rear protection setting signal.

FIG. 3 shows a state transition diagram.

The figure shows how the counter operates depending on the value of the detection pulse, and the state shifts in the direction of the arrow for each bit of the input clock.

In addition, 1.1 to 1. M is a synchronous state, 2.1-3. M is forward protection state; 4. M is a hunting state, 5.1 to 6. M indicates the state of rear protection.

4(a) is a detection state diagram of a detection pulse of a frame synchronization circuit using the sub-synchronization counter of the present invention, and FIGS. 4(b) and fc) are synchronization state diagrams of the main synchronization counter and the sub-synchronization counter. Here, A: detection pulse when a true synchronization pattern is detected B; detection pulse amount when a pseudo synchronization pattern is detected: period, and the number of backward protection stages of the main synchronization counter and sub synchronization counter is 2 stages and 3 stages. is set to .

In the figure: (1) Since the main synchronization counter is synchronized with A, the sub-synchronization counter is in a hunting state and detects input B. However, since this B occurs only twice in a row, the rear protection does not end and the vehicle enters the hunting state again.

(2) Since the main synchronization counter is synchronized to 8, the sub synchronization counter cannot operate at timing A, and the probability of entering synchronization after repeating backward protection and hunting states is low.

(3) Since the probability of the secondary synchronization counter entering the synchronization state is low, the probability of maintaining the synchronization state of the main synchronization counter is high.

Note that even in the case of a circuit that does not include the AND circuit 7 and operates the sub-synchronization counter only when pseudo-synchronization is detected at the timing of the main synchronization counter 5, the number of backward protection stages of the sub-synchronization counter (same as the backward protection time) ) is made longer than the number of backward protection stages of the main synchronization counter to prevent false synchronization.

〔Effect of the invention〕

As explained above, by making the number of backward protection stages of the sub-synchronization counter larger than that of the main synchronization counter, it is possible to reduce the probability of malfunction due to deterioration of the error rate that occurs in the transmission path, and to maintain a stable frame. Synchronization is established.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
Figure 3 is the state i transition diagram of Figure 1, Figure 4 (al is the detection state diagram of the detection pulse, Figure 4 (b)
and (C) are synchronization state diagrams of the main and sub synchronization counters, FIG. 5 is a principle block diagram of the frame synchronization circuit, FIG. 6 (al is a detection state diagram of detection pulses, and FIG. 6 (bl is a synchronization state diagram) , Fig. 7 is a block diagram of a frame synchronization circuit, Fig. 8 is a block diagram of another frame synchronization circuit, Fig. 9 is a block diagram of a conventional example, Fig. 10 is a time chart of Fig. 9, and Fig. 11 is a block diagram of a frame synchronization circuit. The state!3 transition diagram of Figure 9 is shown. Figure 12 (al is a detection state diagram of the detection pulse, Figure 12 (
b) and (C1 shows a synchronization state diagram of the main and sub-synchronization counters. In the figure, 2 is a synchronization pattern detection section, 4 is a pseudo-synchronization detection section, 5 is a main synchronization counter, 6 is a sub-synchronization counter, 10 is M 11 is a quinary counter, 12.14 is a gate circuit, 13 is a hexadecimal counter. 7 and 8 are AND circuits. )"mouth·
77 Leap Figure 1 Melo 1 Direction 3t Rise Back 1 Dagger 2 #9/3 葭 127 沓萬 Figure 1 Counter down and transition diagram Figure 3 Fushi 1 4 Synchronous circuit opening・Fig. 72 No. 5 Fig. 1 Synchronous 4 Atmosphere -j- Synchronous outside materials 11 Synchronous Ai! - Figure 5 - Figure 5 - Figure 5 Figure L - Group of synchronizing circuits, thin frame Figure 7 Figure 7 Figure 7・Schiff diagram Conventional shi1 synchronized sword Tsutsu 100...l diagram Figure 9

Claims (1)

[Claims] On the receiving side of a digital transmission system that transmits a synchronization pattern at regular intervals, a synchronization pattern detection circuit detects the synchronization pattern, and a synchronization pattern detection pulse from the synchronization pattern detection circuit is input, a main synchronization counter and a sub-synchronization counter that enter a synchronous state when the pulse is correctly input for a predetermined backward protection time or longer, and enter an asynchronous state when the pulse is not correctly input for a predetermined forward protection time; and a pseudo-synchronization detection circuit that changes the timing of the main synchronization counter to the timing of the sub-synchronization counter if the sub-synchronization counter is in the synchronization state when detecting the pseudo-synchronization of the main synchronization counter, at least in the synchronization state of the main synchronization counter. A frame synchronization method characterized in that a backward protection time of the secondary synchronization counter is longer than a backward protection time of the main synchronization counter.