JP2705443B2 - Transmission frame timing generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission frame timing generation circuit, and more particularly to a transmission frame timing generation circuit for a time-division multiple access device having a working and a protection.

[0002]

2. Description of the Related Art As shown in FIG. 2, a conventional transmission frame timing generation circuit inputs a reference timing signal 111 input from the outside and a frame timing signal 112 of an output signal of a frame counter circuit 102 to be described later. The OR circuit 101 includes a OR circuit 101 that outputs a logical value, and a frame counter circuit 102 that is initialized by an OR circuit output signal and counts a frame period. Here, when the time division multiple access device adopts a working spare configuration, the working and the spare are independently synchronized.

[0003]

This conventional frame timing generation circuit generates a transmission frame timing synchronized with the reference timing signal by being initialized by an externally input reference timing signal. However, in order to improve the reliability of the device, when the active and standby systems are configured, the active system and the standby system exist independently, and there is a disadvantage that the transmission frame timing of the active and standby system cannot be synchronized.

[0004]

Transmission frame timing generator circuit of the present invention, in order to solve the problem] is the transmission frame timing generator for their split multiple access device to take the working preconfigured,
Input the working spare switching control signal from outside and select the working side
The first signal indicating synchronization is "low" level
And indicates whether it is asynchronous or synchronous when the standby side is selected.
If a second signal is input and this second signal is asynchronous
The first signal is set to a “high” level, and the second signal is
The first signal is transmitted when the signal is synchronous.
Protection game that determines that it is within the expected
Protection gate generation circuit to be used as an external signal and input from outside
Inputting a frame pulse and the first signal to take a logical value
AND circuit, and output from this AND circuit and input from outside
Reference timing signal and external preliminary input
Switching signal is input and the working protection switching signal indicates the working side.
Select the reference timing signal,
If the signal indicates the standby side, the AND circuit
A selection circuit for selecting and outputting a force, and an output signal of the selection circuit
And the third signal, and outputs the logical value of the two signals.
Or circuit that is initialized and initialized by this OR circuit output.
A frame for counting a frame period and outputting the third signal
A counter circuit, the AND circuit output and the first signal;
Signal and output a periodic signal indicating that the AND circuit output is normal.
Outputting the second signal for determining whether the signal is being applied
And a synchronous state determination circuit.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention. When the transmission frame timing generation circuit forms a working configuration and a backup configuration, a transmission frame timing signal specified by another system is input to the AND circuit 2 as a frame timing pulse 12. The AND circuit 2 receives the frame timing pulse 12 and the gate signal 16 as an output signal of the protection gate generation circuit 3 described later, and permits the passage of the timing pulse 12 during the time when the gate signal 16 is "high" to perform an AND operation. Circuit 2 outputs and sends out to signal 15.
The selection circuit 1 receives a signal 15, a reference timing signal 11, and a working protection switching signal 13 input from the outside, selects the signal 11 when the signal 13 indicates working, and the signal 13 indicates protection. If so, the signal 15 is selected and the selection circuit output signal 19 is output. The OR circuit 5 receives a signal 19 and a signal 14 as an output of a frame counter circuit 6 described later, and outputs a logical value of the two signals as an output signal 20 of the OR circuit 5. The frame counter circuit 6 receives the signal 20, is initialized by the signal 20, counts the frame period, and when the counted value becomes the final value of the frame,
At the same time as outputting the transmission frame timing signal 14 as a signal indicating the head of the frame, the input prediction timing signal 18 of the signal 12 input from the outside is output. Signal 1
The signal 4 is fed back to the frame counter circuit 6 via the OR circuit 5, so that the frame counter circuit 6 automatically operates at the frame period unless the signal 19 is input.
The running frame counter circuit 6 is provided. The protection gate generation circuit 3 receives a working spare switching signal 13 input from the outside, a frame counter circuit 6 output signal 18 and an output 17 of a synchronization state determination circuit 4 described later, and outputs a gate signal 16. The gate signal 16 is always in a "low" state when the signal 13 indicates the working side, and the frame pulse signal 12
Are prohibited from passing through the AND circuit 2. Also, signal 13
Indicates the standby side, and when the signal 17 indicates the asynchronous state, the signal 16 is always "high".
Output the protection gate signal 16 at the timing indicated by the signal 18 when the signal indicates the synchronous state. By taking the logical product of the signal 16 and the signal 12, the operation of protecting the condition for capturing the signal 12 is performed. The synchronization state determination circuit 4 receives the signal 15 and the signal 16 and
To determine whether the signal 15 is correctly input. If the signal 15 is correctly input, it is determined that the frame counter circuit 6 and the signal 12, that is, the transmission frame counter of the other system are synchronized. Then, the synchronization state signal 17 is output. The synchronization state determination circuit 4 can be easily obtained by a front and rear protection circuit which can be realized by, for example, a shift register and an AND gate. When the gate width of the protection gate is set to N (N is a positive integer), the timing of the transmission frame timing generation circuit of the own system is changed to that of the other system (working system) when the own system is in standby. Synchronization can be performed after initialization using the transmission frame timing. However, once synchronization is established, the active frame counter circuit 6 malfunctions and the active system frame pulse 1
If 2 is input at a position shifted by N / 2 bits or more,
Synchronizing with this frame pulse signal 12 is prohibited,
By self-running, the transmission frame timing when the working system is operating normally can be maintained and the transmission frame timing can be continuously generated.

[0006]

As described above, according to the present invention, when the frame counter circuit of the own system is on the standby side, the timing of the active system is correct by taking the logical value with the protection gate for the transmission frame timing input from the active system. In this case, if the operation of the active system becomes abnormal once in synchronization with the active system,
By self-running at the timing when the active system was operating correctly without using the timing of the active system, there is an effect that the correct transmission frame timing can be maintained.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a block diagram of a conventional transmission frame timing generation circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 selection circuit 2 AND circuit 3 protection gate generation circuit 4 synchronization state determination circuit 5 OR circuit 6 frame counter circuit 11 reference timing signal 12 frame pulse signal 13 active spare switching control signal 14 transmission frame timing signal 15, 19, 20 output signal 16 Protection gate signal 17 Synchronization state signal 18 Gate timing signal 101 OR circuit 102 Frame counter 111 Reference timing signal 112 Transmission frame timing signal

Claims (1)

(57) [Claims] 1. A transmission frame timing generator for their split multiple access device to take the working preconfigured, external
The working protection switching control signal is input and the working side is selected.
In this case, the first signal indicating the synchronization is set to the “low” level, and
The second that indicates whether asynchronous or synchronous when the device side is selected
Input a signal, and when the second signal is asynchronous, the second signal
1 signal is set to the “high” level, and the second signal is synchronized.
In this case, the first signal is synchronized with the transmission frame timing.
Protection gate signal to determine that the
Protection gate generation circuit and external input frame
AND operation for receiving a pulse and the first signal and taking a logical value
Path, the AND circuit output and a reference input from outside.
Imming signal and external working switching signal input from outside
Input and the working protection switching signal indicates the working side.
Selects the reference timing signal, and the working spare switching signal
Select the AND circuit output when the equipment side is instructed
A selection circuit for outputting, an output signal of the selection circuit, and a third
And outputs the logical value of these two signals.
Circuit and the frame circuit initialized by this OR circuit output.
Frame counter for counting a period and outputting the third signal
A circuit, inputting the AND circuit output and the first signal
And a periodic signal indicating that the AND circuit output is normal is output.
Synchronizing to output the second signal to determine whether
A transmission frame timing generation circuit , comprising: a state determination circuit.