JPH0656954B2 - Duplex switching system of timing signal generator - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a duplexing switching system of a timing signal generator which counts a synchronization clock of a phase synchronization means to generate a timing signal.

[Conventional technology]

FIG. 7 is a block diagram for explaining the conventional duplex switching system shown as “bus SW mode” in FIG. 1 of NTT Facility VOL.38 No.5, 1986, P74. In the same figure, the conventional duplex switching method inputs the input signal (1a) output from the first system device on the opposite side (not shown) and outputs the output signal (1b), and at the same time, outputs the failure alarm signal (1d )
The input signal (2a) output by the first system device (1) of the terminal repeater (or multiplex conversion device) that outputs the signal and the second system device of the opposite side (not shown) is input and the output signal ( 2b) 2nd system device of terminal repeater (or multiplex converter) that outputs 2b)
And a monitoring control device (8) that monitors the fault alarm signal (1d) and outputs a control signal (1e), and an output signal (1b) or an output signal (1b) at the instruction of the control signal (1e) of the monitoring control device (8). A switch (7) for selecting any one of (2b) and outputting it as an output signal (1c) is provided.

The input signals (1a) and (2a) input to the first and second system devices (1) and (2) are the same under normal conditions, and the output timing signals (2a) and (2b) are also the same. Is.

Next, the operation of the above conventional method will be described. The supervisory controller (8) monitors the fault alarm (1d) and controls the switch (7) to select the first system device (1) when there is no fault, and the second system device when the fault occurs. Control switch (7) to select (2).

In FIG. 8, (1b) is the output signal of the first system device (1), (2b)
Is the output signal of the second system device (2), (1c) is the output signal of the switch (7), and the output signal (1c) is switched from the output signal (1b) to the output signal (2b) at the timing of switching occurrence. Replace

[Problems to be Solved by the Invention]

The conventional duplex switching method is configured as above,
When the timing signal generator is duplicated with the conventional configuration, the output timing signals of the first system and the second system are independently generated as shown in FIG. There is a problem that the phase of the timing signal is displaced.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a duplexing switching system of a timing signal generator that suppresses the phase shift of the timing signal to the clock phase difference immediately after switching.

[Means for Solving the Problems]

The duplexing switching system of the timing signal generator according to the present invention inputs the input clocks of the same synchronized phase to the duplicated timing signal generators and outputs the timing signal of one timing signal generator in the operating state to 1 / 2
Bit delay is performed, and the count value of the counting means that counts the input clock in the other timing signal generating device is returned to the initial value by this delay signal and the timing signal of the other timing signal generating device in the non-operation state, and the above-mentioned operation In this configuration, one timing signal generator in one state is switched to another timing signal generator in a non-operation state.

[Action]

The duplex switching system of the timing signal generator in this invention is a counting circuit for generating a timing signal of a timing signal generator in a non-operating state by delaying a timing signal of the timing signal generator in an operating state by 1/2 bit. Since the count is returned to the initial value, the phase shift between the output timing signal in the operating state and the output timing signal in the non-operating state is calculated by the synchronous clock output by the phase synchronization circuit in each operating and non-operating timing signal generator. By suppressing the phase difference, the displacement of the phase that occurs when the operating signal signal generator and the non-operational timing signal generator are duplexed is minimized.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 to 6. FIG. 1 shows a block diagram of the entire circuit of this embodiment system. In FIG. 1, the duplex switching system of the timing signal generator according to this embodiment is in phase synchronization with an input clock (10a) input from the outside. Phase synchronization circuit (1a) that generates a stable and stable synchronization clock (11a) (or (12a))
1) (or (12)) and the synchronization clock (11a) (or (12a)) of the phase synchronization circuit (11) (or (12)) are counted and the timing signal (21) (or ( 22a)) generating counting circuit (21)
(Or (22)) and the output timing signal (21a) (or (22)) of the counting circuit (21) (or (22)) is delayed by 1/2 bit.
First-system (or second-system) timing signal generator (1) (or two-bit delay circuit (61) (or (62)))
(2)) is duplicated and the output timing signal (21a) of the timing signal generator (1) of the 1st system in the operating state is provided.
The 1/2 bit delay circuit (61) delays by 1/2 bit, and the delayed signal (61a) and the output timing signal (22a) of the second system timing signal generator (2) in the non-operational state Counting means (2) in the timing signal generator (2) of the second system
The count value of 2) is returned to the initial value, and the timing signal generator (1) of the first system in the operating state is switched to the timing signal generator (2) of the second system in the non-operating state when a failure occurs. .

The counting circuit (21) (or (22)) is a delay signal (62a) (or (61) from another timing signal generator (2) (or (1)).
a)) and the output timing signal (21a) (or (22a)) output by the counting circuit (21) (or (22)) itself by the AND gate (41) (or (42)). The signal thus obtained is input as a reset signal to cancel the count value and return it to the initial value.

The delay signal (62a) (or (61a)) input to the AND gate (41) (or (42)) activates the timing signal generators (1), (2) of the first system or the second system. Therefore, the logical product condition with the gate signal (51a) (or (51b)) of the first system or the second system that is input from the outside is obtained by the OR gate (51) (or (52)), and this condition is It is output when satisfied.

Next, the operation of the system of this embodiment based on the above configuration will be described. Output timing signal of the first system (or second system) (2
1a) (or (22a)) is the first (or second) synchronization clock (11a) (or
(12a)) is the counting circuit (21) (or (22)) and is set to 1 every 4 clocks.
The following description will be given assuming that the signal is a pulse-generating signal.
The phase-locked loop (11) is the first synchronized with the input clock (10a).
The system synchronous clock (11a) is generated, and the counting circuit (21) counts the first system synchronous clock (11a) as shown in FIG.
The count value is 3 (QA = "H", QB = "H", QC =
When it becomes "L", QD "L"), the NAND gate (31) outputs "L", and the counting circuit (2
When the synchronous clock rises after being input to the RESET terminal of 1), the count value becomes 0 (QA = "L", QB = "L", QC =
"L" and QD = "L") are reset, and counting is started again. Since the output timing signal (21a) of the first system is the output of the NAND gate (31), the synchronous clock (11a) becomes a signal for generating one pulse every four clocks.

The above operation is performed by the phase synchronization circuit (12), the counting circuit (22), the NAND gate (32) in the timing signal generator (2) of the second system,
The same applies to the AND gate (42).

The first system timing signal generator (1) is in the operating state, the second
When the system timing signal generator (2) is in the non-operational state, the first system gate signal (51a) becomes "H", and the OR gate
(51) is closed, the second system gate signal (52a) becomes "L", and the OR gate (52) is opened. Therefore, as shown in FIG. 3, the delayed signal (61a) obtained by delaying the first system timing signal (21a) by 1/2 bit is the OR gate (52) and the AND gate (42).
Is input to the RESET terminal of the second counting circuit (22) and reset, and the count value of the first counting circuit (21) and the count value of the second counting circuit (22) become equal. The next output timing signal is the output timing signal of the first system (21a)
The output timing signal (22a) of the second system coincides with.

When the first system timing signal generator (1) is in the non-operational state and the second system timing signal generator (2) is in the operational state, the first system gate signal (51a) becomes "L", The OR gate (51) opens, the second scene gate signal (52a) becomes “H”, the OR gate (52) closes, and the second system output timing signal (22a) receives the first signal through the same process as described above.
The system output timing signals (21a) match.

FIG. 3 shows the first with respect to the input clock (10a) shown in FIG.
It is a pulse waveform timing diagram when the phase synchronization circuit (11) of the system and the phase synchronization circuit (12) of the second system are phase-synchronized with the same phase and output the synchronization clock of the same phase. The phase of the first system synchronization clock (11a) and the second system synchronization clock (12a) differ due to variations in the elements in the phase synchronization circuit (11) (or (12)).

The 1 / 2-bit delay circuit (61) (or (62)) is provided with the timing signal of the first system when the first system synchronous clock (11a) and the second system synchronous clock (12a) have a phase difference. This has the effect of keeping the phase difference between the two-system timing signal and the phase difference of the synchronous clock. That is, as shown in FIG. 4, the synchronous clock (12a) of the second system is 1/4 of the synchronous clock (11a) of the first system.
If there is a 1/2 delay circuit when the phase is delayed, the timing at which the output timing signal (22a) of the second system returns to the initial value is 1 more than the timing at which the counting circuit (21) of the first system returns to the initial value. Only 4 bits will be delayed. Therefore, the phase difference of the output timing signal (21a) (or (22a)) can be suppressed within the range of the phase difference of the synchronous clock (11a) (or (12a)). When there is a 1 / 2-bit delay circuit (61) (or (62)), the synchronization clock is added by a 1 / 2-bit delayed timing signal when there is no phase difference in the synchronization clock as shown in FIG. The rising counter circuit (11) (or (12)) returns to the initial value, so the synchronous clocks (11a), (1
Even if there is a phase difference in 2a), the phase difference of the output timing signal can be made equal to the phase difference of the synchronous clock, and it is possible to minimize the malfunction due to the phase difference that occurs when switching between operating and non-operating. it can.

Fig. 5 shows the timing signal generator (1) of the 1st system is in the operating state and the timing of the 2nd system without inputting the 1/2 bit delay circuit and inputting the 1st system timing signal directly to the OR gate (52). When the signal generator (2) is in the non-operational state, the second system synchronous clock (12a) is more than the first system synchronous clock (11a).
It is a pulse waveform timing chart in the case of a 1/4 phase delay, and the timing of returning to the initial value of the counting circuit (22) of the second system is more than the timing of returning to the initial value of the counting circuit (21) of the first system.
It will be advanced by 3/4 bit. The output timing signal (22a) of the second system leads the output timing signal (21a) of the first system by 3/4 bit.

The steady phase error between the synchronous clocks (11a) and (12a) of the first system and the second system will be described in more detail.
Generally, a phase-locked clock generates a synchronous clock that is delayed from the input clock by a steady phase error φ (that is, the input clock usually contains jitter etc. and is not stable, so it cannot be used as a clock for driving the device). .

FIG. 6 (A) shows the relationship between the input clock and the first-system synchronous clock and the second-system synchronous clock (the stationary phase errors of the first-system and second-system synchronous clocks are φ ₁ and φ ₂ ). The steady phase errors φ ₁ and φ ₂ cannot be made equal at all, but can be made almost equal by adjusting the characteristics of the phase synchronization circuit because the phase synchronization circuit is composed of an analog circuit.

In this way, when the steady phase errors φ ₁ and φ ₂ are adjusted to be almost equal (when the first system synchronous clock and the second system synchronous clock have substantially the same phase), the 1/2 bit delay circuits (61), (62) )
When the output timing signal is exchanged without passing through the output timing signal of the second system when the synchronization clock of the second system is slightly behind the synchronization clock of the first system as shown in Fig. 6 (A). Will be advanced by about 1 bit. That is, the counting circuits (21), (22) in this embodiment
In the above configuration, the output timing signal of the second system is "L" from the position where the output timing signal of the second system is advanced by 1 bit from the synchronous clock of the second system which rises at the "L" level of the output timing signal of the first system.
It is caused by the fact that it has become odorous. Therefore, the timing signal will be displaced by more than the phase difference of the synchronization clock.

Next, if the 1 / 2-bit delay circuits (21) and (22) are used, the output timing signal of the second system will always have a phase almost equal to the output timing signal of the first system as shown in FIG. 6 (B). Will occur. This substantially equal phase is equal to the phase difference of the synchronous clock and is φ ₁ -φ ₂ .

Next, the value of 1/2 bit of the 1/2 bit delay circuits (21) and (22) is 1 / φ when the steady error is φ ₁ = φ ₂ as shown in Fig. 6 (C). Delay signal with 2-bit delay (61
It is the value determined because it is the center of a) and (62a), and the output timing signal can be captured with the most margin before and after.

Also, if the steady-state phase error is different (φ ₁ ≠ φ _2), what phi _1, phi ₂ is an even half-bit delayed signal (61
It can be captured at a position shifted by a phase difference of φ ₁ −φ ₂ from the center of a) and (62a) (see Fig. 6 (B)). Also,
The timing signal generated by the second system is generated at a position deviated from the phase of the timing signal of the first system by φ ₁ -φ ₂ (that is, the phase difference of the synchronous clock).

As described above, the effect of the 1/2 bit delay circuits (61) and (62) is that when φ ₁ = φ ₂ , the phase difference of the output timing signals disappears as shown in FIG. 6 (C). Even when φ ₁ ≠ φ ₂ , the phase difference of the output timing signal is the stationary phase error φ ₁ −
Can be reduced to φ ₂ .

In the above embodiment, the timing signal generator (1) of the first system is in the operating state, and the timing signal generator of the second system is
Although (2) is described as the non-operational state, the same operation is performed even when the operation and non-operation are reversed.

In the above embodiment, the timing signal is set to 1 every 4 clocks.
Although the pulse is described as a pulse, it goes without saying that the present invention can be applied to other types of timing signals.

〔The invention's effect〕

As described above, according to the present invention, the counting of the counting circuit that generates the timing signal of the timing signal generator in the non-operating state by delaying the timing signal of the timing signal generator in the operating state by 1/2 bit is initialized. Since the configuration is returned to the value, the phase shift between the output timing signal in the operating state and the output timing signal in the non-operating state is output by the phase synchronization circuit in each of the operating and non-operating timing signal generators. The phase difference in the synchronous clock can be suppressed, and the displacement of the phase that occurs when the operating / non-operating timing signal generator is switched to the duplex mode can be minimized.

[Brief description of drawings]

FIG. 1 is a block diagram for explaining a duplexing switching system of a timing signal generator according to an embodiment of the present invention, and FIGS. 2, 3, and 4 are diagrams according to an embodiment shown in FIG. The timing diagram when the duplex switching is performed, FIG. 5 is the timing diagram when the 1/2 bit delay is not performed, and FIGS. 6 (A), (B), and (C) describe this embodiment in more detail. FIG. 7 is a block diagram for explaining a dual switching system of a conventional timing signal generator,
FIG. 8 is a timing chart when the duplex switching is performed by the conventional duplex switching system. In the figure, (1) is the timing signal generator of the 1st system, (2) is the timing signal generator of the 2nd system, (7) is the supervisory control device, (8) is the switch, (11), (12) Is a phase lock circuit, (21), (22) is a counting circuit, (31), (32) is a NAND gate, (41), (42) is an AND gate, (51), (52) is an OR gate, and (61) , (62) is a 1/2 bit delay circuit. The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A phase synchronization means for generating a stable synchronization clock whose phase is synchronized with an input clock input from the outside, and a counting for counting the synchronization clock of the phase synchronization means to generate a timing signal at a predetermined interval. In the duplexing switching system of the timing signal generating device, wherein the timing signal generating device having the means is duplicated and the timing signal generating device is switched to another timing signal generating device when a failure occurs in the timing signal generating device. Input the same input clock, delay the timing signal of one timing signal generator in the operating state by 1/2 bit, and use the delay signal and the timing signal of another timing signal generating device in the non-operating state. The count value of the counting means in the other timing signal generator is returned to the initial value,
A duplex switching system for a timing signal generating device, characterized in that one timing signal generating device in the operating state is switched to another timing signal generating device in the non-operating state.