JPS63232652A - Frame synchronization protection circuit - Google Patents

Abstract

PURPOSE:To attain backward protection by a count of counters of the number of stages equal to the backward protection stage number by inputting a detection output of a frame pattern detection circuit to a reset terminal not only to a set terminal of an SR flip-flop of an alarm control circuit. CONSTITUTION:If a frame pattern detection circuit 1 does not detect a frame pattern synchronously with a 1st decoding signal H1 but detects at the next point of time at the point of time of the first frame pattern detection after the occurrence of alarm, an output D of an alarm control circuit 3 goes to 1 and an output C of the reset signal generator resets it to zero. During this time, the clock CLK of the frame counter 7 is not inhibited and 0 is fetched in the alarm counter 4. In detecting the frame pattern by the pattern detection circuit 1 in synchronism with 0 of the 1st decoding signal H1 at the point of time of the detection of next pattern, the alarm counter 4 fetches and counts 1 being the conversion of output D to apply normal operation.

Description

[Detailed Description of the Invention] [Summary] This is an improvement of a frame synchronization protection circuit for digital multiplexed signals, in which the detection output of a frame pattern detection circuit is connected to an SR flip-flop for input control of an alarm counter for detecting synchronization protection. Not only the set side S but also the reset side R
This has been improved so that the frame pattern detection circuit can guarantee the correct number of stages of synchronization protection detection even if the frame pattern detection circuit detects a frame pattern from the input signal at any point in an alarm condition.

[Industrial application field]

The present invention relates to a frame synchronization protection circuit for digital multiplexed signals, and in particular, once synchronization is established, it is not determined that synchronization is out of synchronization due to an instantaneous change in the synchronization pulse due to a code error in the transmission path (forward protection). This invention relates to an improvement in a frame synchronization protection circuit that prevents erroneous synchronization (backward protection) by determining that synchronization is achieved even when synchronization is not achieved.

In time-division multiplexing of digital signals, the signal pulses of each channel to be multiplexed are arranged synchronously in order, and a synchronization pulse (frame synchronization pulse F) is added to each cycle, which is called a frame and transmitted. On the other hand, the sign of the frame synchronization pulse F is changed in a predetermined pattern every frame and sent out.

On the receiving side, the pulse pattern in the received pulses is checked for each frame, the target frame is detected, and the time slot position of each channel in that frame is identified. This is called frame synchronization.

As a synchronization protection circuit for frame synchronization, it guarantees normal synchronization protection detection of a predetermined number of stages even when a predetermined frame pattern is detected at any point in the input signal when frame synchronization is not established (alarm state). It is hoped that

[Conventional technology]

FIG. 4 is a block diagram showing an example of the configuration of a conventional frame synchronization protection circuit.

The input data is first input to the frame pattern detection circuit 1, which compares the pattern of the frame synchronization pulse F for each frame with a predetermined pattern bit by bit, and outputs "1" when the pattern matches the predetermined pattern. outputs “0”.

The output A of the frame pattern detection circuit 1 is supplied to the OR gate of the non-number output circuit 2 and the first output of the frame counter 7, which will be described later.
It is ORed with the decoded pulse (1), and its output B is input to the set terminal S of the SR flip-flop of the alarm control circuit 3, and the output is outputted from the normal output terminal Q.

The output of the alarm control circuit 3 is input to the alarm counter 4, and the alarm counter 4 detects the same sign of "0" or "1" of the output A of the frame pattern detection circuit 1 three times in a row. Outputs alarm ALM.

The alarm counter 4 counts the succession of the same sign of the input signal using three stages of low flip-flops 41, 42, and 43, and compares the Q outputs of each stage at a Nantes gate 44 to detect forward protection. , D free knob flop 41.
42 Q outputs are compared by a Nant gate 45 to detect backward protection. The detection output of Nant Gate 44.45 is S
Alarm ALM collected by R flip-flop 46
is output as

The alarm counter 4 indicates that the frame pattern 1 circuit 1 cannot detect a predetermined frame pattern, and the output A of the frame pattern detection circuit 1 and the output port 3 of the alarm control circuit 3 are
When the alarm is “0” twice in a row, the alarm ALM “1”
When a predetermined frame pattern is detected and the output is "1" three times in a row, the alarm ALM is output as "0".

The former is called when an alarm occurs, and the latter is called when an alarm is released.

The output ALM of the alarm counter 4 is the inconsistency detection circuit 2.
With the inverted signal of output B (by inverter 52) of
It is input to the inhibit pulse generator 5, and its AND gate 51 performs a logical product, and the output F is transmitted to the input clock CL of the frame counter 7, which will be described later, as an inhibit pulse that passes/blocks the frame via an OR gate 61. Controls the operation of the counter 7.

The output F of the AND gate 51 of the inhibit pulse generator 5 outputs "O" when an alarm occurs, outputs "1" when the alarm is released, and passes the input clock CLK of the frame counter 7 by the OR gate 61. Cut off.

The OR gate 61 interrupts the input clock CLK of the frame counter 7 to stop the counting operation when the output pulse F-/J of the AND gate 51 of the inhibit pulse generator 5 is <"D", and outputs the output pulse of the AND gate 51. is “0”
”, the input clock CLK of the frame counter 7 is passed to perform counting operation.

The count result of the frame counter 7 is decoded by a decoder 8, and the decoder 8 outputs a first decoded pulse H1' and a second decoded pulse H2. The first decoded pulse H1 of the decoder 8 is
The OR gate of the mismatch detection circuit 2 and the OR gate 62 of the input clock CLK for comparison with the frame pattern detection signal
The second decoded pulse H2 following the first decoded pulse II1 is inputted to the reset terminal R of the SR flip-flop 3 of the alarm control circuit 3 and sent from the mismatch detection circuit 2 to the set terminal. Reset the data input to S.

The first decoded pulse H1 of the decoder 8 is transmitted to the mismatch detection circuit 2.
In addition to OR-controlling the output angle of the frame pattern detection circuit 1 by inputting the input clock to the input clock CLK, the OR gate 62 of the input clock CLK performs OR-control of the input clock CLK of the alarm counter 4 to control the output angle of the three-stage flip-flop 41 of the alarm counter 4. .42.Controls the counting operation of 43.

Since the alarm counter 4 counts and detects three consecutive input codes using three stages of flip-flops 41, 42, and 43, the number of synchronization protection stages handled by it is three stages at the front and three stages at the rear.

[Problem that the invention seeks to solve]

The operation and problems of the conventional frame synchronization protection circuit shown in FIG. 4 will be explained using the time charts shown in FIGS. 5 and 6.

5 and 6, ■ is the signal waveform to the output of the frame pattern detection circuit 1, and ■ is the first decoding pulse H1 of the decoder 8.
, ■ is the output B of the mismatch detection circuit 2, ■ is the second decoded pulse H2 of the decoder 8, and ■ is the output D1 of the alarm control circuit 3.
2 is the input clock CLK of the alarm counter 4, 2 is the output ALM of the alarm counter 4, and 2 is the waveform of the output F of the inhibit signal generator 5.

In FIG. 6, when the frame pattern detection circuit 1 cannot detect the frame synchronization pattern of the input signal and the alarm counter 4 outputs an alarm ALM 1 ″, the first frame pattern in condition g (1) is detected. If the frame pattern detection circuit 1 does not detect a predetermined frame pattern at the scheduled time, that is, the A output ■ is “0”, the B output ■ is “0”, the D output ■ is “1”, and the ALM ■ is “0”. is “1”, the F output ■ is “1”, and the input clock of the frame counter 7 is the OR gate 6.
1 inhibits the counting operation and waits for frame pattern detection.

When the pattern detector 1 detects a predetermined frame pattern in state (2) of FIG. 6 at the next frame pattern detection time, that is, the first decoded signal H1 is "0" and the D output is "1".
”, when A output ■ changes from “O” to “1”,
B output ■ becomes "1". However, the D output ■ remains at "1" until the pulse of the second decoded signal H2 is generated.

At this time, the F output ■ changes from "1" to "0", and the input clock CLK of the alarm counter 4 of ■ is blocked (X mark).
is released, and “1” of D output ■ becomes alarm counter 4.
be taken in. Therefore, even if the frame pattern detection pulse A and the first decoded signal old match three times in a row, the alarm counter 4 will only capture 0'' twice.
Three stages of rear protection are possible using the mouth output of only one stage.

However, as shown in FIG. If a pattern is detected, ■ Output A is 61 by one bit only.
", and the first decoded signal H1 of (2) changes from "1'" to 0, but the (2) output B remains at "1" as shown in the figure, and the output of (2) also remains at "0". During this time, alarm counter 4
Since the input clock CLK cannot be inhibited,
■The output of 0'' is taken into the alarm counter 4,
“1” is not input.

However, in the circuit shown in FIG. 4, backward protection is performed with the outputs of only two stages of D flip-flops 41 and 42 on the premise that "0" will not be captured in the first frame pulse detection after an alarm. In the case of Figure 5, “0
The problem arises that the three-stage rear protection that detects three consecutive "" is reduced by one stage to two stages, and the normal rear protection operation is not performed.

[Means for solving problems]

The problem in which the number of backward protection stages decreases by one is that the reset signal is generated so that the detection output A of the frame pattern detection circuit source is input not only to the set terminal S of the SR flip-flop of the alarm control circuit 3 but also to the reset terminal R. This problem is solved by the configuration of the present invention in which the device 8 is provided.

In the principle block diagram of Fig. 1, ① is a frame pattern detection circuit, 2 is a mismatch detector, 3 is a
is an SR flip-flop of the alarm control circuit, 4 is an alarm counter for synchronization protection, 5 is an inhibit pulse generator, 61 is a clock gate for frame counter, 62
7 is a clock gate for an alarm counter, 7 is a frame counter, and 8 is a reset signal generator path.

[Effect]

The frame pattern detection circuit 1 compares the frame synchronization pulse of the input data with a predetermined pattern, and outputs an output A as "1" when it is detected, for example, and when it is not detected.
Output A as “O”.

The mismatch detection circuit 2 compares the output of the frame pattern detection circuit 1 with the first decoded signal H1 of the frame counter 7, and outputs an output B which becomes "1" only when there is a mismatch.

The alarm control circuit 3 is, for example, an SR flip-flop, which inputs the output B of the discrepancy detector 2 to its set terminal S and outputs normal code data from its Q terminal using a clock. 8's output C to its reset terminal R.

The reset signal generator 8 newly installed in the present invention is a circuit that performs a logical product of an inverted signal obtained by inverting the output A of the frame pattern detection circuit 1 and a second decoded pulse H2 of the frame carantuff, and outputs an output C. , the output C of the reset signal generator 8 is input to the reset terminal R of the SR flip-flop of the alarm control circuit 3.

The SR flip-flop of the alarm control circuit 3 inputs the frame pattern by inputting the output B of the mismatch detection circuit 2 to the set terminal S and simultaneously inputting the output C of the reset signal generator 8 to its reset terminal R. The normal operation of an alarm counter 4 is guaranteed even when the output A of a detection circuit 1 is detected at the following special timing.

The alarm counter 4 detects a predetermined number of consecutive outputs of the same code from the alarm control circuit 3 and generates and cancels the alarm ALM.

The alarm output ALM of the alarm counter 4 is input to the inhibit pulse generator 5 together with the output B of the discrepancy detection circuit 2, and outputs an output pulse F when a discrepancy is detected when an alarm occurs.

The output pulse F of the inhibit pulse generator 5 is input to the first clock gate 61 and blocks the input clock CLK of the frame counter 7.

The frame counter 7 inputs the first decoded signal H1 to the second clock gate 62, and the frame counter 7 inputs the first decoded signal H1 to the second clock gate 62.
The input clock CLK is passed to the input clock CLK.

In the frame synchronization protection circuit of the present invention, the output A of the frame pattern detection circuit 1 is input to the alarm control circuit 3 via the mismatch detection circuit 2, and is not only sent when a mismatch is detected, but also reset by a detection pulse to the output. Since the alarm control circuit 3 is reset via the signal generator 8,
When a frame pattern is detected, it is always captured in the alarm counter 4, so there is no need to perform rear protection using the output of the D flip-flop, which is one stage less than the number of rear protection stages, as in the circuit shown in Figure 4. Rearward protection can be performed using the count value of the counter whose number of stages is equal to the number of stages. Therefore, even in the case as shown in FIG. 5, it is possible to perform rearward protection of the correct number of stages.

〔Example〕

FIG. 2 is a block diagram showing an example of the configuration of a frame synchronization protection circuit according to an embodiment of the present invention, and FIG. 3 is a diagram for explaining its operation.

In FIG. 2, the frame pattern detection circuit 1 detects, for example, one frame of 193-bit PCM-next group 1°544
This is a pattern detection circuit that compares the frame-by-frame repetition pattern of the frame synchronization pulse F at the end of the frame of Mb/s input data with a predetermined pattern, and outputs "1" when a match is made, and "0" when there is a mismatch. .

The mismatch detection circuit 2 is an OR gate 21 that logically ORs the first decoded pulse H1 of the decoder 72 of the frame counter 7 with the output of the frame pattern detection circuit 1, and outputs an output B.

The alarm control circuit 3 is a one-stage SR flip-flop 3.
1, the output B of the mismatch detection circuit 2 is input to the set terminal S, and the reset signal generator 8 is input to the reset terminal R.
It inputs the output C of , and outputs the output from the regular output terminal Q in response to the clock CLK.

The alarm counter 4 takes the output of the alarm control circuit 3 as "1" as a mismatch and "0" as a match.

a three-stage D flip-flop 41.42.43 that counts the input; a forward protection Nant gate 44 that compares the normal output Q of each stage of the flip-flop 41.42.43;
A rear protection Nands gate 45 for comparing the complementary outputs i of the flip-flops 41, 42, and 43, and both Nands gates)
It consists of an SR flip-flop 46 which inputs the outputs of 44 and 45 to the set terminal S and reset terminal R, respectively, and outputs the normal output Q as an alarm ALM, forming a frame synchronization protection circuit with three stages in the front and three stages in the rear. .

Frame pattern detection circuit 1 cannot detect a predetermined frame pattern, and its output A becomes “0” for 3 consecutive frames.
When the output is output, the output of the alarm control circuit 3 becomes "0" three times in a row, and the alarm counter 4 that counts the output is the alarm AI.

Output the gate as “1”.

The frame pattern detection circuit 1 can detect a predetermined frame pattern, and its output A is "1" for three consecutive frames e.
”, the output of the alarm control circuit 3 becomes “1” three times in a row, and the alarm counter 4 outputs the alarm ALM as “0”. The former is called the alarm generation time, and the latter is called the alarm. This is called the time of release.

The output ALM of the alarm counter 4 is the inconsistency detection circuit 2.
is input to the AND gate 51 of the inhibit pulse generator 5 together with the inverted signal of the output B (by the inverter 52), and when the alarm occurs, the AND gate 51 of the inhibit pulse generator 5 outputs "0", and when the alarm is released, Outputs “1”.

The output pulse F of the AND gate 51 of the inhibit pulse generator 5 is input to an OR gate 61 that controls on/off the input of the clock CLK of the frame counter 7, and controls the counting operation of the counter 71 of the frame counter 7. That is, when the output pulse F of the inhibit pulse generator 5 is input to the OR gate 61 as 0'' and the clock CLK is input, the output becomes ``1'' and the frame counter 7
The counter 71 performs counting. When the output pulse F of the inhibit pulse generator 5 is input as 1'', even if chlorella CLK is input, the output of the OR gate 61 is @Q I
I, and the counter 71 stops counting.

The count result of the counter 71 of the frame counter 7 is decoded by a decoder 72, and outputs a first decoded pulse H1 and a second decoded pulse H2. First decoded pulse H1 of decoder 72
is input to the input side of the OR gate 21 of the mismatch detection circuit 2 and the OR gate 62 of the input clock CLK of the alarm counter 4, and the second decoded pulse H2 following the first decoded pulse H1 of the decoder 72 is inputted to the AND of the reset signal generator 8. The signal is input to gate 82 .

The first decoded pulse H1 of the decoder 72 is logically summed with the output A of the frame pattern detection circuit 1 in the OR gate 21 of the mismatch detection circuit 2, and the output B is inputted to the set terminal S of the SR flip-flop of the alarm control circuit 3. do.

The first decoded pulse H1 of the decoder 72 is also applied to the OR gate 6
In step 2, a logical OR is performed with the input clock CLK, and the output thereof is used to cause the three stages of D flip-flops 41, 42, and 43 of the alarm counter 4 to perform counting operations.

The second decoded pulse H2 of the decoder 72 is input to the AND gate 82 of the reset signal generator 8, and is ANDed with the inverted signal to the output of the frame pattern detection circuit l.

The reset signal generator 8 is connected to the frame pattern detection circuit 1
an inverter 81 that inverts the output A of the inverter 81;
and the second decoded pulse 112 of the decoder 72, and the output C of the AND gate 82 outputs an inverted sign to the output of the frame pattern detection circuit 1.

FIG. 3 is a time chart for explaining the operation of the frame synchronization protection circuit of this embodiment, and FIG. 3 is a time chart when frame synchronization is restored through a hunting process after an alarm occurs. FIG. 3B is a time chart when synchronization is restored without entering the hunting process.

In Fig. 3A, the alarm output ALM of ■ is “1”.
Immediately after the so-called alarm is generated, the frame pattern detection circuit 1 detects the first frame pattern detection scheduled time (1
), if no frame pattern is detected, the output A of the frame pattern detection circuit 1 in (■) becomes 0", and the first decoding pulse H1 in (2) becomes "0" by 1 bit, so the inconsistency detection circuit 2 in (2) The output B also becomes 1 bit "O", and the output of the alarm control circuit 3 (2) becomes 1 bit "L".

However, the "0" to the output of (2) is logically ANDed with the second decoded pulse 112 in the reset signal generator 8, and the reset signal generator 8 outputs the inverted sign "1" to (1).
Output as output C. Since this (2) output C is input to the reset terminal R of the SR flip-flop of the alarm control circuit 3, the (2) output returns to "O", and the alarm counter 4 receives and counts this (2) output (0). ■When output meter 1 returns from 1” to “0”, ■Output B also °
Return to 0''.

However, after the alarm occurs, even if ■output 1!1 becomes "O" at the scheduled time to detect the first frame pattern, ■if output does not become "1", then ■output B becomes 0''. As a result, (1) the output meter changes from "O" to "1", the input clock to the counter is inhibited, and a hunting state is entered.

Next, when a frame pattern is detected at the next frame pattern detection time point (2), ■ Output A becomes "l" by 1 bit.
” is output. The Hl of ■ is still 0'' at this point, but the ■ output B changes from “0” to l ”, and the ■ output becomes 1.
However, the output C of the reset signal generator 8 changes from "1" to "0" when the output A is detected, as shown in (■), but immediately returns to "1". , and one bit changes from "1" to "0" and becomes the inverted sign of the output returning to "1".Therefore, (2) output is returned from 1" to "0" by (2) output C. At this time, the ■output meter is “
1" changes to "0", the inhibition of the manual clock CLK (X mark) is released, and the alarm counter 4 takes in the "1" of the output (■) and performs normal operation.

FIG. 3B is a time chart when the frame synchronization state is returned without entering the hunting state after an alarm occurs.

After the alarm occurs, the first frame pattern is detected (1
), the frame pattern detection circuit 1 does not detect the frame pattern in synchronization with the first decoded signal H1, and the frame pattern detection circuit 1 detects the frame pattern at the next point in time (
When detecting in step 2), at the time of detection (1), ■output A is “
0", ■ Output 111 becomes "0" for only 1 bit, ■ Output B of mismatch detection circuit 2 becomes "0" for only 1 bit, ■ Output of alarm control circuit 3 becomes "1", but ■ Reset signal is generated. The output C of the device resets this to 11011
Make it. During this time, the frame counter 7 clock CLK
is inhibited and the alarm counter 4 shows “0”.
” will be imported.

At the next pattern detection time point (2), when the pattern detection circuit 1 detects a frame pattern in synchronization with "0" of the first decoded signal H1, ■ Output A becomes "1" and ■ Output total 1 becomes "0", so ① output B becomes ``1'' and ② output B becomes ``O''. During this time, the inhibit signal generator 5
Since the output F of is "0" and the clock input of (2) is not inhibited, the alarm counter 4 takes in the converted "1" from the (2) output and performs normal operation.

〔Effect of the invention〕

As explained above, according to the present invention, even if the frame pattern detection circuit detects a frame pattern from input data at any timing immediately after frame synchronization is not achieved and an alarm occurs, the frame synchronization protection circuit detects a predetermined number of stages. The effect of normal protective operation can be obtained without any reduction.

[Brief explanation of drawings]

FIG. 1 is a principle block diagram showing the configuration of a frame synchronization protection circuit according to the present invention, FIG. 2 is a block diagram showing the configuration of a frame synchronization protection circuit according to an embodiment of the present invention, and FIG. A time chart for explaining the operation of the frame synchronization protection circuit, FIG. 4 is a block diagram of the conventional frame synchronization protection circuit, and FIGS. 5 and 6 are for explaining the operation of the conventional frame synchronization protection circuit. This is a time chart. 1 and 2, 1 is a frame pattern detection path, 2 is a mismatch detection circuit and an OR gate, 3 is an SR flip-flop of an alarm control circuit, 4 is an alarm counter, 5 is an inhibit signal generator, 61.62 is a clock gate and is an OR gate, 7 is a frame counter, 8 is a reset signal generator, 81 is an inverter, and 82 is an AND gate.

Claims (1)

[Claims] A frame pattern detection circuit that detects a frame synchronization pulse pattern from a received signal and outputs a detection signal (A)
1), clock counting is started simultaneously with the detection of the frame pattern detection circuit (1), and when the first predetermined value is reached, the first decoded signal (
H1) becomes a second decoded signal (H2) when it reaches a second predetermined value.
a frame counter (7) that outputs the frame pattern detection circuit (1), and a mismatch detection circuit (2) that detects a mismatch between the detection signal (A) of the frame pattern detection circuit (1) and the first decoded signal (H1) of the frame counter (7). and an alarm control circuit (3) that holds the detection signal (B) of the mismatch detection circuit (2) and is reset by the second decoded signal (H2), and an output (D) of the alarm control circuit (3). an alarm counter (4) that detects the consecutive number of the same code and outputs an alarm (ALM); and an alarm (ALM) of the alarm counter (4) that indicates the occurrence of an alarm, An inhibit pulse generator (5) generates an inhibit pulse (F) while the detection signal (B) indicates mismatch detection.
); and a first clock gate (61) that cuts off the input clock (CLK) to the frame counter (7) while the inhibit pulse (F) from the inhibit pulse generator (5) is being generated; a frame synchronization protection circuit comprising a second clock gate (62) for passing an input clock (CLK) to the alarm counter (4) while the first decoded signal (H1) of the frame counter (7) is being output; , the pulse of the detection signal (A) of the frame pattern detection circuit (1) and the second decoded signal (H2) of the frame counter (7)
) is provided, and the alarm control circuit (3) is reset using the output pulse C of the reset signal generator (8). Features a frame synchronization protection circuit.