SU1193831A1 - Device for quality control of digital communication channel - Google Patents

Description

The invention relates to electrical engineering and can be used for

quality control of digital communication channels in information transmission systems.

The purpose of the invention is to increase the reliability due to auto-control.

The drawing shows a structural electrical circuit of the proposed device.

The device for quality control of a digital communication channel contains a multiplexer 1, a comparator 2, a 3 error counter, a memory block 4, the first AND-5 element 5, a clock 6, a gate pulse shaper 7, a trigger 8, a registration block 9, a second IS-10 element.

• The device works as follows.

The operation of the device is based on the analysis of a part of the sync signal transmitted in the “0” channel of the digital PCM-30 system. Analyzed the sync signal of their digital channel is fed to the information input of the multiplexer 1, which is controlled by pulses coming from the driver 7 gating pulses. In the absence of pulses at the output of the shaper pulse shaper 7 and the presence of a signal at the fourth input of the multiplexer Ί information from the channel passes to the output of multiplexer 1, and the passing of the test information from the chroniser 6 is prohibited. With the appearance of gating pulses of the autocontrol from the shaper 7, the test information from the chroniser 6 during the autocontrol passes to the output of multiplexer 1, and the passage of information from the channel is prohibited. The signal from the output of multiplexer 1 is fed to the second input of the comparator 2, made in the form of an adder modulo two, the first input of which receives the reference sequence from the chroniser 6. The comparator compares two information. If the received information from their digital channel is identical to the reference information (i.e. there is no distortion in the sync pattern), then at the output of comparator 2 we have a constant state "0".

If under the action of noise and interference, the digital stream coming from the channel will be distorted, it is in the same style.

40

193831 ¹

Penalties will affect the sync sequence, go at the output of the comparator

2 will be state '1' *. Information

from the output of comparator 2 comes

5 to the first input of the 3 error counter, which records errors. The result of the number of errors from the output of the counter 3 errors goes to memory block 4, which is connected inverse

10 connection with the counter 3, and also connected to the first element IS-NOT 5. Before counting errors, the previous state of this channel of the digital path fits into the counter 3 errors, then the counting mode is set, and if an error occurs, then the counter 3 increases. mistakes. The new state of the 3 error counter fits into memory block 4. This process

20 occurs until a 3 error counter is filled, which corresponds to an error rate in the digital path equal to 10 ^_3 , which is considered as a threshold.

25 If the counter is filled with 3 errors, it is blocked through its feedback and subsequent errors are not miscalculated.

This error counting operation allows you to control the quality of information for several digital systems using a single device. The number corresponding to the number of errors recorded in the line arrives at the first input of the first element!

AND-NOT 5. If this number "exceeds a certain threshold in the first element AND-NOT 5, the signal" Emergency "is generated, which arrives at the output of the device in the presence of a signal at the enabling input. Similarly, the first element AND — NOT 5 receives a number characterizing the number of accumulated errors in the communication line.

4 $ In order not to repeatedly transmit the same signal "Accident" when the permit signal arrives simultaneously with the signal at the device output

5 ° is fed to the first input of block 9 of registration, which blocks the first element AND-NOT 5, thereby prohibiting the repeated, transmission of the signal "Accident". Duration of observation time

55 behind the digital path to determine

the error rate in it should

be about 4 s. When offensive

new four-second cycle on

3

1193831

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The first 1.25 μs device with the help of the trigger 8 is transferred to the state of automatic control. This is achieved as follows.

The signal from the first output of the trigger 8 goes to the second input of the 3 error counter, I zeroes it, the zero state of the 3 error counter is written to memory block 4, and from its output it goes to the first AND-NE element 5 and further to the registration block. The second output of the flip-flop 8 includes a form-gel ст 7 gating pulses. The output signal from the driver of the 7 gating pulses goes to the multiplexer 1 and blocks the input to its inputs of the information signal from the digital channel and the gating pulse of the digital path control, while simultaneously allowing the test information flow from the chroniser 6 output used in the autocontrol. The structure of the information flow used in the autocontrol is such that if the device is working properly for the first half of the autocontrol time, the 3 error counter gains such a number of errors that it would have typed if it were connected to the digital path when its accuracy is 1SG ³ , during the second half of the time allotted for the autocontrol, the counter of 3 errors, which is previously zeroed, does not receive impulses and the information in it does not accumulate. As a result, with

5, the second element of the NES-10 does not record the correct operation of the device; the state of the counter 3 is either 1111 (1st half of the period) or 0000 (2nd half of the period). The number of errors accumulated

10 in the autocontrol mode, enters the second AND-NOT-THEM element, which functions similarly to the first AND-NOT 5 element.

Information about the accident is received at the corresponding output of the device when a read permission is received at the authorizing input of the second element AND-NOT 10. Simultaneously with

2 On arrival at the output of the device, the signal "Autocontrol" is fed to the second input of the registration unit 9, which is connected to the second input of the second output by its second output

25 elements AND-NOT 10 and blocks the latter, thereby prohibiting the re-transmission of the signal "Accident". Simultaneously, the signal "Failure" triggers the trigger 8, the second output of which including The shaper ₃₀ chaet 7 strobe pulses that sets the device in continuous measuring mode and switches · first and second AND-NO elements 5 and 10.

Claims (1)

A QUALITY CONTROL DEVICE OF A DIGITAL COMMUNICATION CHANNEL, containing a registration unit, a series-connected chronizer and a Comparator, an error counter, differently due to the fact that, in order to increase the reliability due to the auto-control, A memory block, first and second NAND elements and sequentially connected trigger, a gating pulse shaper and a multiplexer, the output of which is connected to the second input of the comparator whose output is connected to the first input of the error counter, the first and second outputs and the second input of which are connected corresponding to the input of the memory block, with the second input of the error counter and the second trigger output, the information input of which is combined with the first input of the registration unit and connected to the output of the second NAND element, the first and the second information inputs of which are connected to the output of the memory block and the first output of the registration block, and the control input of the second element H – NO is connected to the second output of the gating pulse former, and the first and second information inputs of the first AND – IS element are connected respectively to the output of the memory block and the second output of the recording unit, and the control input of the first aND-Beams connected 'with the formation _{of the} third output gate driver, · · output the first item is NOT connected to I / the second input of the registration block, p the second output of the chronizer is connected | ( to the second input of the multiplexer, the third and fourth inputs of which are respectively informational. and gating;:, the inputs of the device, allowing the inputs and outputs of which are respectively the combined third inputs and outputs of the first and second elements AND-NOT, the control inputs of the trigger and driver are combined and are the inputs of clock pulses. 1193831 > <I