SU1347182A1 - Self-monitoring computing device - Google Patents

Abstract

The invention relates to digital automation and instrumentation technology and is intended to restore a fault counter. The purpose of the invention is to increase the reliability of the device. The counting device contains counters 1 and 2, a unit 3 of comparison and a delay element 4. The introduction of block 5 of the delay elements and the element OR 6 makes it possible to exclude from the block diagram a third counter and a second comparison block. Due to this, when one of the counters fails, the last memorized actual information is overwritten. 2 Il. 10 cl

Description

The invention relates to digital automation and instrumentation technology and is intended to become a failure meter.

The aim of the invention is to increase the reliability of the device.

The goal is achieved by eliminating the third counter, the second comparison unit and the introduction of a block of delay elements and an OR element.

The essence of the invention is to memorize the actual information and in the event of the occurrence of one of the counters overwriting it in them. For this, it is sufficient to use two counters.

Figure 1 shows the block diagram of the counting device with the control; 2 shows timing diagrams for his work.

The counting device with the control contains counters 1 to 2, a comparison unit 3, a delay element 4, a delay element block 5, an OR element 6, information outputs 7, an input bus 8, an installation bus 9 and an output bus 10.

The outputs of the counters 1 and 2 are connected respectively to the first and second group of inputs of the comparison unit 3, the output of which is connected to the input of the delay element 4, the installation bus 9 is connected to the zero input of each of the counters 1 and 2. The outputs of the counter 1 are connected to the corresponding inputs of the 5 elements block delays, the outputs of which are connected to the corresponding information inputs of counters 1 and 2, the clock inputs of which are connected to the output of the OR 6 element, the first input of which is connected to the input bus 8, and the second input to the output of the delay element 4 The input of which is connected to the auxiliary synchronization inputs of the meters G and 2. The output of the comparison unit 3 is connected to the output bus 10, and the outputs of the counter 1 to the information outputs 7 of the device.

The device works as follows.

Before work is started, the counters 1 and 2 are reset, and a pulse is sent to the device bus 9. At that, there is no signal on the bus 10 for outputting information about the failure. At the same time

five

0

five

0

yn and the same failure of the counters 1 and | 2 does not occur. By pulses coming through the input bus 8, synchronous modification of counters 1 and 2 occurs.

If counter 1 or counter 2 fails, as well as simultaneous but different failure of both counters 1 and 2, a logical zero signal appears at the output of the comparison block 3, overwriting the actual previous information from the outputs of the block 5 delay elements into counters 1 and 2. After that, the recognition at the output of the comparison unit 3, and, consequently, at the output bus 10, disappears. According to the negative differential pulse at the output of the delay element 4, the contents of the counters 1 and 2 are modified by one unit of the least significant bit. Then in the counters 1 and 2 is valid information.

Thus, in the event of a failure of counters 1 and 2, actual information is overwritten from the outputs of the block 5 delayed elements, followed by modification of the contents of the counters by a unit of the least significant bit.

The minimum delay time by the block 5 of the delay elements of the previous information with the modifications of the counters 1 and 2 is as follows:

Where

€ ZG. ,

4-6

+ 1-l

3 - -4.

- the delay time of the corresponding elements,

The minimum delay time of a signal (impulse) about the failure of counters 1 and 2 by element 4 delay is as follows:

45

Claims (1)

U g, c, + c,, Formula of invention A counting device with a control containing an input bus, an installation bus, two counters, a comparison unit, a delay element, the outputs of the first and second counters are connected respectively to the first and second groups of the input of the comparison unit, the inverse output of which is connected to the input of the delay element The installation bus is connected to the input of resetting each of the counters, which is different in that reliability, a block of delay elements and an OR element are entered into it, the outputs of the first counter are connected to the corresponding inputs of the block of delay elements, the outputs of which are connected to the corresponding information inputs of the first and second counters, clock bus 8 SjtoKu 5 output Item withdrawal Item 6 output 1347182. the primary inputs of which are connected to the output of the OR element, the first input of which is connected to the input bus, and the .g second input — to the inverse output of the delay element whose input is connected to the auxiliary synchronization inputs of the first and second counters. f to t . 2