SU809534A1 - Pulse train-to-single square pulse converter - Google Patents

Description

(54) PULSE CONVERTER OF PULSE INTO A SINGLE RECTANGULAR PULSE

I

The invention relates to automation and computing, in particular, to devices for determining the beginning and end of a series of pulses with an output signal in the form of a rectangular pulse.

A pulse train transducer to a single rectangular pulse is known, containing a trigger, a pulse counter, three matching elements, three delay elements, and an OR ij element.

The disadvantage of this converter is that for its normal operation it is necessary that the pulse period in all sequences always be equal to a certain value.

A pulse train to a single rectangular pulse is also known, which contains a trigger for generating an output pulse, two auxiliary triggers, five coincidence elements, two OR elements.

pulse counter (non-reversible) and auxiliary pulse generator 21.

A disadvantage of this device is also the fact that for its normal operation it is necessary that the period of following pulses in sequences always be equal to a certain predetermined value.

The purpose of the invention is to expand the frequency range of a converter by maintaining its operability when its input receives a sequence of pulses, the period of which from sequence to sequence changes.

This goal is achieved by converting a pulse train into a single rectangular pulse containing three flip-flops, four matching elements, a counter, an OR element and a pulse generator, the output of which is connected to the first inputs of the first and second matching elements, the second input of the last connection to the inverse the output of the first trigger, and the output of the second trigger is connected to the first input of the third element, an inverter, a counter, two decoders and a trigger, the output of which is connected with zero in-dats of main triggers and counters, the outputs of which through the decoders and the element OR are connected to the clock input of the additional trigger, the single input of which is connected to the output of the fourth match element, the first input of which is connected to the output bus, the output of the third trigger, the third input is the second the coincidence element and the information input of the second trigger, the synchronization of which is connected to the clock input of the first trip, the input bus, the synchronous input of the third trigger, and through an inverter with the second input of the fourth the coincidence element, and the direct output of the first trigger is connected to the second inputs of the first and third elements, the third input of the last is connected to the output of the pulse generator, and the output is connected to the subtractive input of an additional counter, the summing input of which is connected to the output of the second coincidence element and subtracting to the input of the main counter, the summing input of which is connected to the output of the first match element. Figure 1 shows the functional diagram of the converter of the sequence of pulses into a single direct impulse; phi% 2 - voltage diagrams illustrating the formation of the output pulse. A pulse train to a single rectangular pulse contains triggers 1–3, additional trigger 4, elements 5–8. match, the element OR 9, the counters 10 and 11, the decoders 12 and 13, the sverhor tor 14 and the generator 15 pulses. Triggers 1–3 with a low potential at the zero input go to the zero state (low level of the voltage by direct trigger output). Trigger 4 at a low potential at a single input goes into a single state (high level (at the direct output of the trigger)). The potential drop from low to high at the clock input of triggers 2 and 4 puts them in the state against the false one they occupied before the occurrence of this difference. Drop from low potential. to high on the synchronous inputs of the flip-flops 1 and 3 translates them into the state determined by the potential present at their information inputs. Counters 1O and 11 are reversible, and decoders 12 and 13 respond to the zero state of the counters. The pulse train to a single rectangular pulse operates as follows. In the initial position, triggers 1-3 and pulse counters 1O and 11 are in the zero state, and trigger 4 is in the single state. Elements 5-7 are locked for the second, third, and first inputs, respectively, and the pulses from the output of the generator 15 are not fed to the inputs of counters 10 and 11. When the first pulse of the input sequence arrives at the converter input (Fig. 2a), the triggers 1 and 2 are set to one (Fig. 26 and Fig. 2c, respectively). At the same time, the pulses from the generator output 15 pulses (Fig. 2 g ) through the coincidence element (fig. 2 d) arrive at the summing input of the counter 10, since at its Second input there is a high potential corresponding to logical 1. At this time, there are zero potentials at the second input of coincidence element 6 and at the first input of element 7 blocking the passage e pulses from the output of the generator 15 through elements 6 and 7 to the subtracting input of the counter 1O and to both inputs of the counter 11, Since the pulses from the output of the generator 15 arrive at the summing input of the counter 10, the code H (T) will be written in the latter, where T is the period following the pulses at the input of the converter, i.e., in the counter 1O, the code (FIG. 2 e) records the period of the pulses of the highly stable frequency of the generator 15 pulses. With the arrival of the second pulse of the input sequence, triggers 2 and 3 change their state, i.e. trigger 2 is set to zero s, and the trigger 3 - in a single state (FIG. 2g) have; as its information input was previously attended by a high voltage level coming from the direct output of trigger 1, now 5 and 7 coincidences are closed by their own inputs, and coincidence element 6 opens and pulses from the output of generator 15 are received through coincidence element 6 ( Fig. 2 h) to the summing input of the counter 11 and to the subtracting input of the counter 10. Now in the counter 11 the code is written (Fig. 2, and) 1, -, and the pulses arriving to the subtracting input of the counter 1O read the code written in it C. With the arrival of the third pulse, the input sequence In order to ensure that the input of the converter, the counter U is set to its original (zero) state, since it will finish reading the code N | . In this case, at the output of the decoder 12, a high voltage level (Fig. 2k) is transmitted through the Vits, which through the element OR 9 (Fig. 2l) enters the counting input of the trigger 4. The trigger 4 does not change its state, since its single input at this time there is a low voltage level coming from the output of the coincidence element 8 (Fig. 2 m). Now, the pulses from the output of the generator 15 through the elements 5 and 7 arrive respectively at the summing input of the counter 10 and at the subtracting input of the counter 11. In the counter. 10 the code A is written again and the counter H code recorded in the previous cycle is read out of the counter 11. After the N code 11 is read from the counter 11, the voltage level is high at the output of the decryptor 13 (Fig. 2n). Trigger 4 does not change its state again, since at the time of input of the converter there is an input pulse of the sequence, which is inverted by inverter 1.4 k through the element. The 8 coincidence is fed to the single input of the trigger 4. The pulse train into a single rectangular pulse up to the time point i / j (see Fig. 2) works in a similar way. When the last pulse is successively input to the converter input, the coincidence element 6 is open and through it to the subtracting input of the counter U and to the summing input of the counter 11 receives pulses from the generator 15; When this happens, the N code recorded in the previous clock is read into counter 10, and the code is written to counter 11 After reading the N code from counter 46 10, a high voltage level appears at the output of decoder 12, which through the OR 9 element goes to the trigger input of the trigger 4. At this moment of time at the input of the converter, the input pulse is absent and trigger 4 is not held. Forcibly in one state. Therefore, the difference from low potential to high at the clock input of the trigger 4, the latter is transferred to the zero state (Fig. 2). The zero potential from the direct output of trigger 4 is fed to the zero inputs of triggers 1–3 and pulse counters. In this case, the triggers and counters are set to the zero state. Setting trigger 1 to the zero state indicates the end of the input pulse sequence. The low potential from the single output of the trigger 1 through the coincidence element 8 is fed to the single input of the trigger 4, returning it to the single state. Thus, the pulse train transducer into a single rectangular pulse returns to the original polishing. Form A of the Invention A pulse train transducer into a single rectangular pulse containing three flip-flops, four elements matching a counter, an OR element and a pulse generator, the output of which is connected to the first inputs of the first and second matching elements, the second input of the last connected to the inverted output of the first trigger, and the output of the second trigger is connected to the first input of the third coincidence element, characterized in that, in order to expand the frequency range, an inverter is additionally inserted into it, a cheek, two debrishers, and the output of which is connected to} 1 zero inputs of main triggers and counters, the outputs of which are skull decoders and the OR element are connected to the clock input of the additional trigger, the single input of which is connected to the output of the fourth match element, the first input of which is connected to the output bus, the output of the third trigger, the third input of the second match element and the information input of the second trigger, the synchronous input of which is connected to the clock input of the first

trigger, input bus, synchronous input of the third trigger and through an inverter with the second input of the fourth match element, and the direct output of the first trigger is connected to the second inputs of the first and third match elements, the third input of the last is connected to the output of the pulse generator, and the output is connected to. subtractive input of the additional counter, the input of which is connected to the output of the second element

match and subtract the input of the main counter, the summing input of which is connected to the output of the first element of the match.

Sources of information taken into account in the examination

1. USSR author's certificate number 577651, cl. H 03 K 5 / GS, 1977.

2. USSR author's certificate N 362447, cl. N OZ 5/156, 1972.

Claims (1)

30 claims A pulse sequence converter into a single rectangular pulse containing three triggers, four 35 elements matching the counter, an OR element and a pulse generator, the output of which is connected to the first inputs of the first and second coincidence elements, the second input of the latter is connected 40 to the inverse output of the first trigger, and the output of the second the trigger is connected to the first input of the third coincidence element, characterized in that, in order to expand the frequency range, an inverter, a counter, two decoders are additionally introduced into it and trigger whose output is connected to the zero-input basic flops and counters whose outputs through deshi ₅₀ fratory and an OR gate connected to the clock input of the additional trigger unit whose input is connected to the output of the fourth matching element having a first input connected to the output line, the output of the third the trigger, the third input of the second match element and the information input of the second trigger, the clock input of which is connected to the clock input of the first trigger, the input bus, the clock input of the third trigger and Erez inverter to the second input of the fourth matching element, and a direct output of the first flip-flop is connected to the second inputs of the first and third coincidence elements, the third input of the latter connected to the output. pulse generator, and the output is connected to. subtracting the input of an additional counter, the simulating input of which is <connected to the output of the second element 8 . coincidence and subtracting input of the main counter, the summing input of which is connected to the output of the first element of coincidence.