JPH088545B2 - Parallel detection type frame synchronization method and its circuit and PCM transmission device - Google Patents

Description

The present invention relates to a method for parallelly detecting a frame synchronization pattern included in high-speed frame format data, a circuit for the method, and a PCM including the circuit. The present invention relates to a transmission apparatus, and more particularly to a frame synchronization method and a circuit therefor capable of obtaining good synchronization recovery characteristics by an operation equivalent to serial 1-bit shift, and a PCM transmission apparatus including the circuit.

[Prior Art] The conventional parallel detection type frame synchronization method is compared with the delay detection shift method as the serial detection type in the paper "Practical application of PCM-400M multiplex converter" (Research Practical Report No. 1). Vol. 25, No. 1, 1976). In this case, in the parallel detection type, the high-order group signal is first demultiplexed into the low-order group signals, and a frame synchronization circuit that operates in parallel is provided for each of the demultiplexed low-order group signals, so that frame synchronization is performed. It is supposed to be taken.
In this case, the channel order may be changed according to the synchronization recovery mode, and although the circuit scale increases, it can be configured by a constant speed logic circuit.

[Problems to be Solved by the Invention] However, in the case of the above-mentioned conventional technique, as described in the article, the worst average synchronization recovery time is about 20 times as compared with the delay concentrated shift method in which high-speed serial processing is performed.
There is a problem that it increases by%. This is because when the frame sync pattern detection result is not obtained at the expected time position, the other frame sync pattern detection results at the same detection time are ignored, and as a result, the synchronization is quickly recovered. This is because he was unable to take action.

In addition to the problem, if the parallel detection number is set to an integer (generally an integer of 2 or more) times the minimum required parallel detection number in order to further reduce the processing speed,
The synchronization recovery time may be extremely long, which may adversely affect the data transmission system. For example, when the number of multiplexing is 4, the number of bits constituting the normal frame synchronization pattern is 4, and whether or not the frame synchronization pattern exists in continuous 7-bit data is detected as the parallel detection number 4. When the number of detections is set to 8, it is detected whether or not the frame synchronization pattern exists in the continuous 11-bit data, and depending on the specific input data pattern, two frame synchronization patterns are simultaneously generated. That is, it may be detected as a high probability. In such a case, which frame synchronization pattern detection result should be prioritized or appropriate priority control needs to be adopted. However, if no consideration is given to this, the synchronization recovery time becomes extremely long. Is there. Even when the number of parallel detections is the minimum, two such frame synchronization patterns may be detected at the same time. Such a phenomenon is prevented in advance depending on the selection of the pattern of the frame synchronization pattern. It has become a thing. For example, if the pattern of the frame synchronization pattern is set to "1111", and if all 7-bit patterns to be detected accidentally become "1111111", two frame synchronization patterns are detected at the same time. is there. However, for example, when "1100" is set, theoretically one frame synchronization pattern may be detected, but two frame synchronization patterns cannot be detected at the same time.

An object of the present invention is to provide a parallel detection type frame synchronization method capable of obtaining the same synchronization recovery characteristics as in the case of serial 1-bit shift even in the parallel detection type frame synchronization method. Another object of the present invention is to provide a parallel detection type frame synchronization method in which the synchronization recovery characteristic is not extremely deteriorated even when the number of parallel detections is set to an integer multiple of the minimum required number of parallel detections. is there. Further, the present invention provides a parallel detection type frame synchronization circuit corresponding to those methods, a PCM transmission device equipped with the frame synchronization circuit, and a PCM transmission device as a multiplex conversion device.

[Means for Solving the Problem] The above-mentioned object is to use n (n: 2) as a frame synchronization pattern.
The above integer) bit continuous specific pattern is k · n · m (k,
(m: integer greater than or equal to 1) From the frame format transmission data inserted in the bit format, the frame synchronization pattern is continuously detected in the k, n, m bit period, and The frame synchronization is established with the position of the frame as the frame start position. At this time, each time the data is sequentially parallel-converted from the frame format transmission data in units of k · n bits, the parallel conversion data and the immediately preceding parallel conversion data are converted. Time-consecutive k · n + n−1-bit data is created from the subsequent n−1-bit data, and a frame is created in each of k · n continuous n-bit data shifted by 1 bit from the created data. The presence or absence of frame synchronization patterns is detected at the same time at the pulse timing, and the existence of these frame synchronization patterns is detected. When each detection result is temporarily held, it is invalidated by masking the presence / absence detection result of the frame synchronization pattern detection on the preceding side of the presence / absence detection result of the frame synchronization pattern detection held immediately before. At the very least, while the presence / absence detection result related to the frame synchronization pattern detection on the posterior side is utilized,
When none of the presence / absence detection results after masking indicate frame sync pattern detection in the frame out-of-sync state, k / n bit units are transmitted on the frame format transmission data until the frame sync pattern is detected. This is achieved by performing the frame synchronization pattern detection operation while shifting the frame synchronization pattern detection position to the rear side.
Another object is that when the number of parallel detections is set to be twice or more, generally two or more frame synchronization patterns may be detected at the same time. This is achieved by masking the presence / absence detection result related to the frame synchronization pattern detection on the succeeding side by the presence / absence detection result related to the frame synchronization pattern detection on the subordinate side.

As the frame synchronization circuit, and when making the holding circuit hold the detection result of the presence or absence of the frame synchronization pattern,
The presence / absence detection result related to the frame synchronization pattern detection held immediately before is used to mask the presence / absence detection result related to the frame synchronization pattern detection on the preceding side by the preceding mask circuit, while the preceding mask is performed in the frame out of sync state. When the presence / absence detection result from the circuit does not include the presence / absence detection result related to the frame synchronization pattern detection, the counter operation in the frame counter is kept generating the frame pulse until the frame synchronization pattern is detected. It is achieved by configuring to stop. When the number of parallel detections is set to be twice or more, the presence / absence detection result relating to the foremost-side frame synchronization pattern detection included in the presence / absence detection result from the anterior mask circuit is also used to detect the presence of This is achieved by masking the presence / absence detection result related to the frame synchronization pattern detection with the subsequent mask circuit.

Furthermore, by providing such a frame synchronization circuit in a PCM transmission device, when the PCM transmission device is a multiplex conversion device, it is also achieved by adding a channel switching circuit to the frame synchronization circuit.

[Operation] Parallel k.n + n-1 bit data is created from the frame format transmission data at a k.n bit period. Whether or not a frame synchronization pattern is included in this data is detected by the timing of the frame pulse. It is supposed to be done. If no frame synchronization pattern is detected at the timing of the frame pulse, the frame pulse is kept as it is until the frame synchronization pattern is detected. It is supposed to be done. On the other hand, when the frame synchronization pattern is once detected at any of the parallel detection positions, the detection result is held, the so-called backward protection operation is once entered, and the frame synchronization pattern is again detected at the same parallel detection position at the next frame synchronization. Is detected. If it is detected at the same parallel detection position, the backward protection operation is continued, but if it is detected at another parallel detection position, the backward protection operation is canceled and predetermined control is performed. It is one that has become. That is, when the frame sync pattern is detected at the parallel detection position on the front side of the parallel detection position where the frame sync pattern was detected immediately before, the result of the frame sync pattern detection is masked and ignored. The same operation is performed as when no is detected. However, if it is detected at the parallel detection position on the rear side of that, the result of the frame synchronization pattern detection is held as valid, and thereafter, the backward protection operation based on this parallel detection position is newly added. It is the one that is supposed to start. When the number of parallel detections is set to twice or more, two or more frame synchronization pattern detection results may be detected at the same time. In such a case, only the result of the frontmost frame synchronization pattern detection is detected. As effective, by masking the result of the frame synchronization pattern detection on the posterior side thereof, deterioration of the synchronization recovery time due to a malfunction can be prevented.

Therefore, the frame synchronization circuit may be configured to operate as described above. When the frame synchronization circuit configured as described above is provided in the PCM transmission device, the frame is transmitted from the high-speed frame format transmission data. The synchronization pattern can be detected by using a low-speed logic circuit except for a part of the circuit in the same manner as in the serial 1-bit shift operation, and with good synchronization recovery characteristics.
If the PCM transmission device is a demultiplexing device, a frame synchronization pattern is detected from the high-speed frame format transmission data as a high-order group signal, and a plurality of low-order group signals are demultiplexed after frame synchronization is established. However, since which of the parallel k · n + n−1-bit data corresponds to each of the low-order group signals can be easily known from the output of the holding circuit in the frame synchronization established state, the holding circuit is used in the channel switching circuit. Parallel k based on output
The data corresponding to the low-order group signal should be extracted from the n + n-1 bit data.

EXAMPLES The present invention will be described below with reference to FIGS. 1 (a), (b) and FIG.

1 (a) and 1 (b) are PCM transmission devices according to the present invention,
More specifically, it shows the configuration of an example of the multiplex conversion device. As shown in the figure, in this example, the number of multiplexing is 4, and the number of parallel detections is 4, which is assumed to be the minimum necessary, and "1100" is assumed as the frame synchronization pattern. ing.

That is, data transmitted from the high-speed frame format transmission data is sequentially parallel-converted in 4-bit units by a parallel converter (not shown in this example) that operates at high speed. The parallel conversion unit is specifically composed of a serial-in / parallel-out type 4-bit shift register and a quaternary counter. The 4-bit parallel conversion data DI from the parallel conversion unit is a clock CK having a 4-bit period. At the same time, it is transferred to the frame synchronization pattern parallel detection unit 1. In the frame synchronization pattern parallel detection section 1, the parallel conversion data DI is sequentially set in parallel in the 7-bit capacity register 2 by the clock CK, but the Q5 to Q7 outputs of the register 2 are fed back to the input side, It appears as Q1 to Q3 outputs when the next parallel conversion data is set.
The bit parallel conversion data is obtained in a 4-bit cycle. Since this parallel conversion data includes four continuous 4-bit data, whether the 4-bit data appears as a frame synchronization pattern is detected by the gates 3 to 6 at the timing of the frame pulse FP. There is something. The detection results at the gates 3 to 6 are obtained as the presence / absence detection results described above.
If we define "front" and "rear" while delaying here, "front" means the side that appears earlier in time, and "rear" means the side that appears later in time. It has been done. Therefore, if the presence detection results D1 to D4 are taken as examples, these results are obtained at the same time, but the presence detection result D1 is related to the leading bit, and the presence detection result D4 is the latter. It is related to the side bit.

Now, the presence / absence detection results D1 to D4 are the D-type flip-flops () that form the holding circuit via the gates 7 to 9 that form the preceding mask circuit and the gates 10 to 12 that form the posterior mask circuit. (Hereinafter simply referred to as F / F) It is temporarily held by the timing of the clock CK while the hunting pulse HUNT is present in 13 to 16, but at that time it is not simply held and is masked to a predetermined level. It is controlled and retained. F / F13 to 16 in the preceding mask circuit
The presence / absence detection result relating to the frame synchronization pattern detection held in any of the above masks the presence / absence detection result relating to the frame synchronization pattern detection on the preceding side. For example, assuming that the F / F14 holds the presence / absence detection result related to the frame synchronization pattern detection, only the presence / absence detection result D1 is ignored.
The presence / absence detection results D1 and D2 are ignored when the F / F15 holds the presence / absence detection results related to the frame synchronization pattern detection. After all, depending on the anterior mask circuit, the direction of the bit as the frame synchronization pattern detection target is always restricted to the posterior side. In addition, the rear mask circuit functions to select only the frontmost one of the presence / absence detection results related to the detection of two or more frame synchronization patterns from the front mask circuit. There is. For example, when the results of frame synchronization pattern detection are simultaneously obtained from the gates 7 to 9, only the one from the gate 7 is selectively output,
Those from 9 are the ones that are ignored. However, in the case of this example, since the pattern of the frame synchronization pattern is set appropriately, the posterior mask circuit is unnecessary.
However, when the number of parallel detections is set to be twice or more, two or more frame synchronization patterns may be detected at the same time, so that the posterior mask circuit is clearly necessary.

As described above, the frame sync pattern is detected under the towing control by the frame pulse and the hunting pulse, and FIG. 1B shows the configuration of an example of the control part including the sync protection counter. As shown, presence / absence detection results D1 to D4, posterior mask circuit outputs F1 to F4 and holding circuit outputs H1 to H4, and frame pulse FP, hunting pulse HUNT, and frame synchronization establishment signal FSYNC are obtained based on clock CK. It is like this.
That is, the presence / absence detection results D1 to D4 and the holding circuit outputs H1 to H4 are logically ANDed by the AND gates 18 to 21, respectively, and these logical AND results are logically ORed by the OR gate 22 to obtain the actual result. Whether or not the result of the frame synchronization pattern detection is continuously obtained at the same parallel detection position as the held result of the frame synchronization pattern detection is detected. Also, the rear mask circuit output F1 ~
The OR of the F4 is performed by the OR gate 23 to detect whether or not at least one frame sync pattern detection result is included in the outputs. The frame counter 28 also generates a frame pulse FP every time it counts m clocks CK having a k · n bit cycle. However, in a certain case, the counting operation continues for an unspecified time immediately after the frame pulse FP is generated. The frame pulse FP is continuously obtained during that time. The hunting pulse HUNT is the frame pulse FP when the frame synchronization establishment signal FSYNC is not obtained (frame synchronization loss state) and the frame synchronization pattern detection result is not continuously obtained at the same parallel detection position. Although it is obtained from the gate 26 at the timing of, the output of the OR gate 23 is monitored while the hunting pulse HUNT is obtained in the gate 27, and the result of the frame synchronization pattern detection is detected in the subsequent mask circuit outputs F1 to F4. If not included, gate 27 only in between
The count operation of the frame counter 28 is stopped by the count inhibit signal CNTINH from.
After that, the count operation is stopped after
It is designed to be released only when the result of the frame synchronization pattern detection is included in any of F4.

By the way, in the synchronization protection counter 25, the rising edge of the hunting pulse HUNT is detected inside, and while this detection signal is reset as a reset signal, the hunting pulse HUNT is used as a selection control signal to output the OR gates 22 and 23. By selectively capturing and performing a counting operation according to a predetermined rule under the timing of the frame pulse FP, it operates to determine whether the current state is the out-of-frame synchronization state or the frame-synchronization established state. Has become. While the OR gate 23 output is taken in while the hunting pulse HUNT is obtained, and the OR gate 22 output is taken in as the selection output DET from the selector 24 while it is not obtained, the simultaneous protection counter 25 Since the operation in the control part including the above is complicated, it will be described below with reference to FIG.

That is, the holding circuit is reset in the initial state, and the frame counter 25 has the frame pulse FP.
Has been initially installed to be output. Therefore, the hunting pulse HUNT is also output. Therefore, in this state, the OR gate 23 continuously monitors that the frame synchronization pattern appears for the first time in the 7-bit parel conversion data updated in the 4-bit cycle, which is sequentially obtained from the register 2. Meanwhile, the frame counter 28 is continuously stopped by the gate 27.
Assuming that the gate 4 eventually detects a frame synchronization pattern, the detection result appears as it is as the subsequent mask circuit output F2, and as a result, the counting operation of the frame counter 28 is stopped via the gates 23 and 27. It is canceled. When the stop of the counting operation is released, the frame counter 28 counts the clock CK immediately after that, so that the frame pulse FP is not output. As a result, the hunting pulse HUNT cannot be obtained either, but while the hunting pulse HUNT is being output, the sync masking counter 25 enables the frame pulse FP by the output of the rear mask circuit F2 via the OR gate 23 and the selector 24. The signal is incremented by one. On the other hand, in the holding circuit, F / F1
In FIG. 4, the posterior mask circuit output F2 is set in synchronization with the clock CK using the hunting pulse HUNT as an enable signal. As a result, the state is changed from the initial state to the backward protection state. Now, after that, the frame counter 28 is about to generate the frame pulse FP again after continuously counting the m clocks CK, and the operation when the frame pulse FP is generated again is as follows. Generally, various cases are considered.

(1) When the frame synchronization pattern is detected again by the gate 4, the rear-end mask circuit output F2 appears again,
This fact is detected by the AND gate 19, so that the generation of the hunting pulse HUNT at the gate 26 is suppressed. As a result, the F / F 14 does not newly hold the detection result of the frame sync pattern, and the output of the AND gate 19 via the selector 24 causes the sync protection counter 25 to be further incremented by one. . In this way, when the frame synchronization pattern is continuously detected by the gate 4 every time the frame pulse FP is generated, it is detected that the frame synchronization pattern is continuously detected for a certain number of times, and the state is shifted to the frame synchronization establishment state. It is what is done. In this state, the frame synchronization establishment signal FSYNC is obtained from the synchronization protection counter 25, and once the frame synchronization establishment signal FSYNC is obtained, the frame synchronization pattern is not detected continuously for a certain number of times. The synchronization establishment signal FSYNC cannot be obtained.

(2) Also, if the frame sync pattern is detected at the gate 5 on the rear side of the gate 4, the result of the frame sync pattern detection is not set in the F / F16. The result of the frame sync pattern detection is directly set in the F / F 15 via the gates 9 and 11. Further, in this case, since the frame synchronization pattern is not continuously detected in the same gate, the condition is not satisfied in any of the AND gates 18 to 21. Therefore, the hunting is performed from the gate 26 at the timing of the frame pulse FP. The pulse HUNT is designed to be obtained. As a result, the synchronization protection counter is once reset, but immediately after that, it is incremented by 1 by the subsequent mask circuit output F3. In this case, the count prohibit signal CN
Since the occurrence of TINH is suppressed, the frame counter 28
In, the count operation is not stopped but the count operation is continued. That is, it is expected that the gate 5 will detect the frame synchronization pattern when the next frame pulse FP is generated. Such a situation is the same when the gate 6 detects a frame synchronization pattern.

(3) If the frame sync pattern is detected by the gate 3 on the front side of the gate 4, the result of the frame sync pattern detection is output by the gate 7 to the holding circuit.
This is suppressed by H2, and as a result, neither condition is satisfied by the AND gates 18 to 21, and the hunting pulse HUNT is obtained from the gate 26. The synchronization protection counter 25 is once reset by the hunting pulse HUNT. Further, in this case, since the results of the frame synchronization pattern detection are not included in the outputs of the subsequent mask circuits F1 to F4, the gate 27 stops the counting operation of the frame counter 28. That is, the state is shifted to the initial state, and the gate 3 to
The frame pulse FP and the hunting pulse HUNT are left as they are until the frame synchronization pattern is detected in any of the steps 6.

(4) If none of the gates 3 to 6 detects a frame synchronization pattern, the result is that the same operation as in (3) is performed.

Explaining the channel switching circuit 17, the channel switching circuit 17 outputs a predetermined 4 bits from the 7-bit parallel conversion data from the frame synchronization pattern parallel detection unit 1 in the frame synchronization established state.
The signal is extracted based on H1 to H4 and then output as a low-order group signal D0. The high-order group signal as the frame format transmission data is bit-multiplexed with a multiplexing number of 4, but F / F13 to 1 in the frame synchronization establishment state.
If it is known in which of 6 the frame synchronization pattern detection result is set, 4 bits can be easily extracted as corresponding to the low-order group signal. Incidentally, if the frame synchronization establishment state is explained in detail, since the frame synchronization establishment signal FSYNC is obtained in this state,
The hunting pulse HUNT is not output, and the counting operation of the frame counter 28 is not stopped. In the frame synchronization established state, holding circuit outputs H1 to H4
Each time the presence detection results D1 to D4 at the gates 3 to 6 are not satisfied by any of the AND gates 18 to 21 at the timing of the frame pulse FP, the synchronization protection cassunter 25 outputs the OR gate 22 output to that effect. However, the frame synchronization establishment signal FSYNC can no longer be obtained only when such counting is continuously performed a certain number of times (forward protection number of times), and instead of this, the hunting pulse HUNT
Is obtained, the process shifts to any one of the above (1) to (4), and the frame synchronization is restored again.

From the above description, it is clear that the same operation as the 1-bit shift in the serial processing is performed. However, even if the number of parallel detections is doubled or tripled, such an operation is similar. It can be easily inferred that it can work. When the number of parallels is set more than twice, the capacity of the register 2 and the number of various gates and F / Fs are only required for that much, and the operation is correct depending on the existence of the posterior mask circuit. It will be guaranteed.

[Effects of the Invention] As described above, in the case of claim 1, even in the parallel detection type frame synchronization method, the same synchronization recovery characteristic as in the case of serial 1-bit shift can be obtained. Even if the number of parallel detections is set to an integer multiple of the minimum required number of parallel detections, the synchronization recovery characteristic is considered to be good. A detection-type frame synchronization circuit is also provided.
In the case of 5 and 6, it is possible to obtain a PCM transmission device and a multiplex conversion device that have good frame synchronization recovery characteristics.

[Brief description of drawings]

1 (a) and 1 (b) are diagrams showing the configuration of an example of the multiplex conversion device according to the present invention, and FIG. 2 is a diagram for explaining the operation thereof. 1 ... Frame synchronization pattern parallel detection unit, 7 to 9 ...
Gate (for anterior mask), 10 to 12 …… (for posterior mask)
Gate, 13 to 16 …… (for holding circuit) D-type flip-flop, 17 …… Channel switching circuit, 24 …… Selector, 25…
… Synchronization protection counter, 28 …… Frame counter

Claims (6)

[Claims] 1. An n (n: integer of 2 or more) bit continuous specific pattern as a frame synchronization pattern is k.n.m (k, m:
(Integer of 1 or more) From the frame format transmission data inserted in the bit cycle, the frame synchronization pattern is k
・ Because it was detected continuously in the n · m bit cycle,
A frame synchronization method for establishing frame synchronization by using the position of the pattern on the frame format transmission data as a frame head position, and the data is sequentially parallel-converted from the frame format transmission data in units of k · n bits. , N × n consecutive n bits shifted by 1 bit in the temporally consecutive K · n + n−1 bit data consisting of the parallel transformed data and the n−1 bit data of the last side of the immediately preceding parallel transformed data. Presence / absence of the frame synchronization pattern is detected by the frame pulse as the frame synchronization pattern detection timing, which is generated from the initial state at each bit data parallel detection position and has a variable cycle and pulse width. The detection results are linked to the same parallel detection position with the frame out of sync. When the presence / absence detection result relating to the frame synchronization pattern detection is not obtained, and the update is temporarily held in synchronization with the clock of the kn bit period while the frame pulse is present, ,
The presence / absence detection result related to the frame synchronization pattern detection at the front side parallel detection position relative to the presence / absence detection result related to the frame synchronization pattern detection held immediately before is held and masked, and the frame synchronization is lost. In the same parallel detection position, the presence / absence detection result related to the frame synchronization pattern detection is not obtained continuously, and the presence / absence detection result OR after masking while the frame pulse is present is k. While the pulse width and period of the frame pulse generated in the n · m bit period are controlled, based on the frame pulse, presence / absence detection result before and after masking, and retained presence / absence detection result. Is a parallel detection type frame synchronization method in which frame synchronization is lost and frame synchronization establishment is determined. 2. When each of the presence / absence detection results of the masked frame synchronization pattern is held, each of the presence / absence detection results after masking is followed by the presence / absence detection result related to the detection of the frame synchronization pattern on the frontmost side of the results. 2. The parallel detection type frame synchronization method according to claim 1, wherein the holding is performed such that the presence / absence detection result related to the detection of the frame synchronization pattern on the upper side is masked. 3. An n (n: integer of 2 or more) bit continuous specific pattern as a frame synchronization pattern is k.n.m (k, m:
(Integer of 1 or more) From the frame format transmission data inserted in the bit cycle, the frame synchronization pattern is k
・ Because it was detected continuously in the n · m bit cycle,
A frame synchronization circuit for establishing frame synchronization by using the position of the pattern on the frame format transmission data as a frame head position, and a parallel conversion for sequentially performing parallel conversion of the data from the frame format transmission data in units of k · n bits. Section, the parallel conversion data from the conversion section and the trailing side n-1 of the immediately preceding parallel conversion data
Time-consecutive kn + n-1 bit data is created from the bit data and then kn shifted by 1 bit
A frame synchronization pattern for detecting the presence or absence of a frame synchronization pattern by a frame pulse as a frame synchronization pattern detection timing, which is generated from an initial state and has a variable cycle and pulse width at parallel detection positions corresponding to consecutive n-bit data. Parallel detection unit, each of the frame synchronization pattern presence or absence detection result from the detection unit, the presence or absence detection result related to the frame synchronization pattern detection is not obtained continuously at the same parallel detection position in the frame out of sync state,
In addition, a holding circuit that temporarily holds the renewal in synchronization with a clock having a k · n bit period while the frame pulse is present, and is provided between the holding circuit and the frame synchronization pattern parallel detection unit. Based on the presence / absence detection result related to the immediately preceding held frame synchronization pattern detection from the holding circuit, a preceding mask circuit for masking the presence / absence detection result on the preceding side of the result, and a clock of k · n bit cycle m times A frame pulse is output each time it is counted, and the presence / absence detection result related to the frame synchronization pattern detection is not continuously obtained at the same parallel detection position in the frame out-of-sync state. A frame counter whose count operation is stopped and controlled based on the subsequent OR detection result OR, a frame pulse from the counter, a mask before, a mask And presence or absence detection result after click, off the frame on the basis of the presence or absence detection result held synchronized, parallel detection type frame synchronizing circuit arrangement including a synchronization protection counter to determine the frame synchronization establishment. 4. The presence / absence detection result from the preceding mask circuit is placed between the preceding mask circuit and the holding circuit according to the presence / absence detection result related to the detection of the frame synchronization pattern on the most significant side. 4. The parallel detection type frame synchronization circuit according to claim 3, wherein a rear mask circuit for masking the presence / absence detection result of the frame synchronization pattern detection according to claim 3 is provided. 5. A PCM transmission device comprising the parallel detection type frame synchronization circuit according to claim 3, for receiving frame format transmission data from the outside. 6. When the PCM transmission device is a multiplex conversion device, the channel switching circuit performs frame synchronization based on the presence / absence detection result of only one frame synchronization pattern detection from the holding circuit in the frame synchronization established state. 6. The PCM transmission device according to claim 5, wherein the low-order group signal related to the number of multiplexing n is separated and extracted from the parallel k · n + n−1 bit data from the pattern parallel detector in a predetermined manner.