JP2680953B2 - Frame synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention is used in a PCM multiplex converter. In particular, it relates to a frame synchronization circuit for demultiplexing multiplexed group signals.

[0002]

2. Description of the Related Art As shown in FIG. 3, a prior art circuit inputs a received PCM code string, a frame sync pulse 2b and outputs various timing signals, and a timing pulse generation circuit 22. Frame pulse generation circuit 23 for inputting and outputting frame pulse signal 2c
, And the frame count pulse 2b is input to input the sync count signal 2
Synchronous counting circuit 2 for outputting h and asynchronous counting signal 2g
4 and a synchronization protection circuit 25 which inputs the synchronous count signal 2h and the asynchronous count signal 2g and outputs the hunting hold signal 2j. Next, the operation will be described with reference to FIG. Under the condition of forward count N = 8 and backward count M = 2,
At the time when synchronization mismatches are continued 1 to 7 times after the backward count M = 2 is satisfied in advance, the mismatching pulse 2d is not output by the output of the hunting hold signal 2j and the synchronous hunting does not start. Next, when 8 consecutive synchronization mismatches occur, the forward count becomes N = 8, and the hunting hold signal 2j is released by the output of the asynchronous count signal 2g, but the delay D1 of the counting circuit and the delay D2 of the protection circuit do not match. Since the pulse 2d cannot be detected, the hunting delay time is generated because the synchronous hunting cannot be immediately started. Next, the non-coincidence pulse 2d can be detected at the time when 9 consecutive non-coincidences occur, and the clock pulse 2a from the next is prohibited and the frame pulse 2c is shifted to the frame sync pulse 2b of the received code string. Move. Next, at the first synchronization coincidence point, the frame pulse 2c is changed to the frame synchronization pulse 2b by the period loop.
Automatically cancels the mismatch pulse 2d to end the synchronous hunting and cancels the output of the asynchronous count signal 2g. Next, when the synchronization coincidence is repeated twice, the backward count becomes M = 2, and the hunting hold signal 2j is output by the output of the synchronization count signal 2h. The above operation is repeated due to a code error in the received code string.

[0003]

In such a conventional example, since the sync protection circuit is provided, even if the sync counting circuit becomes full count due to the delay time of the sync protection circuit in the actual circuit configuration, the hunting cannot be immediately started. , The next mismatch pulse causes hunting, so when the size of the counting circuit is, for example, N = 8 stages, N becomes 9 effectively and the hunting delay time becomes 9 frames, which is added to the synchronization recovery time. There was a drawback.

The present invention eliminates such drawbacks, and an object of the present invention is to provide a frame synchronization circuit having means for preventing delay of synchronous hunting.

[0005]

According to the present invention, there is provided a sync pattern detecting circuit for inputting a PCM code string and outputting a frame sync pulse, and a PC for inputting by the sync pattern detecting circuit.
A timing pulse generation circuit that inputs a clock pulse associated with an M code sequence and outputs a timing pulse signal, and a frame pulse generation circuit that inputs a timing pulse signal output from this timing pulse generation circuit and outputs a frame pulse signal, A synchronization counting circuit that inputs a frame synchronization pulse output from the synchronization pattern detection circuit and outputs a synchronization counting signal, and a synchronization counting signal output from this synchronization counting circuit, and when the count value N is reached, a hunting hold signal is issued. In a frame synchronization circuit including a synchronization protection circuit for outputting, a retiming circuit that counts the synchronization count signal output by the synchronization count circuit and outputs a hold mask signal when the count value N-1 is reached, and this retiming circuit Logic circuit that prohibits output of hunting hold signal by hold mask signal output from circuit Characterized by comprising a.

[0006]

When the size before the full count of the synchronous counting circuit is counted, the hunting suspension is prohibited. As a result, even if the synchronization counting circuit reaches the full count due to the delay time of the synchronization protection circuit, it is not possible to immediately shift to synchronous hunting, and it is possible to prevent a hunting delay from shifting to hunting due to the next synchronization mismatch.

[0007]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram of this embodiment. In this embodiment, as shown in FIG. 1, a sync pattern detection circuit 11 that inputs a PCM code string and outputs a frame sync pulse 1b, and a PCM that the sync pattern detection circuit 11 inputs.
Timing pulse generation circuit 12 for inputting clock pulse 1a accompanying a code string and outputting a timing pulse signal
, A frame pulse generation circuit 13 that receives the timing pulse signal output from the timing pulse generation circuit 12 and outputs the frame pulse 1c, and a frame synchronization pulse 1b output from the synchronization pattern detection circuit 11 that receives the synchronization count signal 1h. In a frame synchronization circuit having a sync counter circuit 14 for outputting a sync count circuit 1 and a sync protection circuit 15 for counting the sync count signal 1h output by the sync count circuit 14 and outputting a hunting hold signal 1j when the count value N is reached, The hunting hold is performed by the retiming circuit 16 that counts the synchronization count signal 1h output from the synchronization counting circuit 14 and outputs the hold mask signal 1i when the count value N-1 is reached, and the hold mask signal 1i output from the retiming circuit 16. And a logic circuit that prohibits the output of the signal 1j.

Next, the operation of this embodiment will be described. FIG.
FIG. 4 is a timing chart showing the operation of this embodiment. Under the condition of the forward count N = 8 and the backward count M = 2, when the backward mismatch M = 2 is satisfied in advance, the hunting hold signal 1
Since the mismatch pulse 1d is not output due to the output of j, the synchronous hunting does not proceed. Next, when 7 times of synchronization disagreement continue, the forward count becomes N = 7, and the hunting hold signal 1j is temporarily masked by the output of the hold mask signal 1i, but it does not shift to the synchronous hunting. Next, at the point of time when eight consecutive synchronization mismatches occur, the forward count becomes N = 8, and the delay D1 of the synchronization counting circuit 14 and the delay D2 of the synchronization protection circuit 15 are used to release the hunting hold signal 1j due to the output of the asynchronous counting signal 1g. However, the unmatched pulse 1d can be detected by the holding mask signal 1i.
The next clock pulse 1a is prohibited, and the frame pulse 1c immediately shifts to the synchronous hunting in which the frame pulse 1c of the received code string is shifted to the point of the frame synchronous pulse 1b without causing a hunting delay time. Next, at the time of the first synchronization coincidence, the frame pulse 1c in the period loop releases the frame synchronization pulse 1b to end the synchronous hunting, and releases the asynchronous count signal 1g and the hold mask signal 1i. Next, when the second synchronization coincidence is continued, the backward count becomes M = 2, and the hunting hold signal 1j is output by the output of the synchronization count signal 1h. The above operation is repeated due to a code error in the received code string.

[0009]

As described above, according to the present invention, the hunting hold signal is temporarily prohibited, so that the hunting delay time is not added to the synchronization recovery time. Further, there is an effect that no circuit correction is required when a low speed system circuit is used for a high speed system circuit or when a logic simulation is delayed by a gated array design.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the embodiment of the present invention.

FIG. 3 is a block diagram showing the configuration of a conventional example.

FIG. 4 is a timing chart showing the operation of the conventional example.

[Explanation of symbols]

 11, 21 Synchronous pattern detection circuit 12, 22 Timing pulse generation circuit 13, 23 Frame pulse generation circuit 14, 24 Synchronous counting circuit 15, 25 Synchronous protection circuit 16 Retiming circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-2-65430 (JP, A) JP-A-63-269840 (JP, A) JP-A-1-229537 (JP, A) JP-A-2- 156743 (JP, A)

Claims (1)

(57) [Claims] 1. A synchronization pattern detection circuit for inputting a PCM code sequence and outputting a frame synchronization pulse, and a timing for inputting a clock pulse associated with the PCM code sequence input by this synchronization pattern detection circuit and outputting a timing pulse signal. A pulse generation circuit, a frame pulse generation circuit that inputs a timing pulse signal output from this timing pulse generation circuit to output a frame pulse signal, and a frame synchronization pulse output from the above synchronization pattern detection circuit To the timing pulse generating circuit when counting the synchronous count signal output from the synchronous counter circuit and reaching the count value N.
Stop the output of the frame pulse signal to
In a frame synchronization circuit equipped with a synchronization protection circuit that outputs a hunting hold signal for holding the hunting operation by the chain detection circuit, the synchronization count signal output from the synchronization count circuit is counted to obtain a count value N. A frame synchronization circuit comprising: a retiming circuit that outputs a hold mask signal when -1 is reached; and a logic circuit that prohibits the output of the hunting hold signal with the hold mask signal output by the retiming circuit.