JPH04323928A - Frame synchronizing device - Google Patents

Abstract

PURPOSE:To reduce the synchronizing recovery time. CONSTITUTION:The device is provided with two frame synchronizing circuits 2, 3, a synchronization detection priority control circuit 6 allows a frame counter giving priority based on a prescribed priority control rule to continue the synchronization detection upon the detection of a frame synchronization pattern in a same frame phase from a hunting state and allows other frame counters to start hunting again from the state of one bit shift from the phase and gives a synchronization detection priority signal giving priority to other frame synchronization circuit entering the synchronization detection state to the frame counters 4, 5 when the frame synchronization circuit with priority implements mis-framing in the backward protection state.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of Industrial Application The present invention is applied to a frame synchronization device using a time division multiplex transmission system.

0002

2. Description of the Related Art Conventionally, a frame synchronization device has a frame counter for an input signal to be synchronized, and a frame synchronization circuit operates this counter based on the result of frame pattern matching to determine frame timing. It had been realized.

0003

[Problems to be Solved by the Invention] However, in such a conventional frame synchronization device, there is only one frame counter, and when synchronization is achieved with a pseudo frame pattern during hunting, the frame in the input signal after one frame time is Since a pattern is searched and a frame pattern is not detected, hunting is restarted from that point on, which has the disadvantage that the synchronization recovery time is relatively long.

The present invention solves the above-mentioned drawbacks, and provides a frame synchronization device that can prevent the frame counter from idling for a long period of one frame even when erroneously synchronizing with a pseudo frame pattern, and can shorten the time required to restore synchronization. The purpose is to provide.

[0005]

[Means for Solving the Problems] The present invention provides a frame synchronization device comprising a frame synchronization circuit including a frame counter that detects a frame synchronization pattern in an input signal and outputs a synchronization state signal when synchronization is established. , a plurality of the frame synchronization circuits are provided, and each of the frame counters has means for outputting a frame phase signal when detecting a frame synchronization pattern, and when priority is given by an input synchronization detection priority signal, the frame counter remains in the synchronization detection state. and when this priority is not given, the synchronization detection state is canceled and the frame synchronization pattern is detected by shifting one bit. When it is detected that a frame synchronization pattern has been detected in the phase, the frame counter that is given the above-mentioned priority based on a predetermined priority control rule is made to continue the synchronization detection operation in the detected frame phase, and the other frame counters are Hunting is started again from a state shifted by one bit from the phase, and if the frame synchronization circuit with the above-mentioned priority misframes in the backward protection state, at that point the above-mentioned priority is given based on the above-mentioned predetermined priority control rule. A synchronization detection priority control circuit that outputs the synchronization detection priority signal to be passed to other frame synchronization circuits that are in the synchronization detection state, and an OR circuit that ORs the output synchronization state signals of each of the frame counters. That's true.

Further, in the present invention, the predetermined priority control rule may be a rule that gives priority to each frame synchronization circuit in ascending order of its unique serial number.

Furthermore, in the present invention, each of the frame counters is configured to perform one cycle based on the phase of the detected frame synchronization pattern.
It can include means for counting over a frame length.

[0008]

[Operation] A plurality of frame synchronization circuits are provided. Each frame counter outputs a frame phase signal when detecting a frame synchronization pattern, and when priority is given by the input synchronization detection priority signal, it continues to be in the synchronization detection state, and when this priority is not given, it remains in the synchronization detection state. The frame synchronization pattern is detected by canceling and shifting by 1 bit. The synchronization detection priority control circuit is a frame counter that gives priority based on a predetermined priority control rule when it detects that a frame synchronization pattern is detected at the same frame phase from a hunting state based on the frame phase signal of each frame counter. The synchronization detection operation continues with the detected frame phase, and the other frame counters start hunting again from a state shifted by 1 bit from that phase. If so, a synchronization detection priority signal is output to the corresponding frame counter to cause the priority to be passed to another frame synchronization circuit that is in the synchronization detection state at that time based on the predetermined priority control rule. The logical sum circuit logically sums the output synchronization state signals of each frame counter and outputs the logical sum.

As described above, even in the case of erroneous synchronization with a pseudo frame pattern, it is possible to prevent the frame counter from running idly for a long period of one frame, and the time required to restore synchronization can be shortened.

0010

Embodiments Examples of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a frame synchronization device according to an embodiment of the present invention.

In FIG. 1, the frame synchronization device includes a frame synchronization circuit including a frame counter that detects a frame synchronization pattern in an input signal and outputs a synchronization state signal when synchronization is established.

A plurality of the frame synchronization circuits (in this case, frame synchronization circuits 2 and 3) are provided, and each frame counter 4 and 5 includes a means for outputting a frame phase signal when detecting a frame synchronization pattern, and a means for inputting a synchronization detection signal. When priority is given by the priority signal, the synchronization detection state continues as it is, and when this priority is not given, the synchronization detection state is canceled, and the frame synchronization pattern is detected by shifting one bit. A frame counter that gives the above priority based on a predetermined priority control rule when detecting a frame synchronization pattern with the same frame phase from a hunting state based on the frame phase signals 7 and 8 of the counters 4 and 5. The synchronization detection operation continues with the detected frame phase, and the other frame counters start hunting again from a state shifted by 1 bit from that phase, and if the frame synchronization circuit with priority above misframes in the backward protection state. a synchronization detection priority control circuit 6 that outputs the synchronization detection priority signal that causes the priority to be passed to another frame synchronization circuit that is in the synchronization detection state at that time based on the predetermined priority control rule; The present invention is provided with an OR circuit 13 which calculates the OR of the output synchronization state signals 11 and 12 of each frame counter 4 and 5.

The above-mentioned predetermined priority control rule is a rule that gives priority to the frame synchronization circuits 2 and 3 in ascending order of their unique serial numbers.

Furthermore, each of the frame counters 4 and 5 includes means for counting one frame or longer period based on the phase of the detected frame synchronization pattern.

The operation of the frame synchronization device having such a configuration will be explained. FIG. 2 is a time chart of signal waveforms of each part of the frame synchronization device of the present invention.

In FIGS. 1 and 2, an input signal 1 is input to two frame synchronization circuits 2 and 3 having the same function, and frame counters 4 and 5 of each frame synchronization circuit 2 and 3 have their own unique functions. It is possible to operate in phase. The frame counters 4 and 5 recognize the pseudo frame pattern 1a of the input signal 1 shown in FIG. 2 as a frame pattern, and frame phase signals 7 (frame pulses 7a),
8 (frame pulse 8a) is output to the outside.

The synchronization detection priority control circuit 6 inputs the frame phase signal 7 of the frame counter 4. For example, suppose that there is a rule in which a frame synchronization circuit with a small number simply has priority to declare synchronization first. , the frame synchronization circuit 2 outputs the frame pulse 7a to the backward protection counter, enters the backward protection state, and starts counting one frame for a long period of time.

Similarly, the synchronization detection priority control circuit 6 inputs the frame phase signal 8, and in order to give priority to the frame synchronization circuit 2, it gives a synchronization detection priority signal 10, and the frame counter 5 inputs the frame phase signal 8. It is released and shifted by 1 bit, and the hunting state is entered again. When a normal frame pattern 1b is input after the pseudo frame pattern, the frame synchronization circuit 2 ignores this frame pattern since it has already captured the frame pattern, and the frame synchronization circuit 3 synchronizes with this frame pattern 1b. The frame counter 5 outputs a frame phase signal 8 (frame pattern 8b) and starts counting for a long period of one frame.

Next, the frame synchronization circuit 2 cannot detect frame data from the input signal in phase 22b when the frame counter 4 counts up, and enters a hunting state. When a normal frame pattern 1c is input,
Since the frame counter 5 is synchronized with this phase, it maintains the backward protection state, outputs the frame pulse 24c to the backward protection circuit, and outputs the frame pulse 8b as the frame phase signal 8.

The frame synchronization circuit 3, which has received the frame pattern satisfying the number of backward protection stages, enters a synchronization established state,
A synchronization state signal 12 is output. The OR circuit 13 takes the OR of the output synchronization state signals 11 and 12 of the frame synchronization circuits 2 and 3 and outputs the result. The frame counter 4 continuously performs frame pattern hunting in a phase different from that of the frame counter 5, but the synchronization detection priority control circuit 6 uses a frame synchronization circuit to prevent synchronization with the same frame pattern as the frame counter 5. For 2,
The synchronization detection priority signal 9 is sent and controlled.

As mentioned above, in this embodiment, the case where there are two frame synchronization circuits has been described, but three or more may be used.

[0022]

[Effects of the Invention] As explained above, the present invention can prevent the frame counter from idling for a long period of one frame even in the case of erroneous synchronization with a pseudo frame pattern, and has the excellent effect of shortening the synchronization recovery time. be.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a frame synchronization device according to an embodiment of the present invention.

FIG. 2 is a time chart of signal waveforms of each part of the frame synchronization device of the present invention.

[Explanation of symbols]

1 Input signal 2, 3 Frame synchronization circuit 4, 5 Frame counter 6 Synchronization detection priority control circuit 7, 8 Frame phase signal 9, 10 Synchronization detection priority signal 11, 12 Synchronization status signal 13 Logical sum circuit

Claims (3)

[Claims] 1. A frame synchronization device comprising a frame synchronization circuit including a frame counter that detects a frame synchronization pattern with respect to an input signal and outputs a synchronization state signal when synchronization is established, wherein the frame synchronization circuit includes a plurality of frame synchronization circuits. Each of the frame counters has a means for outputting a frame phase signal when detecting a frame synchronization pattern, and a means for outputting a frame phase signal when a frame synchronization pattern is detected, and a means for continuing the synchronization detection state when priority is given by the input synchronization detection priority signal. and a means for detecting a frame synchronization pattern by canceling the synchronization detection state and shifting one bit when the synchronization detection state cannot be detected, and detecting a frame synchronization pattern at the same frame phase from the hunting state based on the frame phase signal of each of the frame counters. When this is detected, the frame counter that is given priority based on a predetermined priority control rule is made to continue synchronization detection operation at the detected frame phase, and the other frame counters are made to continue the synchronization detection operation from a state shifted by 1 bit from that phase. If hunting is started again and the frame synchronization circuit with the above-mentioned priority misframes in the backward protection state, at that point the other frame synchronization circuit with the above-mentioned priority is in the synchronization detection state based on the above-described predetermined priority control rule. Frame synchronization characterized by comprising: a synchronization detection priority control circuit that outputs the synchronization detection priority signal to be passed to the frame synchronization circuit; and an OR circuit that ORs output synchronization state signals of each of the frame counters. Device. 2. The frame synchronization device according to claim 1, wherein the predetermined priority control rule is a rule that gives priority to each frame synchronization circuit in ascending order of its unique serial number. 3. The frame synchronization device according to claim 1, wherein each of the frame counters includes means for counting one frame or more for a long time based on the phase of the detected frame synchronization pattern.