JPS60213149A - Synchronizing circuit - Google Patents

Abstract

PURPOSE:To reduce the probability falling into false synchronization and to shorten a synchronization reset time by forming two circuits for comparing and detecting the polarity of a frame marker bit and data to compare continuously and detect two bits of data. CONSTITUTION:Coincidence/inconsistency of the polarity of a frame marker bit with that of a data bit is detected through a received frame synchronization counter 1 and a comparator/detector 3. On the other hand, the 2nd comparator/ detector 7 having the similar function to that of the 1st one 3 is also connected. The 2nd comparator/detector 7 detects the coindidence/inconsistency of the polarity if received data obtained after one bit from the received data compared by the 1st comparator/detector 3 with that of said frame marker bit and a latch circuit 8 latches the detected result. When the 1st and 2nd comparators/detectors 3, 7 generate inconsistent outputs, a shift pulse generating circuit 9 outputs a shift instruction of two bits to the reveiving counter 1 to shorten the time up to synchronization.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronization circuit for synchronizing frames between a transmitter and a receiver used in digital communications.

Since the conventional synchronization circuit has only one comparison detection circuit that compares and detects the polarity of the frame markup/soto generated by the received frame counter and the polarity of data, it is only possible to compare and detect each bit.

For this reason, conventional synchronization circuits have the disadvantage that there is a high probability of false coincidence in the frame synchronization detection process, that false synchronization is likely to occur, and that a long time is required for the synchronization recovery process.

An object of the present invention is to provide a synchronization circuit that can reduce the false coincidence probability and shorten the synchronization recovery time.

The synchronization circuit of the present invention is a frame synchronization circuit used in digital communication, and includes a reception frame synchronization counter that generates a pulse indicating the polarity of a frame marker at a predetermined frame marker bit point, and a reception frame synchronization counter that generates a pulse that indicates the polarity of a frame marker at a predetermined frame marker bit point. a first comparison detector that compares and detects a match φ mismatch between the polarity of the received data and the polarity of the frame marker pulse generated by the received frame synchronization counter; and the received data compared by the first comparison detector. a second comparison detector that compares and detects a coincidence or mismatch between the polarity of the received data 1 bit later than the polarity of the frame marker pulse generated by the received frame synchronization counter; and the first comparison detector; a synchronization protection counter that counts the coincidence output and mismatch output of the detector and outputs a synchronization establishment signal and a synchronization loss signal; means for storing the mismatch output of the second comparison detector; and a means for storing the mismatch output of the second comparison detector; 1
means for responsively outputting a discrepancy output of the comparison detector;
It is characterized by comprising means for generating a control signal for the reception counter in response to the output of the storage means, the output of the protection counter, and the non-coincidence output from the first comparison detector.

Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a conventional synchronous circuit.

In FIG. 1, a clock signal 101 is input to a received frame synchronization counter 1, and the received frame counter 1 is driven. The digital multiplexed data signal 102 sent from the transmitting side is input to the flip-flop 2 and retimed by the clock signal 101, and the output data signal 104 is sent to the frame beam.) Comparison and detection circuit 3
is input.

In the frame bit comparison circuit 3, the frame marker bit signal 103 given from the reception frame synchronization counter 1 and the data signal 104 match.

A mismatch is determined. In the case of a match, the frame bit comparison circuit 3 outputs a frame bit match pulse signal 105, and in the case of a mismatch, a frame bit mismatch pulse signal 106 is output. These frame bit match/mismatch pulse signals 105 and 106 are input to the frame protection counter 4 (for example, a conflict counter). The frame protection counter 4 is a circuit that determines the frame bit synchronization state, and has a protection function against transmission path errors for the operation of the frame synchronization circuit based on the frame coincidence pulse signal 105 and frame bit mismatch pulse signal 106 of the input signal. , outputs a synchronization determination signal 107 depending on whether it is in a synchronized state or out of synchronization.

The 1-bit shift pulse generation circuit 5 knows the synchronization state from the synchronization judgment signal 107 sent from the frame protection counter 4, and when the frame bit mismatch pulse signal 106 is generated in the out-of-synchronization state and input to this circuit. Only at 1 beat, the shift pulse signal 108 is output. 1
The bit shift pulse signal 108 is input to the reception counter 1, and the reception counter 1 prevents the reception counter 1 from counting up for one bit, resulting in a one-bit hunting operation.

By repeating the above process several times, the synchronization recovery process is completed. However, the above-mentioned conventional circuit has the above-mentioned drawbacks.

FIG. 2 is a block diagram showing one embodiment of the present invention. In FIG. 2, reception counter 1. Flip Flop 2.
1st frame bit comparison detection circuit 3. Frame protection counter 4 operates in the same manner as the conventional configuration shown in FIG. The portion within the broken line in FIG. 2 is a newly added portion according to the present invention.

Reception counter circuit 1 is driven by clock signal 101#. A digital multiplex data signal 102 sent from the transmitting side is input to the flip-flop 6 and is retimed by a clock signal 101.

Next, the operation of the parts added according to the present invention will be explained. This portion is shown within the dashed line 100 in FIG.
This is the part that compares and detects the data one bit after the data bit comparatively detected by the comparison detection circuit 3 and the frame marker beat signal 103 generated by the receiving side counter circuit 1. That is, the retimed data signal 109
is input to the second frame bit comparison circuit 7, where a match or mismatch between the frame marker bit signal 103 indicated by the receiving side counter circuit 1 and the data signal 109 is compared and detected. This comparison detection is one bit later in time than the data signal 104 being compared by the first frame bit comparison detection circuit 3, and one bit hunting by the first frame bit comparison detection circuit 3 is completed. This is the bit that is newly compared and detected after the The frame bit mismatch pulse signal 110 is input to the latch circuit 8 only when the second frame bit comparison circuit 7 determines that there is a mismatch. Latch circuit 8 consists of latch circuit 81 and gate 8
2 and a flip-flop 83, it generates a 2-bit shift signal 111 as soon as the frame bit mismatch pulse signal 110 from the second frame bit comparison circuit 7 is no longer input, and until the latch reset signal 112 is input. The I shift signal 111 continues to be output to the shift pulse generation circuit 9.

The shift pulse generation circuit 9 includes a frame protection counter 4.
from the synchronization determination signal 107 and the frame bit mismatch pulse signal 106 from the first frame bit comparison detection circuit 3.
is input, and a 2-bit 9-bit shift pulse signal 111 is input from another 9-bit circuit 8. As a result, when the 2-bit shift command signal 111 is input in the out-of-synchronization state, the 2-bit shift pulse signal 113 is output from the shift pulse generation circuit 9. In addition, the 2-bit shift signal 111
In particular, when only the frame bit mismatch pulse signal 106 is input without inputting the frame bit mismatch pulse signal 106, the 1-bit shift pulse signal 11
3 is output. At the same time as the shift pulse signal 113 is output, a latch reset signal 112 is generated, and the latch circuit 8 is reset.

Next, the principle of the shift operation will be explained with reference to FIG. Now, at the position Fl, when the first frame period comparison circuit compares the frame marker bit F1 generated by the reception frame synchronization counter with the reception data F1, a frame coincidence pulse is generated. At this time, in the second frame bit comparison circuit, the frame marker bit is compared with F1+1 of the received data, and when a frame mismatch pulse is generated, until the first comparison circuit number is detected. be remembered.

Next, when a mismatch is detected in the first frame bit comparison circuit at the position F2, the position F2+1 is already recognized as not a frame bit in the second frame bit comparison circuit in the previous frame. Therefore, a 2-bit shift command is issued and shifted.

If, as in the present invention, the second frame bee,
If the l-comparison circuit is not provided, when the frame marker F2 and the received data F2+1 match, the frame search will be temporarily stopped at this point, and as a result, only one bit will be shifted.

In addition, in the first frame bit comparison circuit, 11
Needless to say, the search is performed continuously until the polarity of the frame marker matches the polarity of the received data.

In the circuit shown in FIG. 2, the output of the latch circuit 81 and the flip-flop 83 is used to operate the rear 9, but as shown in FIG. It is also possible to reset using the frame bit.

As described above, in the synchronization circuit of the present invention, since the search method for frame 7-mold,) detects seven consecutive comparisons of data 2b y), the probability of falling into pseudo-synchronization is extremely low, and the synchronization recovery time is extremely low. This has the effect of shortening the time.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a conventional synchronous circuit, Figs. 2 and 3 are block diagrams and time charts showing one embodiment of the present invention, and Fig. 4 shows another embodiment of the present invention. It is a circuit diagram. In Figures 1, 2, and 4, 1...
・Reception counter circuit, 2...Flip-flop, 3...Frame bit comparison circuit, 4...
...Frame protection counter circuit, 5...1 bit shift pulse generation circuit, 6...FIJ, flop, 7...2nd frame bit drop comparison circuit, 8...Latch circuit, 9...Shift pulse generation circuit.

Claims (1)

[Claims] In a frame synchronization circuit used in digital communication, a reception frame synchronization counter that generates a pulse that indicates the polarity of a frame marker at a predetermined point in the frame marker window;
) A first comparison detector that compares and detects coincidence or mismatch between the polarity of the received data at the time of generation and the polarity of the frame marker pulse generated by the reception frame synchronization counter; a second comparison detector for comparing and detecting a mismatch between the polarity of the received data one bit later than the received data and the polarity of the frame marker pulse generated by the received frame synchronization counter;
a synchronization protection counter that counts the coincidence output and mismatch output of the second comparison detector and outputs a synchronization establishment signal and a synchronization loss signal; means for storing the mismatch output of the second comparison detector; and contents of the storage means. means for outputting in response to a mismatch output from said first comparison detector; and means for outputting said reception counter in response to an output of said storage means, an output of said protection counter, and a mismatch output from said first comparison detector. A synchronous circuit comprising means for generating a control signal.