JPH01120924A - Frame synchronizing circuit - Google Patents

Abstract

PURPOSE:To decrease the time from the asynchronous state till the establishment of synchronization by fixing no frame number for detecting its coincidence at zero but predicting the frame number at which a frame flag synchronizing signal is sent out and comparing the input frame number with the predicted frame number. CONSTITUTION:A frame flag detection circuit 4 compares a frame flag in a reception signal with a built-in frame flag and when they are dissident, the bit is shifted by one by one, the shift is stopped when they are coincident and a frame flag synchronizing signal is sent to a frame number latch circuit 51 and a frame number prediction circuit 52 when M-time of coincidence takes place consecutively. Then the predicted frame number read from a ROM and the frame number after one frame detected actually are compared and when they are coincident, a frame number coincident signal is fed from the frame number prediction circuit 52 to a synchronizing protection circuit 53. The synchronizing protection circuit 53 gives a synchronizing establishment signal to the reception circuit.

Description

[Detailed Description of the Invention] [Summary] For example, regarding a frame synchronization circuit used in a station reception section when performing data communication between stations using a loop type LAN, the present invention relates to a frame synchronization circuit that is used in a station receiving section when performing data communication between stations using a loop type LAN. In a data communication system that performs data communication between stations using a signal consisting of a frame including a frame flag and a frame number, the frame flag is detected when the frame flag in the received signal is detected M times consecutively. A frame flag detection circuit that sends out a frame flag synchronization signal and sends out a frame flag synchronization invalid signal when the frame flag cannot be detected N times in a row after sending out the frame flag synchronization signal; When a synchronization signal is input, the frame number in the corresponding received signal is stored and the next frame number is predicted.

When the frame number matches the detected frame number, a frame number match signal is sent out, but when the frame flag synchronization invalidation signal is input, the stored frame number and Local area
The present invention relates to a frame synchronization circuit used in a station receiving section when performing data communication between stations using a network.

First, let us assume that data communication is carried out using a loop type LAN system consisting of nine mask stations and stations 1 to 3, for example, as shown in the explanatory diagram of the loop type LAN system in FIG.

The master station receives a 1-byte frame flag, as shown in ■ and ■ in the example frame configuration diagram in Figure 4.
A frame consisting of a frame header containing a frame number, a 6-byte destination address, a source address, etc., and an n-byte slot into which data is inserted is sent out to the transmission path at regular intervals, and the frame is sent around the transmission path once. Since the signals deviate from the above-mentioned constant time interval due to variations in the delay time between the transmission path and the station, they are updated so that they become constant time intervals.

Incidentally, as shown in FIG. 4--, one multiframe is made up of, for example, 30 frames, and the 1-byte frame flag has a pattern that makes it difficult to cause pseudo synchronization, and is inverted every frame.

Next, station 1 establishes frame synchronization using the frame flag and frame number in the received signal, and then
Send to station 2.

Station 2 establishes frame synchronization in the same way as station 1, and then sends it to station 3. After frame synchronization of all stations is established in this way, data is correctly transmitted and received at each station.

Therefore, it is necessary to improve transmission efficiency by shortening the time from the state of being out of synchronization to the establishment of synchronization.

[Conventional technology]

FIG. 5 is a block diagram of a conventional example, and FIG. 6 is an explanatory diagram of the operation of FIG. 5.

First, when a signal having the frame structure shown in FIG. The correct frame flag is stored here, and the patterns are compared with a comparator (not shown). If they do not match, the received signal is shifted one bit at a time until they match, and when they match, the shifting is stopped.

Furthermore, when the frame flag synchronization can be detected N times in succession, a frame flag synchronization signal of 2, for example, L level is sent to the frame number O detection circuit and the reception circuit 3 to establish frame flag synchronization.

Note that this frame flag synchronization signal is at L level while frame flag synchronization is being established.

Next, in the frame number O detection circuit 2, the AND of FIG.
Gate 21 is turned on and a portion of the received signal is applied to an internal frame number 0 comparator (not shown). Since the pattern corresponding to frame number O is stored here,
When they do not match, the received signals are shifted until they match, and when they match, the shifting is stopped. For example, when frame number 0 is detected a predetermined number of times in succession, a frame number O detection signal is sent to the receiving circuit 3.

Therefore, in the receiving circuit 3, both the frame flag synchronization signal and the frame number 0 detection signal are L as shown in FIG. 6(b).
When it is at level, the NOR gate 32 outputs 1 (because the level is output and the AND gate 31 is turned on.

The input received signal passes through this AND gate and enters the signal processing section (not shown), and inserts the data to be transmitted into the slot having the designated frame number, or inserts the data inserted into the slot. data is extracted and data is sent and received between stations.

[Problem that the invention seeks to solve]

Now, after frame flag synchronization is established.

Since synchronization of frame number O is established by continuously detecting frame number 0 a predetermined number of times, for example, in the case of the configuration shown in Figure 4-0, when frame flag synchronization is established in the first frame, it is 29 frames. There is a problem that the frame with frame number 0 will not be input to the frame number 0 detection circuit until later, and it will take time to establish synchronization from an out-of-synchronization state.

[Means for solving problems]

FIG. 1 shows a block diagram of the principle of the present invention.

In the figure, 4 indicates that a frame flag synchronization signal is sent when the frame flag in the received signal is detected M times in a row, and when the frame flag cannot be detected 8 times in a row after the frame flag synchronization signal is sent. 5 is a frame flag detection circuit that sends out a frame flag synchronization invalidation signal;
When the frame flag synchronization signal is input from the frame flag detection circuit, the frame number in the corresponding received signal is stored to predict the next frame number, and when it matches the detected frame number, a frame number match signal is sent out. [Operation] When the frame flag synchronization invalidation signal is input, the present invention compares the received signal and the built-in frame flag in the frame flag detection circuit 4, and when they match M times in a row,
A frame flag synchronization signal is sent from here and applied to the frame number detection means 5.

The frame number detection means 5 stores the corresponding frame number and predicts the next frame number, and when the actually detected frame number and the predicted frame number match, a receiving circuit (not shown) receives a frame number matching signal of a predetermined level. Send to,
The receiving circuit processes the input received signal.

However, if the frame flag cannot be detected eight times in a row after sending out the frame flag synchronization signal, synchronization is lost, and a frame flag synchronization invalid signal is sent from the frame flag detection circuit 4 to the frame number detection means 5 and stored. The predicted frame number and predicted frame number are reset and returned to the initial state.

That is, to check whether the frame numbers match, instead of fixing the frame number to 0, the frame number next to the frame number when the frame flag synchronization signal was sent is predicted and compared with the input frame number. This shortens the time from an out-of-synchronization state to establishment of synchronization.

〔Example〕

FIG. 2 shows a block diagram of an embodiment of the invention.

Note that the frame number latch circuit 51. Frame number prediction circuit 52. A synchronization protection circuit 53 represents a component of the frame number detection means 5. The operation of the figure will be explained below.

First, the frame flag detection circuit 4 compares the frame flag in the received signal with the built-in frame flag, and if they do not match, it is shifted one bit at a time until they match, and when they match, it stops shifting, and after that it matches M consecutive times. For example, to establish synchronization for frame flags, a frame flag synchronization signal is sent to the frame number latch circuit 51 and the frame number prediction circuit 52.
Since the frame number is sent out at the same time, the frame number at that time is latched by the frame number launch circuit.

On the other hand, the frame number prediction circuit 52 determines that the frame number (hereinafter referred to as the predicted frame number) one frame after the frame number launched by the frame number latch circuit 51 (hereinafter referred to as the latch frame number) is the latch frame number. The address is written in a built-in ROM (not shown).

Therefore, the predicted frame number read from the ROM is compared with the actually detected frame number one frame later, and if they match, a frame number matching signal is applied from the frame number prediction circuit 52 to the synchronization protection circuit 53. .

The synchronization protection circuit 53 assumes that synchronization has been established and applies a synchronization establishment signal to the receiving circuit, which causes the duplication circuit to perform reception processing on the received signal.

That is, the time from the state of being out of synchronization to the establishment of synchronization is shortened.

〔Effect of the invention〕

As described above in detail, the present invention has the effect of shortening the time from synchronization loss to synchronization establishment. This improves transmission efficiency.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, Fig. 3 is an explanatory diagram of a loop type LAN system, Fig. 4 is an example of a frame configuration diagram, and Fig. 5 is a conventional Example block diagram FIG. 6 is an explanatory diagram of the operation of FIG. 5. In the figure, 4 is a frame flag detection circuit; Figure * 5 (2) Kaya 5 G1's 1 Ka 41 Squeezed Moon C] Kaya et al.

Claims (1)

[Claims] In a data communication system that performs data communication between stations using a signal consisting of a frame including a frame flag and a frame number, a frame flag in a received signal is detected consecutively M times (M is a positive integer). A frame flag detection circuit (4) that sends out a frame flag synchronization signal when the frame flag synchronization signal is sent out, and sends out a frame flag synchronization invalidation signal when the frame flag cannot be detected N times (N is a positive integer) consecutively after sending out the frame flag synchronization signal. ), and when the frame flag synchronization signal is input from the frame flag detection circuit, the frame number in the corresponding received signal is stored and the next frame number is predicted, and when it matches the detected frame number, a frame number match signal is generated. A frame synchronization circuit characterized in that it has frame number detection means (5) for resetting the stored frame number and predicted frame number when the frame flag synchronization invalidation signal is input.