JPH05136779A - Synchronization detection circuit - Google Patents

Abstract

PURPOSE:To realize high speed synchronization by operating a receiver side code generator in a timing when the state of a receiver side shift register reproducing the state of a sender side code generator is in matching with the state of a fixed pattern register. CONSTITUTION:The circuit is provided with a receiver side shift register 3 monitoring and reproducing the state of a shift register of a sender side code generator 1 and with a fixed pattern register 4 latching the state of the sender side shift register as a fixed pattern at a point of time. A coincident detector 5 compares a state of the receiver side shift register 3 with a state of the fixed pattern register 4 and sends a load signal on the detection of the coincidence. Then a clock is supplied to the receiver side code generator 6 from the clock control section 7 based on the load signal and a fixed pattern is loaded from the fixed pattern register 4. Thus, high speed synchronization in the synchronization communication system with a long code series and high speed signal series is realized with simple circuit configuration.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sync detecting circuit, and more particularly to a sync communication system using a code sequence having a long code length and a high speed.

[0002]

2. Description of the Related Art There are a wide variety of fields in which synchronization detection is required, and conventionally, methods for detecting the synchronization have been (1) correlation detection by a sliding correlator method, and (2) correlation detection by a digital matched filter method.

The sliding correlator method (1) is a method of shifting the local code sequence by 1 bit by using a 1-bit correlator to obtain the correlation with the received code sequence every time. The synchronous phase can be obtained by calculating the correlation with respect to the number of bits.

The basic concept of the digital matched filter method of (2) is the same as that of (1), but one cycle of a local code sequence is prepared inside the receiver and the received code sequence is received. Each time it is performed, the correlation is obtained over one cycle. When this method is used, if only one code sequence length is input, the correlation for all the phases is obtained, and thereby the synchronous phase can be detected.

[0005]

However, the above-mentioned conventional synchronization detection method has the following problems. (A) Sliding correlator method The circuit configuration or software algorithm configuration is very simple because the correlation is obtained bit by bit, but since synchronization detection requires an extremely long time, the length of the synchronization detection pattern is long. Will increase. Moreover, high-speed synchronization detection cannot be performed.

(B) Digital matched filter system Since one code sequence length is provided inside the receiver, the hardware scale increases. Further, since the correlation of one code sequence length is obtained for each 1-bit input, the signal speed is greatly limited by the calculation time.

The present invention has been made in order to solve the problems in the conventional example as described above, and a synchronization detection circuit capable of realizing high-speed synchronization in a problem communication system of a long code sequence and a high-speed code sequence. The purpose is to provide.

[0008]

In order to achieve the above object, a synchronization detecting circuit according to the present invention includes a receiving side shift register for monitoring the shift register state of a transmitting side code generator and a transmitting side shift register. Based on the load signal, a fixed pattern register that holds the state at the time point as a fixed pattern in advance, a match detector that compares the states of the receiving shift register and the fixed pattern register and sends a load signal when a match is detected, A controlled clock control unit, a reception side code generator to which a clock is supplied from the clock control unit based on the load signal and a fixed pattern is loaded from the fixed pattern register, and reception by the reception side shift register A correlator for obtaining a correlation value between the input and the code sequence output from the receiving side code generator; Based on the comparison between the correlation value and the threshold is characterized in that a comparator for controlling the clock of the clock control unit.

[0009]

In the present invention, the receiving side shift register which reproduces the state of the transmitting side code generator by the coincidence detector compares with the fixed pattern having the fixed pattern register, and at the coincident timing, the receiving side code generator and the clock. High-speed synchronization acquisition is realized by operating the control unit.

[0010]

The present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention. As shown in FIG. 1, the synchronization detection circuit according to this embodiment includes a reception side shift register 3 for monitoring the shift register state of a transmission side code generator 1 composed of n stages of shift registers, and a certain time point of the transmission side shift register 1. A fixed pattern register 4 which holds the state in step 1 as a fixed pattern in advance, a coincidence detector 5 which compares the states of the reception side shift register 3 and the fixed pattern register 4 and sends a load signal when a coincidence is detected, and the load signal A clock control unit 7 controlled based on the load signal, a receiving side code generator 6 to which a clock is supplied from the clock control unit 7 based on the load signal and a fixed pattern is loaded from the fixed pattern register 4. The correlation value between the reception input by the reception side shift register 3 and the code sequence output from the reception side code generator 6 is obtained. It comprises a half adder 8 and correlator comprising an integrator 9, and a comparator 10 for controlling the clock of the clock control unit 7 based on a comparison between the correlation value and the threshold. Note that 2 is noise that causes a line error.

In this embodiment, it is assumed that the code sequence is a shift register sequence as shown by the transmitter code generator 1 in FIG. In this embodiment, instead of obtaining the correlation over one cycle of the code sequence, the state of the shift register that generates the transmission side code sequence from the received input is monitored, and the initial value of the transmission side code generator 1 (a _{1 in the} figure). , A ₂ , ... A _n ) and the state of the shift register 3 on the receiving side are compared. If the bit error on the line is zero, the state of the shift register 3 on the receiving side should always be the initial state of the code generator 1 on the transmitting side during one cycle of the code sequence. If the initial values a ₁ , a ₂ , ... A _n are loaded into the code generator 6 shown in FIG. 1 and a clock is input, the receiving side can generate a code sequence synchronized with the receiving input, and the synchronization is achieved. Established.

The problem here is that synchronization cannot be established correctly when there is a bit error in the line. The probability of erroneous synchronization establishment in this case will be described below. The following two factors can be considered as the factors that make an error in establishing synchronization. A. If there is no error, the receiving side coincidence detector 5 does not operate due to a bit error where the initial value appears in the receiving side shift register 3. This is called a lock miss. B. Although it is not originally the initial value, the pattern becomes the same as the initial value due to a bit error, and the coincidence detector 5 operates. This is called false lock.

Below, it is assumed that the bit error of the line is a random error, the bit error probability is P, and the number of stages of the shift register is n. (A) Lock miss rate P _m This occurs when n bits in the shift register are incorrect by 1 bit or more.

[0014]

[Equation 1]

(B) False lock rate P _f This occurs when the code distance is R with _respect to the initial state and the k bits are just wrong.

[0016]

[Equation 2]

Expressions are equivalent expressions, and Perr =
The synchronization establishment error probability is obtained by 1- (1-P) ⁿ .
Now, the number n of shift registers is 9 and the bit error rate P is 1.
^Assuming 0 ^-4 (generally, this degree is guaranteed), P
err = 9 × 10 ⁻⁴ , which is an error rate of about once in 1000 times. Further, even if synchronization is established with an incorrect phase, the error state is determined by the correlator including the half adder 8 and the integrator 9 in FIG. 1 and the comparator 10 that compares the correlation value with the threshold value. As a result, it is possible to reset the receiving system and perform synchronization detection again.

[0018]

As described above, according to the present invention, the state of the shift register of the transmitting side code generator is reproduced on the receiving side, and when a certain fixed pattern (for example, initial value) is obtained, the local code sequence is By operating from the pattern, it is possible to realize high-speed synchronization in a synchronous communication system of a long code sequence and a high-speed signal sequence with an extremely simple circuit configuration.

[Brief description of drawings]

FIG. 1 is a block diagram of a synchronization detection circuit according to an embodiment of the present invention.

[Explanation of symbols]

 1 Transmitter-side code generator 2 Noise 3 Receiver-side shift register 4 Fixed pattern register 5 Match detector 6 Receiver-side code generator 7 Clock controller 8 Half adder 9 Integrator 10 Comparator

Claims (1)

[Claims] 1. A receiving side shift register for monitoring the state of a shift register of a transmitting side code generator, a fixed pattern register for holding a state of the transmitting side shift register at a certain point in time as a fixed pattern, and the receiving side shift register. And the state of the fixed pattern register are compared to each other to output a load signal when a match is detected, a clock control unit controlled based on the load signal, and a clock from the clock control unit based on the load signal. Correlation for obtaining the correlation value between the receiving side code generator supplied with the fixed pattern from the fixed pattern register and the receiving input by the receiving side shift register and the code sequence output from the receiving side code generator The clock of the clock control unit is controlled based on the comparison between the correlation value and the threshold value. A synchronization detection circuit comprising: