JPH0437335A - Multi-frame synchronization restoration system - Google Patents

Abstract

PURPOSE:To reduce the synchronization recovery time by receiving a result of a comparator means, selecting a clock signal in the case of dissidence, selecting an output signal of a timing generating means in the case of coincidence and giving the signal to a frame pattern generating means. CONSTITUTION:When coincidence is taken by a comparator means 11, a selection means 13 selects a multi-frame timing signal mf between a clock signal CK and the signal mf. In the case of dissidence, an output signal 110 representing dissidence is fed to the selection means 13, which selects the clock signal CK, and it is inputted to a multi-frame pattern generating means 14. Every time a single is inputted, the output phase of the multi-frame pattern is advanced by the means 14 and a relevant output is outputted to the comparator means 11. Thus, the output of the bit signal of the pattern is advanced sequentially, and when the coincident signal is outputted by the comparator means 11, the selection means 13 is selected to switch the clock signal CK into the signal mf, and the similar operation to the case with the coincidence of detection is implemented by the comparator means 11.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] This invention relates to a multi-frame synchronization recovery method for a communication device that transmits a signal with a multi-frame configuration including multi-frame patterns discretely distributed on frames at predetermined frame intervals. The purpose is to provide a multi-frame synchronization recovery method that can be shortened.

Multi-frame timing generation means that counts clock signals extracted from input signals and generates an output at each generation interval of a bit signal of a synchronization pattern.

Memory holding means for storing the contents of the multi-frame signal in the input signal at the timing of output from the multi-frame timing generating means; and multi-frame pattern generating means for sequentially generating bits constituting the multi-frame pattern for each supplied signal. and.

Comparing means for comparing the output of the memory holding means and the output of the multi-frame pattern generating means; inputting the comparison result of the comparing means; selecting the above-mentioned clock signal when there is a mismatch; and outputting the multi-frame timing generating means when there is a match; and selecting means for selecting a signal and supplying the selected signal to the multi-frame pattern generating means.

frame pattern is used as a redundant signal when
Communication devices need to detect the pattern and synchronize. And pattern synchronization has become essential for processing general information or other redundant signals.

Furthermore, when receiving and synchronizing a multi-frame signal, conventional methods take time to detect the synchronization pattern because each bit is inserted discretely across multiple frames. There are drawbacks, and improvements are desired.

[Field of Industrial Application] The present invention relates to a multi-frame synchronization recovery method for a communication device that transmits signals in a multi-frame configuration including synchronization patterns discretely distributed on frames at predetermined frame intervals.

In communication devices that electrically or optically transmit digital signals, the transmitted signals are composed of general information and redundant signals. Then, the multiplexed signal is transmitted [Prior art] Fig. 4 is an example of the frame structure of a multi-frame.

FIG. 5 is a configuration diagram of a conventional example.

In FIG. 4, a multiframe for transmitting 9 time-division multiplexed digital signals is composed of a plurality of frames (also referred to as short frames).

In each frame, time slots for information to be transmitted are sequentially arranged after the first overhead bit (OHB), and n time slots are provided, and the next frame has a similar structure.

In the multi-frame configuration, a multi-frame is configured by a plurality of predetermined short frames.

In a multi-frame configuration, control information for maintenance (alarm information, check information, etc.) is distributed and allocated in advance to specific bit positions in each frame in order to transmit control information to predetermined time slot bit positions in each frame. and is transmitted at a period of one multiframe.

In order to receive information (audio, etc.) for each time slot of such a multi-frame signal, it is first necessary to detect the beginning of the frame signal, so a two-frame synchronization signal is added to the OHB of each frame. .

The frame synchronization signal has a specific bit pattern such as rl
ooIJ is used. In that case, as a method of providing a synchronization signal, a bit pattern rl is included in the OHB of each frame.
There is a method in which o01J is placed in a concentrated manner at the beginning of each frame, and a method in which each bit of the bit pattern is distributed and added one bit at a time to ○HB in each frame (four frames in this example).

1 for each frame or multiple frame interval of the latter.
A frame structure in which bits are distributed bit by bit is shown in FIG.

The method of detecting the beginning of each frame using a frame synchronization pattern as described above is a conventionally known technique.

Second, in order to accurately receive a control signal from a multi-frame signal, it is necessary to detect the first frame of the multi-frame from among consecutive frames, and for this purpose a multi-frame synchronization signal is added to the frame signal. ing. This multi-frame synchronization signal also uses a pattern consisting of a specific predetermined plurality of bits. Each bit making up the pattern is placed at a specific bit position within a specific time slot in the frame at intervals of each frame or multiple frames, and the pattern is determined in advance by detecting the bit information. If it is a specific pattern, it is determined that multiframe synchronization has been recovered, and reception processing is performed.

FIG. 4 shows an example of the multi-frame synchronization signal. In this example, it is provided at a specific bit position for each frame, and is provided at the first bit of the th time slot from the first time slot of the frame, and after that specific bit position, control bits A, B, It is assumed that C, D, etc. are set.

FIG. 5 shows a conventional configuration for restoring multiframe synchronization.

In FIG. 5, first, a received signal from a transmission line such as a coaxial cable or an optical fiber is input to an input terminal, and a clock circuit 50 extracts a clock component from the received signal to generate a clock signal. The frame synchronization circuit 51 detects frame synchronization using a known frame signal detection technique, and generates a detection signal of a frame synchronization signal (generated at the first bit of each frame).

The multi-frame timing circuit 52 is synchronized by the frame synchronization detection signal, counts clock signals, and calculates the timing when the multi-frame synchronization signal is generated (the number of clocks from the frame synchronization signal to the detection of the frame synchronization signal is known). , generates a multi-frame timing signal, and sets the received signal at that time in the memory 53. That is.

A bit signal for multiframe synchronization is extracted from the multiframe signal in the received signal. The output of the memory 53 is input to the comparison section 55.

In addition, the multi-frame timing signal is transmitted to the inhibit gate 5.
4 to the multi-frame pattern generation circuit 56. The prohibition gate 54 is controlled by the comparison result of the comparator 55, and outputs "0" to stop the prohibition function of the prohibition gate 54 when the comparison result is "match", and outputs "1" when the comparison result is "mismatch". Output and execute the prohibited function.

When the contents of the memory 53 and the output of the multi-frame pattern generation circuit 56 initially match, the output of the multi-frame timing circuit 52 passes through the inhibit gate 54 and is supplied to the multi-frame pattern generation circuit 56. When a multiframe timing signal is input, the multiframe pattern generation circuit 56 changes from a state in which it outputs a certain bit signal within a specific pattern to a state in which it outputs the next succeeding bit signal. For example, if the pattern is rio
ooJ (when 1 bit is added to each frame and a multi-frame laminate is configured with 4 frames),
When the previous output was "1" and matched with the output of the memory 53, the multi-frame timing signal passing through the inhibit gate 54 changes the state to generate an output of "0".

When a match is obtained, the comparator 55 sets the counter 57
counts up and when a discrepancy occurs, the counter 5
7 is reset. When the counter 57 receives successive matching outputs equal to the number of bits constituting the multi-frame pattern, the count reaches the number of bits of the pattern and generates an output. The output represents the state of multi-frame synchronization.

If the output from the comparator 55 does not match, the prohibition gate 54
Since the multi-frame pattern generation circuit 56 enters a prohibited state, the bit output of the pattern does not change, and the previous bit output is maintained as it is. In this way, if the output of the multi-frame pattern generation circuit 56 is held as it is, the next output signal from the primary multi-frame timing circuit 52 is generated when (n+1) clock signals after the previous output signal are counted. Then, the multi-frame signal received at that time is stored in the memory 53.

At this time, since the multi-frame synchronization signal input to the prohibition gate 54 is prohibited, it is not input to the multi-frame pattern generation circuit 56, so the bit signal of the output pattern does not change.

If a match is detected, the prohibition gate 54 will not perform prohibition control based on the coincidence output from the comparator 55, and the output of the 5th multi-frame timing circuit 52 will not be prohibited, and the multi-frame pattern generation circuit 56 will The next bit signal is output and supplied to the comparator 55.

In this way, the detection operation is performed until all the patterns of the multi-frame pattern generation circuit 56 and the multi-frame synchronization bits over multiple frames are detected (a predetermined count output is generated from the counter 57), and the multi-frame synchronization is lost. If

A similar operation is performed for synchronization recovery.

[Problems to be Solved by the Invention] In the conventional multiframe synchronization (recovery) operation described above, the multiframe synchronization signal set in the memory 53 is compared with the bit signal generated from the multiframe pattern generation circuit 56. If they match, the bits of the primary multi-frame pattern are compared. However, if the bit signal output from the multi-frame pattern generation circuit 56 and the multi-frame synchronization signal of the input signal do not match, the multi-frame timing circuit 52
Even if the next timing signal from
A comparison is made with the multi-frame synchronization signal of the input signal.

In other words, if the time interval in which multi-frame patterns exist is X seconds, then in the conventional technology, pattern comparisons are only performed at intervals of X seconds, so the comparison is performed again after stopping for X seconds due to mismatch. , if there is a mismatch again,
Furthermore, a stop for X seconds and subsequent comparison is required.

This is the worst situation in a synchronization method like this.

That is, in the state where the time for synchronization pull-in is maximum, 1 generally by the time pull-in is completed.

(Number of multi-frame distribution locations - 1) mismatch occurrences are required. Hereinafter, this number will be referred to as S.

Therefore, in the prior art, the time required for one cycle of pull-in is at least X-S seconds.

In addition, the time required for pull-in is based on the assumption that the probability of a mismatch in each comparison process is 1/2.

It takes 2X-3 seconds, which is a relatively long time.

However, in a digital communication device, restoration of synchronization is essential for signal processing, and if it takes such a long time, there is a problem that processing may be hindered depending on the conventional technology.

An object of the present invention is to provide a multi-frame synchronization recovery method that can shorten the synchronization recovery time.

[Means to solve the problem] FIG. 1 is a diagram explaining the principle of the present invention.

In FIG. 1, A shows the basic configuration, and B shows the signal waveforms of each part.

In the principle configuration of A, 10 is a memory holding means for extracting and holding multi-frame timing in an input signal;
1 is a comparison means for comparing the output of the memory holding means and the output of the multi-frame pattern generation means; 12 is a multi-frame timing generation means;

Reference numeral 13 denotes a multi-frame pattern generating means in which a multi-frame pattern is set and the output of bits constituting the pattern is sequentially switched in response to an input signal.

The present invention extracts a multi-frame pattern signal from an input signal at multi-frame timing, stores it, and compares the held signal with a pattern signal generated from a multi-frame pattern generating means. The multi-frame pattern signals are compared at the next multi-frame timing. If they do not match, input the clock signal to the output phase of the multi-frame pattern generating means to advance the pattern phase, and if it matches the held signal, the signal is This is to stop inputting the text.

[Effect] The action of A will be explained below.

The input signal IN is input to the memory holding means 10 as data. A clock signal CK extracted from the input signal IN is input to the multi-frame timing generating means 12, and the multi-frame timing signal mf is generated by frequency-dividing the clock signal CK. The memory holding means 10 stores and holds one bit of the multi-frame pattern of the input signal IN using the multi-frame timing signal mf.

The signal output 100 stored in the memory storage means 10 is
is supplied to one input of the comparison means 11.

It is compared with the pattern output of the multi-frame pattern generating means 14 supplied to the other input.

In comparison means 11, if a match is found, comparison output 1 is output.
10, a coincidence signal is given to the selection means 13, and the multi-frame timing signal mf is selected from among the clock signal CK and the multi-frame timing signal mf input to the selection means 13. In this case, the comparison means 11 is 9
In the next generated multi-frame timing signal mf.

A comparison is made between the next multi-frame signal (output of the memory holding means 10) of the input signal IN and the next pattern signal generated from the multi-frame pattern generating means 14.

In the comparison means 11, when a mismatch is detected, an output signal representing the mismatch is supplied to the selection means 13. At this time, the 1 selection means 13 selects the clock signal CK and inputs it to the multi-frame pattern generation means 14. The multi-frame pattern generating means 14 advances the output phase of the multi-frame pattern each time a signal is input, and outputs a corresponding output to the comparing means 11. In this way, when the output of the bit signals of the pattern is advanced in order and a signal indicating a match is generated from the comparing means 11, the 9 selecting means 13 is switched to switch from the clock signal CK to the multi-frame timing signal mf, and the comparing means At 11, the same actions as when a match is detected are performed.

Next, to explain the waveform shown in B, in the example of the input signal IN in (3), the multi-frame pattern is arranged in a total of 26 bits (bits) from A to Z in each frame. Then, 1 in 26 frames
Configure multiframe. At this time, the multi-frame pattern.

AY-“1” and 2=“0” (rillll・
・1110'' pattern).

If such an input signal IN is input as shown in ■.

The memory holding means 1 uses the multi-frame signal mf shown in
0, the 26th multi-frame pattern “Z
” (="0") is held and a "0" signal is output as shown in ■.

At this time, if the multi-frame pattern generating means 14 generates the pattern at the beginning position "A" (= "1") of the multi-frame pattern as shown in ■, the comparing means 11 generates the pattern shown in ■. A mismatched output similar to the one shown below occurs. This mismatch output is input to the selection means 13 and switched to input the clock signal CK as shown in (3), and the multi-frame pattern generation means 14 is sequentially driven to change the pattern signals from "A" to "B" to "C". In this case, since the pattern signal from A to Y is "1", the output of the comparator 11 generates a mismatch output, but when it reaches "°Z", the comparator A coincidence output is generated as shown in (■), and the selection means 13 stops inputting the clock signal.After this, the multi-frame signal pattern of the input signal and the multi-frame pattern generation means 14 are synchronized. (It is sufficient to obtain a match on the specific side by counting the matching outputs of the comparing means).

Synchronization pull-in is complete.

In this case, assuming that the multi-frame signal interval time is X seconds and the number of data existing during this time is N (=n+1 bits), the pull-in is completed in 25XX/N seconds.

Using probability theory, when calculating the average value in the worst case, the probability of disagreement is set to 1/2.

It can be seen that the synchronization recovery time is (1+1/N)X-S seconds, which is faster than the conventional technique. However, S is (number of distribution points of multi-frame - 1)
represents.

[Embodiment] FIG. 2 is a block diagram of the embodiment, and FIG. 3 is a time chart of the embodiment.

In FIG. 2, 20 to 24 correspond to each part 10 to 14 of the principle configuration shown in FIG. Comparison circuit configured by logical sum,
Reference numeral 22 represents a multi-frame timing generation circuit composed of a 1/386 frequency dividing circuit, 23 represents a selection circuit, and 24 represents a signaling pattern generation circuit that generates a multi-frame pattern.

Note that this embodiment shows a configuration when applied to the primary group code adopted in North America.

In other words, superframe (SF
), the ISF consists of 12 frames, and bit signals called frame bits for frame synchronization and multiframe are provided at the beginning of each frame. Third. The frame bits of the 5th...11th odd frames are provided with a terminal pattern for frame synchronization, and the frame bits of the 2nd... The frame bits of the fourth, sixth, . . . , twelfth even frames are set with signaling patterns for control signals.

Therefore, in the North American primary group, the terminal pattern for frame synchronization is a sheet frame signal, and the signaling pattern is considered to be a multiframe pattern, and the operation is performed according to the configuration of the embodiment. Here, it is assumed that frame-by-frame pull-in using the terminal pattern (frame synchronization pattern) has been completed.

There are six signaling patterns in total, and in this example, if each bit making up the pattern is M1 to M6,
The pattern is M1=“O”, M2-“0”, M3=”1
”, M4=“1”, M5=“1”, M6-“O”.

In addition, the number of bits between each pattern is 386 (every 2 frames), and in the worst case 11i (the state where the patterns are most out of phase), the output of the latch circuit 2o is M6.
This is the case where the pattern output of the signaling pattern generation circuit 24 is in the output state Ml.

The time chart shown in FIG. 3 shows the operation starting from this worst situation.

First, the multi-frame timing generation circuit 22
When the bit signal M6 (-0'') is latched in the latch circuit 20 by the timing pulse shown in ■ output from Because of this.

The comparison circuit 21 outputs "o".

As a result, the 9 selection circuit 23 selects the output of the multi-frame timing generation circuit 22, and a multi-frame timing pulse is generated as shown in (■).The signaling pattern M1 in the input signal at this time is
Latched to 0.

At the same time, this multi-frame timing signal (pulse signal) is supplied to the signaling pattern generation circuit 24 via the selection circuit 23, which operates for one clock, and the pattern output becomes M2 (="O") as shown in ■. .

As a result, both signals input to the comparison circuit 21 become "0", and the 1 selection circuit 23 still selects the multi-frame timing generation circuit 22.

In the next multi-frame timing pulse, the latch circuit 20 generates M2 (="0") and the signaling pattern generation circuit 24 generates M3 (="l"), so the comparator circuit 21 generates "1". do. Then, the 3 selection circuit 23 selects the clock signal, so one clock signal is supplied to the signaling pattern generation circuit 24.

Then, the signaling pattern generation circuit 24.

A pattern M4 (="l") is generated and supplied to the comparison circuit 21. Therefore, the comparison circuit 21 still generates "1" and the 1 selection circuit 23 selects the next clock signal.

In this way, as shown in FIG. 2, when the phase is sequentially advanced until the signaling pattern generation circuit 24 generates the pattern M6 (="0"), the comparison circuit 21 generates "0" which is a coincidence output. After that, the launch circuit 20 becomes M3 (="1") by the 9 multi-frame timing pulses, and the pattern of the signaling pattern generation circuit 24 becomes M3.
l (="0"), the comparison circuit 21 generates "bi" indicating a mismatch, the 9 selection circuit 23 selects the clock signal again, and the phase of the signaling pattern generation circuit 24 advances. Generation circuit 2
4 advances to the phase of pattern M3, the comparator circuit 21
A coincidence output is generated, and the 1 selection circuit 23 stops inputting the clock signal. In this way, multi-frame synchronization is completed.

[Effects of the Invention] According to the present invention, in restoring multiframe synchronization,
Recovery time can be shortened. Thereby, the recovery time for recovery from a transmission signal interruption state can be shortened.

[Brief Description of the Drawings] Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a configuration diagram of an embodiment, Fig. 3 is a time chart of the embodiment, Fig. 4 is an example of a multi-frame frame structure, FIG. 5 is a configuration diagram of a conventional example. In Figure 1. lO: Memory retention means 11: Comparison means 12: Multi-frame timing generation means 13: Selection means 14: Multi-frame pattern generation means
l 8 m $2 figure

Claims (1)

[Claims] In a multi-frame synchronization recovery method for a communication device that transmits a signal with a multi-frame configuration including multi-frame patterns discretely distributed on frames at predetermined frame intervals, the clock signal extracted from the input signal is provided. multi-frame timing generating means for counting and generating an output at each generation interval of a bit signal of a synchronization pattern; and a memory for storing the content of the multi-frame signal in the input signal at the timing of the output from the multi-frame timing generating means. holding means; multi-frame pattern generation means for sequentially generating bits constituting a multi-frame pattern for each supplied signal; comparison means for comparing the output of the memory holding means and the output of the multi-frame pattern generation means; and selecting means for inputting the comparison results of the means, selecting the clock signal when there is a mismatch, and selecting the output signal of the multi-frame timing generating means when there is a match, and supplying the selected output signal to the multi-frame pattern generating means. A multi-frame synchronization recovery method.