JPS6021649A - Frame synchronizing circuit - Google Patents

Frame synchronizing circuit

Info

Publication number
JPS6021649A
JPS6021649A JP58129479A JP12947983A JPS6021649A JP S6021649 A JPS6021649 A JP S6021649A JP 58129479 A JP58129479 A JP 58129479A JP 12947983 A JP12947983 A JP 12947983A JP S6021649 A JPS6021649 A JP S6021649A
Authority
JP
Japan
Prior art keywords
circuit
error rate
stages
protecting
detection circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58129479A
Other languages
Japanese (ja)
Inventor
Eiichi Kabaya
蒲谷　衛一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58129479A priority Critical patent/JPS6021649A/en
Publication of JPS6021649A publication Critical patent/JPS6021649A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/042—Detectors therefor, e.g. correlators, state machines

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To provide the proper forward protecting number of stages to each of many lines having different error rate by changing the forward protecting number of stages by the information from an error rate detecting circuit. CONSTITUTION:A synchronism pattern coincidence/dissidence detecting circuit 1 detects the coincidence between a frame synchronizing pattern in a reception signal and a frame synchronizing pattern formed at a reception side and a coincidence pulse 8 is counted by a backward protecting and counting circuit 5 by the number of backward protecting stages to attain the synchronism state. A dissidence pulse 9 detected by the circuit 1 is counted by the forward protecting number of stages to form the out-of-synchronism state 10. When the frame synchronism is established, the error rate is supervised by an error rate detecting circuit 2 and transmits a signal 11, 12 or 13 depending on the small, middle or large error rate to a foward protecting number of stage switching circuit 3. The circuit 3 makes a signal 14, 15 or 16 representing the small, middle or large number of protecting stages generated from a number of protecting stage generating circuit 6 coincident with the signal 11, 12 or 13 to decide the forward protecting number of stages considered to be optimum to the error rate of the line thereby controlling the circuit 4.

Description

【発明の詳細な説明】 本発明は、ディジタル伝送系で送受の通話路のタイムス
ロットあるいはワードを混信のないように１対１に対応
させるフレーム同期回路に関し、特に、同期バタン監視
によるリセット形フレーム同期回路に関するものである
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frame synchronization circuit that matches time slots or words of a transmission/reception channel in a one-to-one manner to avoid interference in a digital transmission system. It is related to synchronous circuits.

従来、同期バタン監視によるリセット形フレーム同期回
路は２回線の誤り率を一定と仮定してミスフレーム間熱
から前方保護段数を決定し。Conventionally, a reset-type frame synchronization circuit using synchronization button monitoring determines the number of forward protection stages from the heat between misframes, assuming that the error rate of the two lines is constant.

誤同期危険率、再ハンチング危険率から後方保護段数を
決定している。上述の段数はフレーム数に対応する。ま
た、従来のフレーム同期回路は、パリティ検出やＣＲＣ
（Ｃｙｃｌｉｃ　ＲｅｄｕｎｄａｎｃｙＣｈｅｃｋ　）
符号による誤り検出機能を持っているが、それを同期同
護の段数に反映させることは行われていない。The number of rear protection stages is determined from the false synchronization risk rate and the rehunting risk rate. The number of stages mentioned above corresponds to the number of frames. In addition, conventional frame synchronization circuits also perform parity detection and CRC.
(Cyclic Redundancy Check)
Although it has a code-based error detection function, it is not reflected in the number of synchronization protection stages.

このように、従来のバタン監視のりセット形フレーム同
期回路は１回線の誤り率を一定と仮定し、前方保護段数
を決定しているが、異なった回線では誤り率も異なる。As described above, the conventional frame synchronization circuit using a button monitoring set type determines the number of forward protection stages on the assumption that the error rate of one line is constant, but the error rate differs for different lines.

従って、従来のフレーム同期回路では、多種の回線と接
続しようとする場合には、各回線に最適な前方保護段数
な選択できないという欠点があった。Therefore, the conventional frame synchronization circuit has the disadvantage that when connecting to various lines, it is not possible to select the optimal number of forward protection stages for each line.

本発明の目的は、上記欠点を除去し、誤り率検出回路か
らの情報で前方保護段数を変化させることにより、誤り
率の異なる多種の回線の各各に最適な前方保護段数を与
えることができるようにしたフレーム同期回路を提供す
ることにある。An object of the present invention is to eliminate the above drawbacks and to change the number of forward protection stages using information from an error rate detection circuit, thereby making it possible to provide an optimal number of forward protection stages to each of various lines with different error rates. An object of the present invention is to provide a frame synchronization circuit as described above.

本発明によれば、受信信号中のフレーム同期バタンと受
端側で作ったフレーム同期ノくタンとの一致又は不一致
を検出する同期ノくタン一致・不一致検出回路と、該同
期パタン一致・不一致検出回路よりの一致パルスをカウ
ントし、後方保護段数だけカウントすると同期状態とす
る後方保護用計数回路と、前記同期ノくタン一致・不一
致検出回路よりの不一致パルスをカウントし。According to the present invention, there is provided a synchronization button match/mismatch detection circuit for detecting whether a frame synchronization button in a received signal matches or does not match a frame synchronization button created on the receiving end side, and a synchronization pattern match/mismatch detection circuit. Counts the matching pulses from the detection circuit, and when the number of backward protection stages is counted, it becomes a synchronized state.The counting circuit for backward protection, and the mismatch pulses from the synchronization button coincidence/mismatch detection circuit are counted.

前方保護段数だけカウントすると同期はずれ状態とする
。前方保護段数を可変とした前方保護用計数回路と９回
線の誤り率を検出する誤り率検出回路と、該誤り率検出
回路の検出した誤り率の状態に応じて、前記前方保護用
計数回路の前方保護段数を切替える切替回路とを有する
ことを特徴とするフレーム同期回路が得られる。When the number of forward protection stages is counted, it becomes an out-of-synchronization state. a forward protection counting circuit with a variable number of forward protection stages; an error rate detection circuit that detects the error rate of nine lines; A frame synchronization circuit characterized by having a switching circuit for switching the number of forward protection stages is obtained.

次に本発明の実施例について図面を参照して説明する。Next, embodiments of the present invention will be described with reference to the drawings.

第１図を参照すると９本発明の一実施例（二よるフレー
ム同期回路は、受信信号中のフレーム同期バタンと受端
側で作ったフレーム同期バタンとの一致又は不一致を検
出する同期バタン一致・不一致検出回路１と、同期パタ
ン一致・不一致検出回路１からの一致パルス８をカウン
トし、後方保護段数だけカウントすると同期状態を示す
信号７を出力する後方保護用計数回路５と、同期パタン
一致・不一致検出回路１からの不一致パルスをカウント
し、前方保護段数だけカウントすると同期はずれ状態有
号権示ず信号１０を出力し、前方保護段数を可変とした
前方保護用計数回路４と１回線の誤り率を検出する誤り
率検出回路２と、この誤り率検出回路２の検出した誤り
率の状態に応じて、前方保護用計数回路４の前方保護段
数を切替える前方保護段数切替回路６とを有している。Referring to FIG. 1, a frame synchronization circuit according to an embodiment of the present invention (according to No. 2) is a synchronization button matching circuit that detects a match or mismatch between a frame synchronization button in a received signal and a frame synchronization button created on the receiving end side. A mismatch detection circuit 1, a backward protection counting circuit 5 that counts the match pulses 8 from the synchronization pattern match/mismatch detection circuit 1, and outputs a signal 7 indicating the synchronization state when the number of backward protection stages is counted, and a synchronization pattern match/mismatch detection circuit 5. When the mismatch pulses from the mismatch detection circuit 1 are counted and the number of forward protection stages is counted, the out-of-synchronization state signal 10 is output, indicating an error in the forward protection counting circuit 4 with variable number of forward protection stages and one line. and a forward protection stage number switching circuit 6 that switches the number of forward protection stages of the forward protection counting circuit 4 according to the state of the error rate detected by the error rate detection circuit 2. ing.

本実施例のフレーム同期回路は、同期パタン一致・不一
致検出回路１の一致パルス８を後方保護計数回路５でカ
ウントし、後方保護段数だけカウントされると同期状態
となる。また、不一致パルス９を前方保護計数回路４で
カウントし、前方保護段数だけカウントされると同期は
ずれ状態となる。まず、同期パタン一致・不一致検出回
路１でフレーム同期を確立する。フレーム同期が確立さ
れたら、誤り率検出回路２で誤り率の監視を行い、この
結果は前方保護段数切替情報として前方保護段数切替回
路３に送られる。前方保護段数段数切替回路３ではこの
情報により回線の誤り率に最適と思われる前方保護段数
を決定し、前方保護用計数回路４の制御を行う。前方保
護段数切替回路３は、保護段数発生回路６と、アンドゲ
ート１７．．１．８．１９と、オアゲート２０とを有す
る。保護段数発生回路６は。The frame synchronization circuit of this embodiment counts the coincidence pulses 8 of the synchronization pattern coincidence/mismatch detection circuit 1 in the backward protection counting circuit 5, and enters a synchronized state when the backward protection stage number is counted. Further, the mismatch pulses 9 are counted by the forward protection counting circuit 4, and when the number of forward protection stages is counted, an out-of-synchronization state occurs. First, the synchronization pattern match/mismatch detection circuit 1 establishes frame synchronization. Once frame synchronization is established, the error rate detection circuit 2 monitors the error rate, and the result is sent to the forward protection stage number switching circuit 3 as forward protection stage number switching information. The forward protection stage number switching circuit 3 uses this information to determine the number of forward protection stages that is considered to be optimal for the error rate of the line, and controls the forward protection counting circuit 4. The forward protection stage number switching circuit 3 includes a protection stage number generation circuit 6 and an AND gate 17 . ．． 1.8.19 and ORGATE 20. The protection stage number generation circuit 6 is as follows.

保護段数を小とする信号１４と、保護段数を中とする信
号１５と、保護段数を犬とする信号１６とを出力してい
る。他方、誤り率検出回路２は９回線の誤り率が小のと
き、信号１１を出力し９回線の誤り率が中のとき、信号
１２を出力し９回線の誤り率が犬のとき、信号１６を出
力する。A signal 14 indicating that the number of protection stages is small, a signal 15 that indicates that the number of protection stages is medium, and a signal 16 that indicates that the number of protection stages is dog are output. On the other hand, the error rate detection circuit 2 outputs a signal 11 when the error rate of the 9th line is small, outputs a signal 12 when the error rate of the 9th line is medium, and outputs a signal 16 when the error rate of the 9th line is a dog. Output.

ここで問題となるのは、誤り率と前方保護段数の関係で
あるが、これを第２図に示す。第２図の中で特徴的な６
つの場合について以下に説明する。The problem here is the relationship between the error rate and the number of forward protection stages, which is shown in FIG. Characteristic 6 in Figure 2
Two cases will be explained below.

■誤り率：小（即ち、誤り率検出回路２が信号１１を出
力した場合） フレーム同期バタンか１誤る確率は低く。■Error rate: Small (ie, when the error rate detection circuit 2 outputs signal 11) The probability of a frame synchronization slam or one error is low.

むしろ誤同期にはいった場合に早くぬけだせるように前
方保護段数を小さくする。Rather, the number of forward protection stages is made small so that if a false synchronization occurs, it can be quickly exited.

■誤り率：中（即ち、誤り率検出回路２が信号１２を出
力した場合） フレーム同期バタンか誤っても同期が はずれにくいように前方保護段数を大きくする。(2) Error rate: Medium (that is, when the error rate detection circuit 2 outputs signal 12) The number of forward protection stages is increased so that it is difficult to lose synchronization even if there is a frame synchronization slam or an error.

■誤り率：犬（即ち、誤り率検出回路２が信号１６を出
力した場合） 誤り率が設定したスレッンユホールド レベルＴｈ２を越えた場合は、早く再ハンチング状態に
入るように、前方保護段数を小さくする。■Error rate: (i.e., when the error rate detection circuit 2 outputs signal 16) If the error rate exceeds the set threat hold level Th2, the number of forward protection stages is set so that the re-hunting state is quickly entered. Make it smaller.

この関係に基づき回線の誤り率の状態から前方保護段数
を最適にすることが可能となる。Based on this relationship, it is possible to optimize the number of forward protection stages based on the state of the error rate of the line.

以上述べたように２本発明は回線の誤り率の状態により
前方保護段数を可変としたフレーム同期回路であり、こ
れにより、各回線に最適な前方保護段数を〜えることが
できるという効果を有する。As described above, the present invention is a frame synchronization circuit in which the number of forward protection stages is variable depending on the state of the error rate of the line, and this has the effect that the optimal number of forward protection stages can be determined for each line. .

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例によるフレーム同期回路のブ
ロック図、第２図は第１図の前方保護段数切替回路６の
動作を説明するための誤り率と最適な前方保護段数の関
係を示す図である。 １・・・同期パタン一致・不一致検出回路、２・・・誤
り率検出回路、３・・・前方保護段数切替回路。 ４・・・前方保護用計数回路、５・・後方保護用計数回
路、６・・・保護段数発生回路、７・・・同期状態信号
、８・・・一致パルス、９・・・不一致パルス、１０・
・・同期はずれ状態信号、１１・・・誤り率・小を示す
信号、１２・・・誤り率・中を示す信号、１６・・・誤
り率・犬を示す信号、１４・・・保護段数・小とする信
号、１５・・・保護段数・中とする信号。FIG. 1 is a block diagram of a frame synchronization circuit according to an embodiment of the present invention, and FIG. 2 shows the relationship between the error rate and the optimal number of forward protection stages to explain the operation of the forward protection stage number switching circuit 6 shown in FIG. FIG. 1... Synchronization pattern match/mismatch detection circuit, 2... Error rate detection circuit, 3... Forward protection stage number switching circuit. 4... Forward protection counting circuit, 5... Backward protection counting circuit, 6... Protection stage number generation circuit, 7... Synchronization state signal, 8... Match pulse, 9... Mismatch pulse, 10・
... Out-of-synchronization state signal, 11... Signal indicating small error rate, 12... Signal indicating medium error rate, 16... Signal indicating error rate dog, 14... Number of protection stages. Signal to be small, 15... Signal to be medium to protection stage number.

Claims (1)

【特許請求の範囲】 １、受信信号中のフレーム同期バタンと受端側で作った
フレーム同期バタンとの一致又は不一致を検出する同期
バタン一致・不一致検出回路と、該同期バタン一致・不
一致検出回路よりの一致パルスをカウントし、後方保護
段数だけカウントすると同期状態とする後方保護用計数
回路と、前記同期パタン一致・不一致検出回路よりの不
一致パルスをカウントし、前方保護段数だけカウントす
ると同期はずれ状態とする。前方保護段数をＩＩＪ変と
した前方保護用計数回路と。 回線の誤り率を検出する誤り率検出回路と、該誤り率検
出回路の検出した誤り率の状態に応じて、前記前方保護
用計数回路の前方保護段数をｔｕＪ　４にえる切替回路
とを有することを特徴とするフレーム同期回路。[Claims] 1. A sync-bump coincidence/mismatch detection circuit that detects whether a frame sync-bang in a received signal matches or doesn't match a frame sync-bang created on the receiving end; and a sync-bang coincidence/mismatch detection circuit. The backward protection counting circuit counts the matching pulses from the synchronous pattern match/mismatch detection circuit, and becomes synchronized when the number of backward protection stages is counted, and the synchronization pattern goes out of synchronization when the synchronization pattern match/mismatch detection circuit counts the number of forward protection stages. shall be. A forward protection counting circuit with the number of forward protection stages changed to IIJ. It has an error rate detection circuit that detects the error rate of a line, and a switching circuit that changes the number of forward protection stages of the forward protection counting circuit to tuJ 4 according to the state of the error rate detected by the error rate detection circuit. A frame synchronization circuit featuring:
JP58129479A 1983-07-18 1983-07-18 Frame synchronizing circuit Pending JPS6021649A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58129479A JPS6021649A (en) 1983-07-18 1983-07-18 Frame synchronizing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58129479A JPS6021649A (en) 1983-07-18 1983-07-18 Frame synchronizing circuit

Publications (1)

Publication Number Publication Date
JPS6021649A true JPS6021649A (en) 1985-02-04

Family

ID=15010496

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58129479A Pending JPS6021649A (en) 1983-07-18 1983-07-18 Frame synchronizing circuit

Country Status (1)

Country Link
JP (1) JPS6021649A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007258792A (en) * 2006-03-20 2007-10-04 Fujitsu Ltd Synchronizing device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007258792A (en) * 2006-03-20 2007-10-04 Fujitsu Ltd Synchronizing device

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