JP2870242B2 - Competitive synchronization protection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a contention-type synchronization protection circuit for a digital transmission apparatus, and more particularly to a contention-type synchronization protection circuit for performing frame synchronization in a digital transmission system.

[0002]

2. Description of the Related Art As shown in FIG. 2, a conventional synchronous protection circuit of this kind comprises a front protection counter 3 for counting up a mismatch pulse a, a front protection counter 9 for counting up a match pulse b, and a rear protection counter. Counter 10-3
It consists of two protection counters.

In this case, the forward protection counter 3 is used for synchronization loss due to the non-coincidence pulse a, and the front protection counter 9 and the rear protection counter 10 are used for synchronization using the coincidence pulse b. The output signal of the front protection counter 3 is input as a reset signal of the SR flip-flop (FF) 7, and the output signal of the rear protection counter 10 is input as a set signal of the flip-flop 7. More hunting pulse c
Is output, a frame synchronization pull-in operation is performed when an out-of-synchronization is detected by a synchronization detection circuit (not shown) in the frame synchronization method of digital transmission. In FIG. 2, reference numerals 1 and 2 denote input terminals to which the non-coincidence pulse a and the coincidence pulse b are input from the synchronization detection circuit, 6 denotes an OR gate, 8 denotes a hunting pulse output terminal, and 11 denotes an AND gate.

[0004]

Although the above-mentioned conventional synchronous protection circuit has three counter circuits, the realization of the counter circuit in LSI design requires a large number of cells. There are drawbacks that limit the degree of integration and increase the circuit scale.

[0005]

To solve the above-mentioned problems, the present invention is constituted by the following means. That is, in the above-mentioned competitive synchronization protection circuit, the coincidence pulse signal and the non-coincidence pulse signal from the synchronization detection circuit are input, and the front / rear protection counter by the coincidence pulse, the front protection counter by the non-coincidence pulse, and the front protection counter by the coincidence pulse. And a selector circuit for switching the use of the rear / back protection counter to a counter for front protection or rear protection using a hunting pulse.

[0006]

Therefore, the front / rear protection counter during frame synchronization can be selectively used by switching with a selector circuit using a hunting pulse.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of a contention-type synchronization protection circuit according to the present invention. This embodiment is different from the conventional example shown in FIG. 2 in that a front protection counter 3 using a mismatch pulse a and a front / rear protection counter 4 using a match pulse b are provided. By using the hunting pulse c generated by the SR type flip-flop (FF) 7
The front / rear protection counter 4 is configured to be switched between forward and rear by a selector circuit 5. The same reference numerals in the drawings indicate the same or corresponding parts.

In the synchronous protection circuit configured as described above, when a mismatch pulse a is input to the mismatch pulse input terminal 1, the front protection counter 3 counts up and outputs a reset signal when it reaches a predetermined value. Similarly, when the coincidence pulse b is input to the coincidence pulse input terminal 2,
The front / rear protection counter 4 counts up and outputs a set signal when it reaches a predetermined value. These output signals are input to an SR-type flip-flop (FF) 7 and also input from the OR gate 6 to the front protection counter 3 and the front / rear protection counter 4 as reset signals.

As a result, the hunting pulse c is output from the SR flip-flop 7 and the selector circuit 5
Is input to Accordingly, when the hunting pulse is present (out of synchronization), the selector circuit 5 outputs the forward / backward protection counter 4.
Can be switched to a rear protection counter when there is no hunting pulse (during synchronization).

[0010]

As described above, according to the present invention, the counter circuit can be reduced as compared with the conventional example by selectively using the forward / backward protection counter during frame synchronization by switching with a selector using a hunting pulse. Therefore, the circuit size of the competitive synchronization protection circuit can be reduced, and the LSI
This has the effect of increasing the degree of integration.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram illustrating an example of a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Unmatched pulse input terminal 2 Matched pulse input terminal 3 Forward protection counter 4 Forward / backward protection counter 5 Selector circuit 6 OR gate 7 SR type flip-flop (FF) 8 Hunting pulse output terminal

Claims (1)

(57) [Claims] 1. A contention type synchronous protection circuit for performing frame synchronization in a digital transmission system, comprising: a coincidence pulse signal and a non-coincidence pulse signal from a synchronization detection circuit as inputs; A forward protection counter for counting up the non-coincidence pulse, hunting pulse generating means for generating a hunting pulse from the output signals from the front / rear protection counter and the front protection counter, and a hunting pulse for the front / rear protection counter And a selector circuit for switching the application to a counter for forward protection or a counter for backward protection.