JP2549472Y2 - Frame synchronization protection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a digital signal communication system, and more particularly to a frame synchronization protection circuit for establishing frame synchronization based on a frame pulse included in a received digital signal. is there.

[Conventional technology]

FIG. 2 shows an example of a conventional frame synchronization protection circuit.

In the figure, 1 is a mismatch pulse input terminal, 2 is a clock input terminal of a clock signal having a repetition period equal to the frame period, 3, 4, 5, 6 and 7 are cascade-connected D flip-flops, and 8 is a D flip-flop. Each Q of 7
An AND gate having an output as an input, 9 is an AND gate having each of the outputs of the D flip-flops 3 to 6 as an input, and 10 is set by the output of the AND gate 8 and reset by the output of the AND gate 9. RS flip-flop 11 is an out-of-frame output terminal.

FIG. 2 shows a frame synchronization protection circuit having five stages of front protection and four stages of rear protection.

FIG. 3 and FIG. 4 are diagrams for explaining the operation of FIG. 2. FIG. 3 is a diagram showing an example of the waveform of each part in FIG. The figure shows an example of the waveform of each part in FIG. 2 and explains the operation of the rear protection.

Next, the operation of the frame synchronization protection circuit shown in FIG. 2 will be described with reference to FIG. 3 and FIG.

First, it is assumed that the initial state in FIG. 2 is a front protection state.

In FIG. 2, five consecutive non-coincidence pulses a (a comparison between a received data frame pulse and a local frame generated by the receiver) as shown in FIG. Is output to the clock input terminal 2).
It is assumed that a clock signal b (synchronized with the frame period of the local frame of the receiver) as shown in FIG. 3A and a phase relationship as shown in FIG. 3 are inputted.

The Q outputs e, d, e, f, g of the D flip-flops 3, 4, 4, 6, and 7 in FIG. 2 are shown in FIGS. 3 (c), (d), (e),
(F) and (g), the output h of the AND gate 8 and the Q output i of the RS flip-flop 10 connected to the S terminal, that is, the frame synchronization output terminal 11 Output changes as shown in FIG. 3 (h) or (i). That is,
The output of the frame-out-of-frame output terminal 11 changes to "H" level (HIGH) after five consecutive non-coincidence pulses, and it is determined that the output of the frame-out-of-frame output terminal 11 has become "H" level. If it is considered as a loss, it is clear that the circuit shown in FIG. 2 performs the function of the forward protection five stages (mismatch pulses are out of synchronization with five frames).

Then, a frame synchronization circuit (not shown) separately provided in the receiver recognizes that the frame synchronization is lost when the output of the frame synchronization output terminal 11 is at the “H” level, and shifts to a hunting operation.

Next, the operation of the four rearward protection steps will be described with reference to FIG.

First, it is assumed that the initial state in FIG. 2 is a rear protection state. Then, a clock signal b as shown in FIG. 4 (a) is input to the clock input terminal 2 of FIG. 2, and a non-coincidence pulse a having a time relationship with this clock b as shown in FIG. 4 (b). It is assumed that the input is made to the mismatch pulse input terminal 1.

At this time, the output j, k, l, m of each of the D flip-flops 3, 4, 5, 6 in FIG. 2 and the output of the AND gate 9 which takes the logical product of the respective outputs of the D flip-flops 3, 4, 5, 6 n changes as shown in FIGS. 4 (c), (d), (e), (f) and (g), respectively. Then, the output i of the RS flip-flop 10 whose output from the AND gate 9 is connected to the R terminal, that is, the output of the out-of-frame output terminal 11 changes as shown in FIG. 4 (h).

In other words, in order for the output of the frame out-of-frame output terminal 11 to change from the “H” level state to the L level (LOW) state, the mismatch pulses are intermittently lost for four consecutive frames.
That is, it is necessary that the frame pulse of the data received four consecutive frames and the frame pulse generated by the local frame in the receiver coincide with each other, and the frame synchronization protection circuit of FIG. It can be seen that the function is provided.

[Problems to be solved by the invention]

In the conventional frame synchronization protection circuit shown in FIG.
Due to an error in the opposing transmitter or transmission line, etc.
As a result of the operation of the local frame circuit operating together with the clock signal extracted from the received data signal being stopped,
When the clock signal input to the clock input terminal 2 disappears, the outputs of the D flip-flops 3 to 7 are not controlled. For example, when the clock signal input to the clock input terminal 2 is lost, all the outputs of the D flip-flop are stopped at the "L" level (of course, the output from the frame synchronization output terminal 11 is at the "L" level). When
When the clock signal is input to the clock input terminal 2 after the abnormality of the transmitter or the abnormality of the transmission line is recovered, the frame synchronization circuit of the receiver usually needs to perform the hunting operation to establish the frame synchronization. Since the initial state of the frame synchronization protection circuit shown in FIG. 2 is "L" level and the Q outputs of all D flip-flops are "L" level, the hunting operation of the frame synchronization circuit in the receiver is performed by the function of the forward protection five stages. It takes 5 frames to start the process, and the time until frame synchronization is established may be delayed.

In addition, if the newly input received data signal has a pulse having the same configuration as the frame pulse even once, for example, once every five frames in addition to the normal frame pulse, the generation of a mismatch pulse for five consecutive frames May not be seen, and the time until the frame synchronization circuit shifts to the hunting operation becomes longer,
If the position of a pulse having the same configuration as a frame pulse other than a regular pulse remains at a fixed position, the problem that the forward protection operation may not be released even though frame synchronization is not established may occur. Atsuta.

[Means for solving the problem]

The frame synchronization protection circuit according to the present invention includes a clock signal synchronized with a frame period from a frame synchronization circuit for establishing frame synchronization based on a frame pulse included in a received data signal and a local frame pulse generated in the frame synchronization circuit. And the information on the match / mismatch of the frame pulse included in the received data signal, and determines whether or not the frame is out of synchronization based on the given number of forward protection stages and the number of backward protection stages. In the frame synchronization protection circuit
S for receiving a desired signal different from the clock signal
It has a plurality of D flip-flops each having a terminal. The Q terminal of the D flip-flop arranged before is connected to the D terminal of the D flip-flop arranged behind, and a clock is connected to the T terminal of each D flip-flop. The D terminal of the leading D flip-flop is supplied with a D flip-flop group configured to receive the information on the match / mismatch of the frame pulse, and a predetermined number of forward protection stages among the Q terminals of the D flip-flop. The first connected to the Q terminal
, A second AND gate connected to a predetermined number of backward protection stages of the D flip-flop, and an output terminal and an S terminal of the first AND gate. And an RS flip-flop in which the output terminal of the second AND gate and the R terminal are connected to each other, and the first when the clock signal synchronized with the frame period is input to the frame synchronization protection circuit. A level signal is supplied to the S terminal of the D flip-flop, and when a clock signal synchronized with the frame cycle is not input to the frame synchronization protection circuit, a second level signal is supplied to the S terminal of the D flip-flop. And a mono-multi to be supplied to the vehicle.

[Operation] In the present invention, the presence or absence of an input clock signal is detected, and if there is no input clock signal, the frame synchronization protection circuit is fixed so as to be in the backward protection state.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a frame synchronization protection circuit according to the present invention.

In FIG. 1, the same reference numerals as those in FIG. 2 denote corresponding parts. Reference numerals 12, 13, 14, 15, and 16 denote D flip-flops with S terminals, and 17 inputs the Q outputs of the D flip-flops 12 to 16. AND gate (first AND gate) 18 is each of D flip-flops 12 to 15 (inverted Q)
An AND gate (second AND gate) having an output as an input, 19 is set by the output of the AND gate 17,
An RS flip-flop reset by the output of the AND gate 18 is a mono-multi 20 whose input terminal is connected to the clock input terminal 2 and whose output terminal is connected to each S terminal of the D flip-flops 12-16. Constitutes means for setting the frame synchronization protection circuit to the backward protection state when a clock signal synchronized with the frame period is not input to the frame synchronization protection circuit.

 Next, the operation of the embodiment shown in FIG. 1 will be described.

First, when a clock signal is normally input to the clock input terminal 2, the output of the monomulti 20 is at the "L" level (first level), and the S terminals of the D flip-flops 12 to 16 are all at the "L" level. The circuit shown in FIG. 1 is completely equivalent to the circuit shown in FIG.
That is, a frame synchronization function of five stages of front protection and four stages of rear protection is achieved.

On the other hand, when the clock signal is not inputted to the clock input terminal 2 for a certain period of time, the output of the mono multi 20 becomes "H" level (second level), and the D flip-flops 12 to 16 are set, that is, the D flip-flop 12 is set.
All 16 Q outputs are set to “H” level. As a result,
The output of the frame synchronization loss output terminal 11 is set to the “H” level (frame synchronization loss).

Next, the reception data to the receiver is temporarily interrupted due to the abnormality of the opposing transmitter or the abnormality of the transmission line, and similarly, after the clock signal input to the clock input terminal 2 in FIG. When the frame synchronization circuit in the receiver needs to recover and hunting operation to establish frame synchronization, as described above, the initial state of the frame synchronization protection circuit in FIG. Since the hunting operation is possible immediately, the time until the frame synchronization is established is also minimized.

In addition, even if a pulse having the same configuration as a frame pulse other than a regular frame pulse is applied, a pseudo-synchronization is not performed unless a pseudo-frame pulse that is continuous for four or more frames is provided by the backward protection function, thereby eliminating the drawbacks of the conventional example. be able to.

Thus, the frame synchronization protection circuit according to the present invention is:
The presence or absence of an input clock signal is detected, and when there is no input clock signal, the outputs of the D flip-flops for setting the number of protection stages constituting the frame synchronization circuit are all fixed to the same logic, and the output of the frame synchronization protection circuit is frame synchronized. It is configured to keep in a detached state, that is, a rearward protection state.

Although the embodiment shown in FIG. 1 shows a special case of five stages of front protection and four stages of rear protection, it is clear that the present invention is effective regardless of the number of front protection stages and the number of rear protection stages. It is.

[Effect of the invention]

As described above, the present invention detects the presence or absence of an input clock signal, and if there is no input clock signal, fixes the frame synchronization protection circuit so that it is in the backward protection state, thereby receiving the input clock signal when re-input. This has the effect that the operation of establishing frame synchronization by the frame synchronization circuit in the device becomes faster and more reliable.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a frame synchronization protection circuit according to the present invention, FIG. 2 is a block diagram showing an example of a conventional frame synchronization protection circuit, and FIGS.
It is a figure which shows the example of a waveform of each part used for description of operation | movement of a figure. 1 ... unmatched pulse input terminal, 2 ... clock input terminal, 11 ... out-of-frame output terminal, 12-16 ... D
Flip flop, 17,18 …… And gate, 19 …… RS
Flip Flop, 20 ... Mono Multi.

Claims (1)

(57) [Scope of request for utility model registration] 1. A clock signal synchronized with a frame cycle by a frame synchronization circuit for establishing frame synchronization based on a frame pulse included in a received data signal, a local frame pulse generated in the frame synchronization circuit, and the received frame signal. Matching of frame pulse included in data signal
The frame synchronization protection circuit that receives the mismatch information, determines whether or not the frame synchronization is lost based on the given number of forward protection stages and the number of backward protection stages, and sends the determination result to the frame synchronization circuit. S for receiving the desired signal
It has a plurality of D flip-flops each having a terminal. The Q terminal of the D flip-flop arranged before is connected to the D terminal of the D flip-flop arranged behind, and a clock is connected to the T terminal of each D flip-flop. A group of D flip-flops configured to receive the information of the match / mismatch of the frame pulse at the D terminal of the supplied D flip-flop, and a predetermined number of forward protection stages among the Q terminals of the D flip-flop. A first AND gate connected to a corresponding Q terminal; a second AND gate connected to a predetermined number of backward protection stages of the D flip-flops; An RS flip-flop in which the output terminal of the AND gate is connected to the S terminal and the output terminal of the second AND gate is connected to the R terminal; When a clock signal synchronized with the frame period is input to the clock synchronization protection circuit, a first level signal is supplied to the S terminal of the D flip-flop, and the signal synchronized with the frame period is synchronized with the frame synchronization protection circuit. And a monomultiplier for supplying a second level signal to the S terminal of the D flip-flop when a clock signal is not input.