JPH04259137A - Bit synchronization system - Google Patents

Abstract

PURPOSE:To take synchronization of a transmission signal correctly even when distortion takes place in a transmission signal by taking the synchronization of a reception clock signal again even against bit synchronization deviation in a window after the synchronization of the reception clock signal is established. CONSTITUTION:A window mask circuit 36 decides whether or not a window is valid and when the synchronization is not established, the window is masked to generate a reception clock signal S37 by using an edge detection signal S34. After the establishment of synchronization, the window is made effective and the signal S37 is generated by using window signals S35, S34. Thus, transmission distortion takes place just after the start of transmission while the synchronization is not established, the signal S37 is generated without being affected by the signal S35. On the other hand, even when bit deviation is large before the establishment of synchronization, since the signal S35 is valid after the establishment of synchronization, the phase is not locked as it is without being almost affected to the phase in which the synchronization is taken at first.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit synchronization method for serial data transmission, and more particularly to a bit synchronization method that improves synchronization technology for distorted transmission signals.

0002

2. Description of the Related Art Generally, when a transmission signal is transmitted using a communication line, a serial data transmission method is used in which the transmission data of the transmission signal is transmitted in the form of a bit string. In this serial data transmission system, the entire signal processing is performed based on the bit period of the transmission signal. For this reason, bit synchronization is a very important requirement in signal processing. Here, bit synchronization means synchronization according to the bit period.

By the way, conventionally, in the bit synchronization method for transmission signals, after determining the bit period from the transmission signal, a clock signal for bit synchronization is generated according to this bit period, and the clock signal for bit synchronization is used to synchronize the transmission signal. The method is to detect bits of transmitted data. Therefore, in order to process transmission signals correctly, it is essential to generate a clock signal for bit synchronization to accurately detect the bits of transmission data, and the quality of signal processing for serial data transmission depends on the bit synchronization. This will have an impact on the

[0004]In this type of serial data transmission, the transmission signal includes transmission data and a synchronization pattern (hereinafter referred to as a synchronization signal) for synchronizing the transmission data. The synchronization signal does not necessarily have a stable bit period. Therefore, even if a bit synchronization clock signal is generated once, there is a possibility that a synchronization error will occur thereafter. Therefore, it is necessary to sequentially monitor the bit synchronization clock signal and correct the deviation. Furthermore, when determining the bit period from the transmission signal, if the transmission signal is distorted, a bit synchronization clock signal may be generated incorrectly. In any case, the generation of the clock signal for bit synchronization is greatly affected by the distortion of the transmission signal.

The configuration of a bit synchronization circuit to which a conventional bit synchronization method is applied will be explained below with reference to FIG.
Special Publication No. 63-19105). That is, this FIG. 4 shows a bit synchronization circuit equipped with a window circuit for detecting synchronization shift, and is composed of a bit synchronization circuit 2 that synchronizes bits of a transmission signal 1 and a transmission signal regeneration circuit 3. It is configured to generate a clock signal S6 and input it to the transmission signal reproducing circuit 3.

The bit synchronization circuit 2 includes a counter circuit 22 that receives a reference signal S1 from a clock generator 21 and generates an operating clock S2, and a counter circuit 22 that detects a change point, that is, an edge, of the transmission signal 1 and generates an edge detection signal S3. An edge detection circuit 23 outputs an edge detection circuit 23, and each time a change point pulse of the transmission signal appears from the output of this edge detection circuit 23, the phase at which the next change point pulse should appear is predicted, and a forward/backward detection window is set for that phase. A window circuit 24 for setting is provided. This window circuit 24 applies a similar shift to the phase of the received clock signal depending on whether the changing point pulse shifts forward or backward. That is, the window circuit 24 sends an additional signal or a mask signal to the pulse manipulation circuit 26 when the change point pulse enters the front or rear window. Therefore, the pulse operation circuit 26 receives the addition signal or the mask signal and outputs a count pulse signal S4 in which a pulse is added or omitted from the operation clock of the counter circuit 22. The reception counter 25 outputs a reception clock signal S5 after counting a predetermined number of pulses based on the count pulse signal S4. Therefore, the output timing of this reception clock signal S5 is shifted forward or backward. On the other hand, the transmission signal reproducing circuit 3 is composed of, for example, a D flip-flop or the like, and sequentially samples the transmission signal 1 using the reception clock signal S5 to obtain a reproduction signal S6 for the transmission signal.

Therefore, in the bit synchronization circuit 2 as described above, the reception clock signal S5 is successively corrected according to the deviation of the edge detection signal S3, and the reproduced signal S with respect to the transmission signal is corrected.
6. Next, of the bit synchronization circuit 2,
In particular, the operation of the window circuit 25 will be explained with reference to FIG.

Normally, the reception counter 25 detects the reception clock signal S so that bit detection can be performed approximately at the center of each bit A1, A2, A3, . . . of the transmission signal 1, as shown in FIG. 5(a).
5, that is, B1, B2, B3', ... (Fig. 5(b)
) is input to the transmission data reproducing circuit 3. As a result, the transmission signal reproducing circuit 3 outputs the reproduced signals S6 as F1, F2, F3, . . . with a delay of time t, as shown in FIG. 5(f).

On the other hand, when the transmission signal 1 changes from "0" to state A1 of "1", the edge detection circuit 23 detects the state shown in FIG.
The edge detection signal S3 is outputted as E1 and E2 shown in (c) and inputted to the subsequent window circuit 24. The window circuit 24 receiving this edge detection signal E1 operates based on the reception clock signal S5 from the reception counter 25 as shown in FIG.
As shown in (d), a normal phase P1 is predicted to detect the next edge. Then, a front window FW1 and a rear window RW1 are set in front and behind the window (see FIG. 5(e)).

Next, the operation of the window circuit 25 when a bit shift occurs in the transmission signal 1 will be explained. Now, assume that a bit shift occurs in bit A3 of transmission signal 1 (see FIG. 5(a)). The window circuit 24 sets a front window FW2 and a rear window RW2 before and after the edge detection phase P2 predicted in advance (FIGS. 5(d) and (e)
)reference). On the other hand, when a bit shift occurs in the transmission signal 1, the edge detection signal S3 of the edge detection circuit 23 is delayed from E2 to E2' (see FIG. 5(c)). Therefore, the window circuit 24 detects that the edge detection signal E2' is located in the rear window RW2, and instructs the pulse operation circuit 26 to reduce the pulse signal. Therefore, the pulse operation circuit 26, which has received the instruction to reduce the pulse signal, appropriately masks the operation clock S2 from the counter circuit 22 and sends the count pulse signal S4 to the reception counter 25. As a result, the generation of the reception clock signal S5 by the reception counter 25 is delayed by the number of masked count pulses. Therefore, the next reproduced signal S6 (O2) is also delayed by the delay of the edge detection signal, and synchronization is achieved so that bits are detected correctly.

[0011]

However, in the window circuit 24 as described above, the following problem occurs when distortion occurs in the transmission signal 1 immediately after the start of transmission before synchronization has been completed. In other words, the window circuit 24 outputs a pulse correction signal in order to achieve correct synchronization, but if the deviation is large, it takes time to correct it correctly, and the phase deviation remains affected by the initially synchronized phase. There is a problem in that the phase is locked as it is, and the transmitted signal cannot be detected correctly thereafter.

The present invention has been made in view of the above-mentioned circumstances, and provides a bit synchronization method that can reliably confirm the established state of bit synchronization and can correctly synchronize transmission signals even if distortion occurs in the transmission signals. The purpose is to

[0013]

[Means for Solving the Problems] In order to solve the above problems, the present invention provides a transmission signal having transmission data transmitted by serial transmission and a synchronization signal for synchronizing the transmission data. In a bit synchronization method that generates a reception clock signal by determining a bit period from each bit, synchronization establishment detection means detects the synchronization signal and generates a synchronization establishment detection signal;

Edge detection means for detecting a change point of a pulse of the transmission signal to generate an edge detection signal; and a window for generating a window signal for detecting a shift in the edge detection signal generated by the edge detection means. a setting means, a window signal generated by the window setting means and the synchronization establishment detection signal are input;
A window mask means for validating only the synchronization establishment detection signal by masking the window signal before synchronization is established, and outputting a reset signal by validating the window signal and the synchronization establishment detection signal after synchronization is established; There is a system that includes reception clock generation means for generating a reception clock signal based on a reset signal output from the means.

[0015]

[Operation] Accordingly, in the present invention, by taking the above-mentioned measures, when a transmission signal is input, the synchronization establishment detection means detects the synchronization signal from the transmission signal, generates a synchronization establishment detection signal, and detects the window mask. send to means. Further, the edge detection means similarly detects the change point of the pulse of the input transmission signal, generates an edge detection signal, and sends it to the window mask means. On the other hand, the window setting means generates a window signal via the window masking means regarding the deviation of the edge detection signal generated by the edge detection means, and sends it to the window masking means. Here, the window masking means determines whether or not the window signal is valid based on the window signal generated by the window setting means and the synchronization establishment detection signal. After synchronization is established, a reception clock signal is generated by synchronizing with a window signal. by this,
Even if transmission distortion occurs immediately after the start of transmission before synchronization is complete, a reception clock signal can be generated without being affected by the window signal.

[0016]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a bit synchronization circuit to which the method of the present invention is applied. This configuration consists of a bit synchronization circuit 30 and a transmission signal regeneration circuit 40, of which the bit synchronization circuit 30 finally generates the reception clock signal S37 based on the transmission signal 1 inputted from the outside and transmits the received clock signal S37. On the other hand, the transmission signal regeneration circuit 40 is composed of, for example, a D flip-flop, and receives the reception clock signal S37 and outputs the transmission signal 1.
The reproduced signal S40 is generated and outputted while sampling.

The bit synchronization circuit 30 includes a synchronization establishment detection means 31, a clock generator 32 that generates a clock pulse S31 serving as an operation reference signal, a synchronization section 33, and the like. This synchronization establishment detection means 31 has a role of detecting synchronization establishment, and for example, the shift register 31
A and an arithmetic circuit 31b, the transmission signal 1 inputted from the outside is transferred bit by bit into a shift register 31a.
The arithmetic circuit 31b detects the synchronization establishment flag by determining the bit patterns S32a to S32n output from the shift register 31a, and sends the synchronization establishment detection signal S33 to the synchronization section 33.

The synchronization section 33 detects a change point, that is, an edge, of the transmission signal 1 and generates an edge detection signal S34.
, a window setting circuit 35 configured of, for example, a JK flip-flop circuit and outputting a window signal S35, a window mask circuit 36, and a reception clock generation circuit 37.

The window mask circuit 36 includes a window switch 36a such as a logic circuit, and a reset switch 36b, of which the reset switch 3
6b is the edge detection signal S34 and the window switch 36
Based on the window switch signal from a, the reset signal S36 is sent out only when the window is in the open state (LOW state). On the other hand, the reception clock generation circuit 37
is constituted by, for example, a hexadecimal counter 37a for bit division, a gate circuit 37b that generates a control signal, and a reception clock phase determining circuit 37c that generates a reception clock signal S37.

The window switch 36a receives the synchronization establishment detection signal S33 and the window signal S35 from the window setting circuit 35, and sends the window switch signal S36a to the reset switch 36b.

Next, the operation of the bit synchronization circuit 30 configured as described above will be explained. Note that it is assumed here that the transmission signal 1 for serial data transmission is expressed in Manchester code. The Manchester code is a code in which the polarity is reversed at the midpoint of the bit, and the polarity is different between the first half and the second half of one bit. In other words, the bit (1) 2 representing the ON state changes to 0, 1 and represents the OFF state (
0) 2 shall change from 1 to 0. (1) Regarding operations after synchronization is established.

Now, in the synchronization establishment detection means 31, for example, the synchronization establishment pattern is (101010101010101
0)2, that is, by representing each half bit by Manchester code (01100110011001100
110011001100110). Each transmission bit of the transmission signal 1 is sequentially transferred to the shift register 31.
a, and a shift operation is performed here to create the bit pattern.
The signals S32a to S32n are input to the arithmetic circuit 31b. In this arithmetic circuit 31b, the bit pattern appearing as the output of the shift register 31a is shown in B1 of FIG. 2(b) (011001100110011001100110
01100110) by calculation,
If it matches this bit pattern, it is determined that there is no deviation in the sampling position determined by the phase of the received clock signal S37, and the synchronization establishment signal S33 (FIG. 2(d)) is set to HIGH state D2 indicating synchronization establishment. ) is introduced into the window switch 36a. On the other hand, the edge detection circuit 34 detects the edge of the transmission signal 1, and generates an edge detection signal S34 shown in C1 of FIG. 3(c).
is introduced into the reset switch 36b.

In addition to the edge detection signal S36, the reset switch 36b also receives the window switch signal S36.
a is input, and this window switch signal S3
Only when 6a is in the HIGH state I1 (see FIG. 3(i)),
Reset signal S36 in HIGH state D1 indicating reset
is supplied to the reception clock generation circuit 37 (see FIG. 3(d)). Here, the hexadecimal counter 37a in the reception clock generation circuit 37 that receives the reset signal D1 resets its own count value and starts counting from zero. Furthermore, the gate circuit 37b following the counter 37a uses the window generation circuit 3 based on the count value of the counter 37a.
A close signal and a window open signal are applied to the J terminal and the K terminal of No. 5, respectively, while a clock reset signal S37b1 and a clock set signal S37b2 are sent to the reception clock phase determining circuit 37c. This clock reset signal S37b1 and clock set signal S37b
2, the reception clock phase determination circuit 37c determines the phase determination circuit 37c in FIG.
The reception clock signal S37 in the oscillation state shown in K1 of k) is generated and output.

Furthermore, specifically, the reception clock signal S37
The generation process will be explained. Note that the gate circuit 37b
Assume that it is programmed to operate as follows. a. The count value of the counter 37a is (1) 16 (1)
6 in hexadecimal), a close signal for closing the window is sent to the J terminal of the window setting circuit 35.

b. Similarly, when the count value is (3) 16, the reception clock phase determining circuit 3 sends a clock reset signal S37b1 that changes the phase of the reception clock to the LOW state.
Send at 7c.

c. Similarly, when the count value is (B) 16, the reception clock phase determination circuit 3 sends the clock set signal S37b2 that sets the phase of the reception clock to HIGH state.
Send at 7c. d. Similarly, when the count value is (C)16, an open signal for opening the window is sent to the window setting circuit 3.
Send to the K terminal of 5.

This means that when D1 of the reset signal S36 as shown in FIG. 3(d) is output from the reset switch 36b, the hexadecimal counter 37a starts counting from 0, and the count value becomes (1). When I was 16, I started playing games.
A close signal E1 is output from the gate circuit 37b and input to the J terminal of the window setting circuit 35 (see FIG. 3(e)). This window setting circuit 35 receives the close signal E.
When 1 is received, the window signal S35 is window clocked.
The window switch 36a is set to the HIGH state J2, which indicates a closed state, and is input to the window switch 36a (see FIG. 3(j)). here,
In the window switch 36a, the synchronization establishment detection means 31
The synchronization establishment signal S33 and the window signal S35 from
and sets the window switch signal S36a to the LOW state I2 in the reset switch 36b (see FIG. 3).
(see i)). Therefore, even if the edge detection signal S34 becomes the HIGH state C2 after that (see FIG. 3(c)), the reset signal S36 is not output to the hexadecimal counter 37a.

Next, the count value of the counter 37a becomes (3
)16, the gate circuit 37b outputs the reset signal H.
1 to the reception clock phase determination circuit 37c (Fig. 3
(see (h)). Receiving the reset signal H1, the reception clock phase determination circuit 37c resets the reception clock signal S37 to the LOW state K2, and
The oscillation state of is stopped (see FIG. 3(k)).

Furthermore, the count value of the counter 37a is (
B) At 16, the gate circuit 37b receives G1 of the clock set signal S37b2 and outputs it to the clock phase determining circuit 37.
c (see FIG. 3(g)). This set signal S3
Reception clock phase determination circuit 37c receiving G1 of 7b2
sets the reception clock signal S37 to the HIGH state K3 and starts oscillating the reception clock signal 37 (Fig. 3(k)
)reference).

Then, the count value of the counter 37a becomes (
C) When the signal becomes 16, the gate circuit 37b sends the open signal F1 to the K terminal of the window setting circuit 35 (see FIG. 3(f)). Here, the window setting circuit 35
When receiving the open signal F1, the window signal S35 is sent.
is set to the LOW state J3 indicating the window open state and sent to the window switch 36a (FIG. 3(j)
reference). This window switch 36a calculates the synchronization establishment signal S33 from the synchronization establishment detection means 31 and the window signal S35, and sends the window switch signal S36a in the HIGH state I3 to the reset switch 36b (see FIG. 3(i)). After this, the edge detection signal S34
becomes the HIGH state C3, the D of the reset signal S36
2 is sent to the hexadecimal counter 37a (Fig. 3(c), (
d)).

Now, let us consider the case where a bit shift state B1 occurs in the transmission signal 1 as shown in FIG. 3(b). In other words, when the transmission signal 1 enters the bit shift state B1, the edge detection signal S34 also shifts from C3' to C3 (Fig. 3(c)).
reference). As a result, the reset signal S36 becomes
) generates D2 as shown in FIG. Therefore, counter 37
A starts counting again from 0 as shown in A1 of FIG. 3(a). Thereafter, the time during which the window is open shifts from J4' to J4, and as a result, the generation time of the reception clock signal S37 also shifts from K4' to K4 (see FIG. 3(k)).

Therefore, the reception clock signal S37 remains in a HIGH state until the count value of the hexadecimal counter 37a is from (C) 16 to (3) 16 at the next count. and,
The time of this reception clock signal S37 is determined by the timing of the reset signal input to the hexadecimal counter 37a. Normally, the reception clock signal S37 with no bit shift is located at the center K of the bits, and its time is half the time of the entire bits (see FIG. 3(k)). As described above, the synchronization unit 33 that has received the synchronization establishment detection signal S33 establishes a window that provides phase limitations for detecting phase shifts, and resynchronizes only for phase shifts within the range of the window. Work like you do. (2) Regarding operations before synchronization is established.

First, the edge detection circuit 34 detects the transmission signal 1.
The edge detection signal S34 shown at C1 in FIG. 3(c) is introduced into the reset switch 36b. Here, since the window switch signal S36a is input to the reset switch 36b that receives C1 of the edge detection signal S34, this window switch signal S36
a is in a HIGH state F1 indicating a masked state before synchronization is established (see FIG. 2(f)). Therefore, C1 of the edge detection signal S34 is directly supplied to the reception clock generation circuit 37 as the reset signal G1 (FIG. 2(g)
reference). When G1 of this reset signal S36 is received, 1
The hexadecimal counter 37a resets its own count value and starts counting from 0. Here, gate circuit 37b
b sends a window close signal to the J terminal of the window setting circuit 35 based on the count value of the counter 37a;
While introducing an open signal to the K terminal, a clock reset signal S37b1 and a clock set signal S37b2 are sent to the reception clock phase determining circuit 37c. The reception clock phase determining circuit 37c generates the reception clock signal S37 in the h1 state based on the clock reset signal S37b1 and the clock set signal S37b2. However, the close signal and open signal to the window setting circuit 35 are masked because the synchronization establishment detection signal S33 is in the LOW state, and the window setting becomes invalid. Therefore, when synchronization has not been established, the edge detection signal S34 is used to directly detect the received clock signal S3.
7.

In this way, until the synchronization establishment detection signal S33 is received, the synchronization is re-established for all phase shifts in the bit period, and the reception clock signal S37 is generated.

Therefore, according to the configuration of the embodiment described above, the window mask circuit 36 determines whether the window is valid or not, and if synchronization is not established, the window is masked and edge detection is performed. A reception clock signal S37 is generated by the signal S34, and after synchronization is established, a window signal S35 is generated with the window as valid.
and the received clock signal S by the edge detection signal S34.
Generate 37. Thereby, even if transmission distortion occurs immediately after the start of transmission before synchronization has been completed, the reception clock signal S37 can be generated without being affected by the window signal S35. On the other hand, even if the bit shift is large before the synchronization is established, the window signal S35 becomes valid after the synchronization is established, so the phase will not be locked as it is, almost unaffected by the initially synchronized phase.

Note that the present invention is not limited to the above embodiments. For example, in this embodiment, a Manchester code is used as the transmission signal, but the transmission signal does not need to be a Manchester code. In addition, the present invention can be implemented with various modifications without departing from the gist thereof.

[0037]

As described above, according to the present invention, it is possible to provide a bit synchronization system that allows easy confirmation of synchronization and ensures synchronization without causing a phase shift even in distorted transmission signals.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing an embodiment of a bit synchronization circuit to which a bit synchronization method according to the present invention is applied.

FIG. 2 is a timing chart illustrating the operation of a bit synchronization circuit to which the method of the present invention is applied.

FIG. 3 is a timing chart illustrating operations after synchronization is established.

FIG. 4 is a configuration diagram of a bit synchronization circuit to which a conventional method is applied.

FIG. 5 is a timing chart illustrating the operation of a conventional circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1... Transmission signal, 30... Bit synchronization circuit, 31... Synchronization establishment detection means, 32... Clock generator, 33... Synchronization unit, 34
...Edge detection circuit, 35...Window setting circuit, 36...
window mask circuit, 37...reception clock generation circuit,
40...Transmission signal regeneration circuit.

Claims (1)

[Claims] 1. A bit that generates a reception clock signal by determining a bit period from each bit of a transmission signal that has transmission data transmitted by serial transmission and a synchronization signal for synchronizing this transmission data. In the synchronization method, synchronization establishment detection means detects the synchronization signal and generates a synchronization establishment detection signal, edge detection means detects a change point of a pulse of the transmission signal and generates an edge detection signal, and the edge detection means detects the synchronization signal and generates a synchronization establishment detection signal; a window setting means for generating a window signal for detecting a deviation of the edge detection signal generated by the means; the window signal generated by the window setting means and the synchronization establishment detection signal are input; a window mask means for validating only the synchronization establishment detection signal by masking the window signal, and outputting a reset signal by validating the window signal and the synchronization establishment detection signal after synchronization is established; 1. A bit synchronization method, comprising: reception clock generation means for generating a reception clock signal based on a reset signal.