JP2971150B2 - Bit synchronization method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit synchronization system for serial data transmission, and more particularly to a bit synchronization system in which a synchronization technique for a transmission signal having distortion is improved.

[0002]

2. Description of the Related Art In general, when transmitting a transmission signal using a communication line, a serial data transmission system for transmitting transmission data of the transmission signal in a bit string is used. In this serial data transmission system, the entire signal processing is performed according to the bit period of the transmission signal. For this reason, bit synchronization is a very important requirement in signal processing. Here, the bit synchronization means that synchronization is performed according to a bit cycle.

Conventionally, in a bit synchronization method for a transmission signal, a bit period is obtained from a transmission signal, a bit synchronization clock signal is generated in accordance with the bit period, and the transmission signal is generated using the bit synchronization clock signal. The method of detecting the bits of the transmission data is used. Therefore, in order to correctly process a transmission signal, it is essential to generate a bit synchronization clock signal for accurately detecting bits of transmission data, and depending on bit synchronization, whether signal processing for serial data transmission is good or not. Will be affected.

In this type of serial data transmission, a transmission signal includes transmission data and a synchronization pattern (hereinafter referred to as a synchronization signal) for synchronizing the transmission data. The synchronization signal does not always have a stable bit period. Therefore, even if a bit synchronization clock signal is generated once, there is a possibility that a synchronization shift will occur thereafter. Therefore, it is necessary to sequentially monitor the bit synchronization clock signal and correct the deviation. In addition, when the bit period is obtained from the transmission signal, if the transmission signal is distorted, a bit synchronization clock signal may be erroneously generated. In any case, the generation of the bit synchronization clock signal is greatly affected by the distortion of the transmission signal.

[0005] Hereinafter, the configuration of the conventional bit synchronization method bit synchronization circuit according to the described with reference to FIG. 4 (JP-B 63-19105 Patent Publication). That is, FIG. 4 shows a bit synchronization circuit provided with a window circuit for detecting a synchronization shift, which is composed of a bit synchronization circuit 2 for synchronizing the bit of the transmission signal 1 and a transmission signal reproduction circuit 3. The configuration is such that a clock signal S5 is generated and input to the transmission signal reproduction circuit 3.

The bit synchronization circuit 2 receives a reference signal S1 from a clock generator 21 and generates an operation clock S2. The bit synchronization circuit 2 detects a change point of the transmission signal 1, that is, an edge detection signal S3. From the output of the edge detection circuit 23, and predicts the phase at which the next change point pulse should appear from the output of the edge detection circuit 23, and calculates the forward / backward detection window for the phase. Is provided. The window circuit 24 applies the same shift to the phase of the received clock signal according to whether the change point pulse shifts forward or backward. That is, the window circuit 24 sends an additional signal or a mask signal to the pulse operation circuit 26 when the transition point pulse enters the front or rear window. Therefore, the pulse operation circuit 26 receives the additional signal or the mask signal and outputs a count pulse signal S4 in which the operation clock of the counter circuit 22 has addition or omission of a pulse. When the reception counter 25 counts a predetermined number of pulses based on the count pulse signal S4, it outputs a reception clock signal S5. Therefore, the output timing of the reception clock signal S5 is shifted forward or backward. On the other hand, the transmission signal reproducing circuit 3 is composed of, for example, a D flip-flop, and sequentially samples the transmission signal 1 using the reception clock signal S5 to obtain a reproduction signal S6 for the transmission signal.

Therefore, in the bit synchronization circuit 2 as described above, for example, from "0" of each bit of the transmission signal,
Detects a level change point of a predetermined bit that rises to “1” and
Is intended to obtain a reproduction signal S6 for successively correcting the transmission signal of the reception clock signal S5 in accordance with the edge detection signal S 3 output. Next, the operation of the window circuit 24 of the bit synchronization circuit 2 will be described with reference to FIG.

Normally, as shown in FIG. 5A, the reception counter 25 receives the reception clock signal S so that the bit can be detected substantially at the center of each bit A1, A2, A3,.
5, that is, B1, B2, B3 ',.
(B)) and input to the transmission data reproduction circuit 3. As a result, the transmission signal reproducing circuit 3 outputs a reproduced signal S6 reproduced as F1, F2, F3,... With a delay of time t as shown in FIG.

On the other hand, when the transmission signal 1 changes from "0" to "1" state A1, the edge detection circuit 23
The edge detection signal S3 is output as shown by E1 and E2 shown in FIG. The window circuit 24 that has received the edge detection signal E1 generates a signal based on the reception clock signal S5 from the reception counter 25 as shown in FIG.
As shown in (d), the normal phase P1 is predicted to detect the next edge. Then, a front window FW1 and a rear window RW1 are set at the front and the rear (see FIG. 5E).

Next, the operation of the window circuit 25 when a bit shift occurs in the transmission signal 1 will be described. Now, it is assumed that a bit shift has occurred in the bit A3 of the transmission signal 1 (see FIG. 5A). The window circuit 24 sets a front window FW2 and a rear window RW2 before and after the predicted phase P2 of the edge detection (FIG. 5D,
(E)). On the other hand, when a bit shift occurs in the transmission signal 1, the edge detection signal S3 of the edge detection circuit 23 becomes E2
To E2 '(see FIG. 5C). Therefore, the window circuit 24 detects that the edge detection signal E2 'is located in the rear window RW2, and instructs the pulse operation circuit 26 to reduce the pulse signal. Therefore,
Upon receiving the instruction to reduce the pulse signal, the pulse operation circuit 26 appropriately masks the operation clock S2 from the counter circuit 22 and sends out the count pulse signal S4 to the reception counter 25. Thus, the generation of the reception clock signal S5 by the reception counter 25 is delayed by the number of masked count pulses. Therefore, the next reproduction signal S6 (O
2) is also delayed by the delay of the edge detection signal, and synchronized so as to correctly detect the bit.

[0011]

However, in the above-described window circuit 24, when distortion occurs in the transmission signal 1 immediately after the start of transmission in which synchronization is not completed, the following problem occurs. In other words, the window circuit 24 outputs a pulse correction signal in order to properly synchronize, but if the deviation is large, it takes time to correct correctly, and the phase deviation is affected by the initially synchronized phase. There is a problem in that the transmission signal cannot be detected correctly after the phase locks.

The present invention has been made in view of the above circumstances, and provides a bit synchronization system capable of reliably confirming the establishment state of bit synchronization and correctly synchronizing transmission signals even when distortion occurs in the transmission signals. The purpose is to:

[0013]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides each bit of a transmission signal having transmission data transmitted by a serial data transmission method and a synchronization signal for synchronizing the transmission data. in the bit synchronization method for generating a reception clock signal seeking bit period from the synchronization establishment detecting means for generating a detected synchronization establishment detecting signal the synchronization signal from the bit pattern of the transmission signal, each bit of said transmission signal predetermined bit detection level <br/> change point and an edge detection means for generating or falling edge of edge detection signal, synchronization establishment before based on the output of the synchronization establishment detecting unit of
The edge detection signal is masked by masking the window signal described later.
Signal as it is as a reset signal,
After synchronization is established after receiving the synchronization establishment detection signal from the detection means
Only when the window signal described later is open.
Window that generates a reset signal based on an edge detection signal
Mask means and a clock for generating a reference clock signal
A source and a reset signal from the window mask means.
After receiving and resetting, the reference clock signal
Count and different predetermined counts
Based on the value, the window close control signal and the window
Output window open control signal and receive clock
Receiving clock generating means for generating and outputting a signal;
The close control signal output from the
Window close and open control signals
And the window signal that opens the window
Window setting to be introduced into the window mask means
This is a bit synchronization system having a setting means.

[0014]

[0015]

According to the present invention, when the transmission signal is inputted, the synchronization establishment detecting means generates the synchronization signal based on the bit pattern of the transmission signal.
Judge whether it is out of the specified sampling position
If there is no displacement, a synchronization establishment detection signal is generated.
To the window mask means. Meanwhile, edge detection
In the means, a predetermined bit level of each bit of the transmission signal is
Edge detection by detecting a point where the direction changes from "0" to "1"
A signal is generated and sent to the window mask means.
In this window mask means, the synchronization establishment detecting means is synchronized.
When it is determined that it is not established, the
Invalidates the window signal that is
As a reset signal, while the synchronization
Judgment that synchronization is established when a synchronization establishment detection signal is received from the stage
Only when the window signal is open, the edge
Generates and outputs a reset signal based on the detection signal and receives it
Send to clock generation means. Here, the received clock
The reset signal from the window mask means.
Each time it is received, it is reset and counts the reference clock signal.
To a different predetermined count value.
Window close control signal and window based on
Sends an open control signal to the window setting means,
Generate and output a receive clock signal. Window setting hand
In the stage, the closed signal output from the receiving clock generating means is closed.
Close and close according to the control signal and the open control signal.
Output a window signal to open
To the masking means. As a result, the window mask means determines whether or not the window signal is valid based on the window signal generated by the window setting means and the synchronization establishment detection signal. Generate a signal. As a result, even when transmission distortion occurs immediately after the start of transmission, such as when synchronization is not completed , a reception clock signal can be generated without being affected by the window signal.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram showing one embodiment of a bit synchronization circuit to which the method of the present invention is applied. This configuration comprises a bit synchronizing circuit 30 and a transmission signal reproducing circuit 40, of which the bit synchronizing circuit 30 finally generates a reception clock signal S37 based on the transmission signal 1 input from the outside, and The transmission signal reproduction circuit 40 is configured by, for example, a D flip-flop, and receives the reception clock signal S37 to receive the transmission signal 1.
The reproduction signal S40 is generated and output while sampling the data.

The bit synchronization circuit 30 comprises a synchronization establishment detecting means 31, a clock generator 32 for generating a clock pulse S31 as an operation reference signal, a synchronization section 33, and the like. The synchronization establishment detecting means 31 has a role of detecting the establishment of the synchronization.
a and an operation circuit 31b, and transmits the transmission signal 1 input from the outside to the shift register 31a one bit at a time.
The arithmetic circuit 31b determines the bit pattern S32a to S32n output from the shift register 31a to detect the synchronization establishment flag, and sends a synchronization establishment detection signal S33 to the synchronization section 33.

The synchronization section 33 detects a change point of the transmission signal 1, that is, an edge, and detects an edge detection signal S34.
, A window setting circuit 35 composed of, for example, a JK flip-flop circuit and outputting a window signal S35, a window mask circuit 36, and a reception clock generation circuit 37.

The window mask circuit 36 includes a window switch 36a such as a logic circuit and a reset switch 36b.
6b is an edge detection signal S34 and a window switch 36
The reset signal S36 is transmitted only when the window is in the open state (LOW state) based on the window switch signal from a. On the other hand, the reception clock generation circuit 37
Is composed of, for example, a hexadecimal counter 37a for bit division, a gate circuit 37b for generating a control signal, and a reception clock phase determination circuit 37c for generating a reception clock signal S37.

The window switch 36a receives the synchronization establishment detection signal S33 and the window signal S35 from the window setting circuit 35, and sends out the window switch signal S36a to the reset switch 36b.

Next, the operation of the bit synchronization circuit 30 configured as described above will be described. Here, it is assumed that the transmission signal 1 of the serial data transmission is represented by Manchester code. The Manchester code is a code in which the polarity is inverted at the middle point of the bit, and the polarity is different between the first half and the second half of one bit. That is, it is assumed that (1) 2 representing the ON state of the bit changes to 0, 1 and (0) 2 representing the OFF state changes to 1, 0. (1) Operation after synchronization is established.

Now, in the synchronization establishment detecting means 31, for example, the synchronization establishment pattern is (1010101010101010) 2, that is, the half-bit representation by the Manchester code (01
100110011001100110011001100110). Each transmission bit of the transmission signal 1 is sequentially transferred to the shift register 3
1a, where the shift operation is performed, and the bit patterns S32a to S32n are input to the arithmetic circuit 31b.
The arithmetic circuit 31b determines by arithmetic operation whether or not the bit pattern appearing as the output of the shift register 31a is (01100110011001100110011001100110) shown in B1 of FIG. 2 (b). It is determined that there is no shift in the sampling position determined by the phase of the clock signal S37, and the state is set to the HIGH state D2 indicating the establishment of the synchronization, and the synchronization establishment signal S33 (FIG.
(D) is introduced into the window switch 36a.
On the other hand, the edge detection circuit 34 detects an edge of the transmission signal 1 and outputs an edge detection signal S34 indicated by C1 in FIG.
To the reset switch 36b.

The reset switch 36b has an edge detection signal S36 and a window switch signal S36.
a is input and the window switch signal S3
Only when 6a is in the HIGH state I1 (see FIG. 3 (i)), the reset signal S36 of the HIGH state D1 indicating the reset is supplied to the reception clock generation circuit 37 (FIG. 3).
(D)). Here, the hexadecimal counter 37a in the reception clock generation circuit 37 receiving the reset signal D1 resets its own count value and starts counting from zero. Further, a gate circuit 37b following the counter 37a
Then, the window is set based on the count value of the counter 37a.
A close control signal (hereinafter referred to as “claw”) is
Open system of window's signal is referred to as a) and K terminal
A control signal (hereinafter referred to as an open signal) is supplied to the reception clock phase determination circuit 37c.
S37b2 and the clock set signal S37b1 are transmitted. Upon receiving the clock reset signal S37b2 and the clock set signal S37b1 , the reception clock phase determination circuit 37c generates and outputs the reception clock signal S37 in the oscillation state indicated by K1 in FIG. 3 (k).

Further, more specifically, the reception clock signal S37
Will be described. The gate circuit 37b
Is programmed to operate as follows. a. When the count value of the counter 37a is (1) 16 (16 is 1
In the case of hexadecimal notation, a close signal for closing the window is sent to the J terminal of the window setting circuit 35.

B. Similarly, when the count value is (3) 16,
A clock reset signal S37b2 for setting the phase of the reception clock to the LOW state is sent to the reception clock phase determination circuit 37c.

C. Similarly, when the count value is (B) 16,
The clock set signal S37b1 for setting the phase of the reception clock to the HIGH state is sent to the reception clock phase determination circuit 37c.

That is, when D1 of the reset signal S36 as shown in FIG. 3D is output from the reset switch 36b, the hexadecimal counter 37a starts counting from 0, and the count value becomes (1). At 16, the close signal E1 is output from the gate circuit 37b and input to the J terminal of the window setting circuit 35 (see FIG. 3E). The window setting circuit 35 generates the close signal E1.
When the window signal S35 is received, the window signal S35 is set to the HIGH state J2 indicating the window close state, and is input to the window switch 36a (see FIG. 3 (j)). Here, the window switch 36a calculates the synchronization establishment signal S33 from the synchronization establishment detecting means 31 and the window signal S35, and sets the window switch signal S36a to the LOW state I2 for the reset switch 36b (FIG. 3).
(See (i)). Therefore, thereafter, the edge detection signal S34
Is in the HIGH state C2 (see FIG. 3C), the reset signal S36 is not output to the hexadecimal counter 37a.

Next, when the count value of the counter 37a is (3) 16, the gate circuit 37b sends the reset signal H1 to the reception clock phase determination circuit 37c (see FIG. 3 (h)). Upon receiving the reset signal H1, the reception clock phase determination circuit 37c outputs the reception clock signal S37.
Is reset to the LOW state K2, and the reception clock signal S3
7 is stopped (see FIG. 3 (k)).

Further, when the count value of the counter 37a is (B) 16, the gate circuit 37b converts the G1 of the clock set signal S37b1 into the reception clock phase determination circuit 37.
c (see FIG. 3 (g)). This set signal S3
Received clock phase determination circuit 37c receiving G1 of 7b1
Sets the reception clock signal S37 to the HIGH state K3 and starts oscillating the reception clock signal S37 (FIG. 3).
(K)).

When the count value of the counter 37a becomes (C) 16, the gate circuit 37b sends the open signal F1 to the K terminal of the window setting circuit 35 (see FIG. 3 (f)). ). Here, the window setting circuit 35
Receives the open signal F1, the window signal S35
Is set to the LOW state J3 indicating the window open state, and sent to the window switch 36a (FIG. 3 (j)).
reference). The window switch 36a calculates a synchronization establishment signal S33 from the synchronization establishment detecting means 31 and the window signal S35, and sends a HIGH state I3 window switch signal S36a to the reset switch 36b (see FIG. 3 (i)). Thereafter, the edge detection signal S34
Becomes HIGH state C3, the reset signal S36
2 is sent to the hexadecimal counter 37a (FIG. 3 (c),
(D)).

Here, it is assumed that a bit shift state B1 occurs in the transmission signal 1 as shown in FIG. That is, when the transmission signal 1 enters the bit shift state B1, the edge detection signal S34 also shifts from C3 'to C3 (FIG. 3).
(C)). As a result, the reset signal S36 generates D2 as shown in FIG. Therefore, the counter 37a starts counting from 0 again as indicated by A1 in FIG. After that, the window
The time in the open state shifts from J4 'to J4. As a result, the generation time of the reception clock signal S37 also changes from K4' to K4.
4 (see FIG. 3 (k)).

Accordingly, the reception clock signal S37 is in the HIGH state from the time when the count value of the hexadecimal counter 37a is (C) 16 to the time (3) 16 at the next count. And 16
The time of the received clock signal S37 is determined by the timing of the reset signal input to the binary counter 37a. Normally, the reception clock signal S37 without any bit shift is located at the center K of the bit, and its time is half the time of the entire bit (see FIG. 3 (k)). As described above, the synchronization unit 33 receiving the synchronization establishment detection signal S33
Operates such that a window for imposing a phase limit for detecting a phase shift is provided, and resynchronization is performed only for a phase shift within the window. (2) Operation before synchronization is established.

First, the edge detection circuit 34 detects the transmission signal 1
Is detected, and an edge detection signal S34 indicated by C1 in FIG. 3C is introduced to the reset switch 36b. Here, since the window switch signal S36 has been input to the reset switch 36b that has received C1 of the edge detection signal S34, this window switch signal S36a
Is the state before the synchronization is established , so that HI indicating the mask state
The state is the GH state F1 (see FIG. 2F). Therefore, C1 of the edge detection signal S34 is supplied as it is to the reception clock generation circuit 37 as the reset signal D1 ( see FIG. 2C). Upon receiving D1 of the reset signal S36, the hexadecimal counter 37a resets its own count value and starts counting from 0. Here, the gate circuit 37 b is-out based on the count value of the counter 37a,
For example, when the count value is “1”, the J
A window close signal is applied to the terminal and the count value "C"
, An open signal is introduced into the K terminal, and a clock reset signal S37b2 with a count value “3 ” and a clock set signal S37b1 with a count value “B” are sent to the reception clock phase determination circuit 37c. The reception clock phase determination circuit 37c generates the reception clock signal S37 in the state of h1 based on the clock reset signal S37b2 and the clock set signal S37b1 . However, the close signal and the open signal to the window setting circuit 35 are masked because the synchronization establishment detection signal S33 is in the LOW state, and the window setting becomes invalid. Therefore,
When the synchronization is not established, the operation is performed so as to generate the reception clock signal S37 by the edge detection signal S34.

As described above, until the synchronization establishment detection signal S33 is received, the operation is performed so as to generate the reception clock signal S37 while re-establishing the synchronization for all the phase shifts in the bit cycle.

Therefore, according to the configuration of the above-described embodiment, whether the window is valid or not is determined by the window mask circuit 36. If the synchronization is not established, the window is masked to detect the edge. A reception clock signal S37 is generated by the signal S34, and after the synchronization is established, the window signal S35
And the reception clock signal S by the edge detection signal S34.
37 is generated. As a result, even when transmission distortion occurs immediately after the start of transmission where synchronization is not completed, the reception clock signal S37 can be generated without being affected by the window signal S35. On the other hand, even if the bit shift is large before the synchronization is established, the window signal S35 becomes valid after the synchronization is established, so that the phase is not locked as it is without being affected by the initially synchronized phase.

The present invention is not limited to the above embodiment. For example, in this embodiment, the Manchester code is used as the transmission signal, but the transmission signal need not be the Manchester code. In addition, the present invention can be implemented with various modifications without departing from the scope of the invention.

[0037]

As described above, according to the present invention, it is possible to provide a bit synchronization system in which the establishment of synchronization can be easily confirmed, and the synchronization can be reliably achieved without causing a phase shift even in a distorted transmission signal.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of a bit synchronization circuit to which a bit synchronization method according to the present invention is applied.

FIG. 2 is a timing chart illustrating the operation of a bit synchronization circuit to which the method of the present invention is applied.

FIG. 3 is a timing chart illustrating an operation after synchronization is established.

FIG. 4 is a configuration diagram of a bit synchronization circuit to which a conventional method is applied.

FIG. 5 is a timing chart for explaining the operation of the conventional circuit.
G.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Transmission signal, 30 ... Bit synchronization circuit, 31 ... Synchronization establishment detection means, 32 ... Clock generator, 33 ... Synchronization part, 34
... Edge detection circuit, 35 ... Window setting circuit, 36 ...
Window mask circuit, 37 ... reception clock generation circuit,
40 ... Transmission signal reproduction circuit.

Claims (1)

(57) [Claims] 1. A cerealDepending on the data transmission methodTransmitted
Transmission data and synchronization for synchronizing this transmission data
A bit period from each bit of a transmission signal having
Bit synchronization method that generates a receive clock signal
hand,Bit pattern of the transmission signal From the synchronization signal
ShidoSynchronization establishment detecting means for generating a phase establishment detection signal;The level of a given bit of each bitchange
Find pointDEdge detection means for generating an edge detection signal
When,Before synchronization establishment based on the output of the synchronization establishment detection means,
The edge detection is performed by masking the window signal.
Output signal as it is as a reset signal, and
Synchronization confirmation after receiving the synchronization establishment detection signal from the establishment detection means
Only after the window signal is open
A window that generates a reset signal based on the edge detection signal
Window mask means, A clock source for generating a reference clock signal; Upon receiving a reset signal from the window mask means,
Count the reference clock signal after being set
Together with a different predetermined count value
Window close control signal and window
Generates a receive clock signal while outputting a pin control signal
Receiving clock generating means for outputting Close control output from the reception clock generation means
Window clock based on the signal and the open control signal.
Window signal that causes
Signal which is output to the window mask means.
Dough setting means and With Bit synchronization method characterized by the following:
formula.