JPH05244147A - Detecting circuit for hit of digital data - Google Patents

Abstract

PURPOSE:To provide the subject detecting circuit which can shorten the time when the digital date has a hit and then a data hit detecting signal is transmitted and also can work stably even with a low C/N ratio. CONSTITUTION:A frame synchronization protecting circuit (a synchronization detector 1, a coincident counter 2, a discordant counter 3 or a frame counter 4, etc.) protects the frame synchronizing signals produced by the frame synchronization patterns which are included in a prescribed cycle in the received digital data. Then a correlative pattern synchronization detector 9 is provided to the frame synchronization protecting circuit to detect the correlative discordance of the frame synchronization patterns and to produce a detection pulse together with a discordance detector 11 which produces a discordance signal based on the inverted signal of the detection pulse and the retrieving position pulse of the frame synchronization pattern obtained by the frame synchronization protecting circuit, and a circuit (a flip-flop 8) which receives the discordance signal and outputs a date hit detection signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital data momentary interruption detection circuit, and more particularly to a digital data momentary interruption detection circuit used for suppressing and controlling noise generated by momentary interruption of PCM voice data during reception.

[0002]

2. Description of the Related Art Conventionally, as means for detecting a momentary interruption of digital data that occurs during reception of PCM voice data, for example, in a PCM voice data receiver, a momentary interruption of digital data occurs when a receiving channel is switched. ,
The channel switching signal is used as a data interruption detection signal. Also, when PCM audio data is decoded at a place distant from the receiver, or when a channel switching signal cannot be obtained, the synchronization of the frame synchronization protection circuit that protects the frame synchronization pattern included in the PCM audio data is lost. Data instantaneous interruption detection signal is generated by the signal.

FIG. 2 shows an example of a digital data instantaneous interruption detection circuit using an out-of-sync signal of a conventional frame synchronization protection circuit. A synchronism detector 1 that detects a frame synchronization pattern composed of 16 bits included in the PCM audio data Si at a period of 1 ms and sends a detection pulse Pd, and a frame synchronization pattern is generated at a period of 1 ms, which is the same as the received frame synchronization. Then, the frame counter 4 that outputs the synchronization pulse Ps synchronized with this, the detection pulse Pd, and the synchronization pulse P
a coincidence counter 2 for comparing s and counting the number of coincidences,
A mismatch counter 3 that counts the number of mismatches by comparing the detection pulse Pd and the synchronization pulse Ps, and a frame counter 4
Flip-flop 5 and AND gate 7 provided for resetting the match counter 2, mismatch counter 3, and OR gate 6 provided for resetting the flip-flop 5, and a flip-flop 5 for generating the data instantaneous interruption detection signal Sa. 8 and.

Next, the operation will be described. When the coincidence counter 2 counts the number of coincidences up to 3, it outputs the coincidence signal C1 to reset the flip-flop 8 and resets the coincidence counter 2, the non-coincidence counter 3 and the flip-flop 5 via the OR gate 6. Further, when the mismatch counter 3 counts the mismatches up to eight times, the mismatch signal C2
To output flip-flops 5 and 8
Set. Therefore, the mismatch counter 3 is now 8
When the coincidence counter 2 counts 3 times before counting the number of times, the non-coincidence counter 3 is reset, but when the non-coincidence counter 3 counts 8 times, the flip-flop 5 is set and the detection pulse from the synchronization detector 1 is set. Pd
Is transmitted, the frame counter 4 is reset via the AND gate 7 and the synchronization is corrected.

The coincidence counter 2 and the disagreement counter 3
The count number is set according to the synchronization protection characteristic of the frame counter 4. The flip-flop 8 outputs the data instantaneous interruption detection signal Sa when the mismatch counter 3 counts eight times. Therefore, as shown in FIG.
When the CM voice data Si is momentarily interrupted, the non-coincidence state continues, and therefore the data instantaneous interruption detection signal Sa is sent 8 ms later.

[0006]

The above-mentioned conventional digital data instantaneous interruption detection circuit sends out the data instantaneous interruption detection signal when the mismatch counter 3 counts eight times, that is, 8 ms after the PCM voice data is instantaneously interrupted. To do. However, when suppressing a voice signal by this data interruption detection signal,
Since the noise generated after the PCM voice data is momentarily interrupted increases with time, it is necessary to shorten the time from the momentary interruption of the PCM voice data to the transmission of the data momentary interruption detection signal. However, since the count numbers of the coincidence counter 2 and the non-coincidence counter 3 are set according to the synchronization protection characteristics of the frame counter 4, they cannot be arbitrarily changed and have no degree of freedom. Therefore, there is a problem that the time from the momentary interruption of the PCM voice data to the transmission of the data momentary interruption detection signal cannot be shortened. An object of the present invention is to provide a digital data momentary interruption detection circuit which shortens the time from the momentary interruption of digital data to the transmission of the data momentary interruption detection signal and which operates stably even under a low C / N. To do.

[0007]

According to the present invention, a frame sync protection circuit for protecting a sync signal according to a frame sync pattern included in received digital data at a predetermined cycle detects a frame sync pattern by correlation and coincidence to generate a detection pulse. Correlation pattern synchronization detector, a mismatch detector that generates a mismatch signal based on the inverted signal of this detection pulse and the frame synchronization pattern search position pulse obtained from the frame synchronization protection circuit And a circuit that outputs a detection signal.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.
The same parts as those of the conventional digital data instantaneous interruption detecting circuit shown in FIG. 2 is different from FIG. 2 in that the correlation pattern synchronization detector 9 detects a frame synchronization pattern included in the data Si by, for example, a correlation pattern that is regarded as frame synchronization when 12 bits or more out of 16 bits match, and generates a detection pulse Pe. The inverter 10 for inverting the detection pulse Pe and the mismatch detector 11 for generating the mismatch signal C3 based on the inverted signal Pf and the search position pulse of the frame synchronization pattern obtained from the frame synchronization protection circuit are provided. That is, the flip-flop 8 is configured to be set.

The correlation pattern synchronization detector 9 is a PCM.
If the frame synchronization pattern composed of 16 bits included in the audio data Si at a period of 1 ms matches 12 bits or more, it is regarded as a synchronization signal and the detection pulse Pe is output.
The non-coincidence detector 11 compares the inversion signal Pf obtained through the inverter 10 with the synchronization pulse Ps from the frame counter 4 to detect the non-coincidence signal C3 of the synchronization pattern.

According to this structure, the PCM voice data Si
When there is a momentary interruption, the sync pattern disappears, so the discrepancy detector 11 uses the sync pulse cycle of 1 m from the frame counter 4.
The mismatch signal C3 is detected within s, and the flip-flop 8
Set. Therefore, the data instantaneous interruption detection signal Sa can be obtained via the flip-flop 8 within 1 ms after the instantaneous interruption of the PCM audio data Si. The purpose of using the correlation pattern synchronization detector 9 is to slow down the synchronization detection sensitivity with respect to the frame synchronization pattern error at low C / N. This prevents the data instantaneous interruption detection signal Sa from being erroneously generated when the C / N is low.

[0011]

As described above, according to the present invention, the inversion signal of the detection pulse obtained by the correlation coincidence detection of the frame synchronization pattern and the search position pulse of the frame synchronization pattern obtained by the frame synchronization protection circuit are provided. Since the data interruption detection signal is output based on the disagreement, the time from the momentary interruption of the PCM audio data to the transmission of the data interruption detection signal can be shortened within one frame, and the noise after the interruption is effective. Can be suppressed to. Further, by detecting the correlation coincidence of the frame synchronization pattern, it is possible to obtain a digital data instantaneous interruption detection circuit which operates stably even under a low C / N.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a digital data instantaneous interruption detection circuit of the present invention.

FIG. 2 is a block diagram of an example of a conventional digital data instantaneous interruption detection circuit.

FIG. 3 is a diagram showing a timing of a data instantaneous interruption detection signal.

[Explanation of symbols]

 1 Sync Detector 2 Match Counter 3 Mismatch Counter 4 Frame Counter 5,8 Flip Flop 6 OR Gate 7 AND Gate 9 Correlation Pattern Sync Detector 10 Inverter

Claims (2)

[Claims] 1. A digital data instantaneous interruption detection circuit having a frame synchronization protection circuit for protecting a synchronization signal according to a frame synchronization pattern included in received digital data at a predetermined cycle, and detecting a correlation pulse of the frame synchronization pattern to detect a detection pulse. A correlation pattern synchronization detector to generate, a non-coincidence detector that generates a non-coincidence signal based on the inverted signal of the detection pulse and the search position pulse of the frame synchronization pattern obtained from the frame synchronization protection circuit, and in response to the non-coincidence signal. A digital data instantaneous interruption detection circuit comprising: a circuit for outputting an instantaneous data interruption detection signal. 2. A frame synchronization protection circuit detects a frame synchronization pattern included in received digital data at a predetermined cycle and sends a detection pulse, and a frame synchronization pattern at the same cycle as the received frame synchronization. , A frame counter that outputs a synchronization pulse synchronized with this, a coincidence counter that compares the detection pulse with the synchronization pulse and counts the number of coincidences, and a mismatch counter that compares the detection pulse with the synchronization pulse and counts the number of disagreements 2. The digital data instantaneous interruption detection circuit according to claim 1, further comprising: