JP2747994B2 - Pseudo random signal synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a pseudo-random signal (PN signal) such as spread spectrum communication (SSRA).
The present invention relates to a synchronization circuit used for a receiver of a communication system using the same. In particular, the present invention relates to a synchronization circuit suitable for a measuring instrument for measuring a radio wave propagation characteristic in mobile communication of the communication system.

[0002]

2. Description of the Related Art Radio wave propagation characteristics in mobile communications are measured by continuously and repeatedly transmitting pseudo-random signals (hereinafter referred to as PN signals) and measuring the reception characteristics. This measurement is performed mainly for the purpose of measuring the effect of fading in the mobile radio, but the PN signal reproduced on the receiving side is used as a reference for measuring the bit error rate of the received PN signal or measuring the delay profile. Therefore, it is required that errors are small and the time is stable. For this purpose, it is necessary that the pseudo-random signal synchronization circuit be stably synchronized.

FIG. 2 shows a conventional example of the present invention. Conventionally, P
The N signal synchronizing circuit includes a PN signal reproducing circuit and a reproduced P signal.
A synchronization judgment circuit for comparing the N signal with a PN signal in the received NRZ signal to judge whether or not synchronization has been achieved. When the synchronization judgment circuit judges that synchronization has been lost, a PN signal is output. A method of resynchronizing the signal reproducing circuit has been used.

In FIG. 2, the received NRZ signal is P
The signal is input to the N signal reproducing circuit 1. The output of the PN signal reproduction circuit is connected to the synchronization determination circuit 2, and in this circuit, when synchronization is established, the electronic switch 8 selects the S1 side,
If synchronization is not established, control signal X for selecting S2 side
Issue ₂ . When the switch has selected the side S1, the output X ₁₀ of the shift register 10 is inputted to the gate circuit 9 which calculates according to a predetermined rule, the output X ₉ is fed back to the shift register again. (The type of PN signal used differs for each line, and is the same as the PN signal used for transmission.
A signal is generated at the receiving end and used for line identification and separation. )

[0005] Circuit 10, circuit 9 and its output circuit 10
The feedback circuit forms a PN signal generation circuit as a whole, and the output X ₉ coincides with the PN signal X ₀ of the received NRZ signal in a state where synchronization is established.

The synchronization determination circuit 2 determines whether or not synchronization has been achieved by comparing X ₀ and X ₉ . The two are compared by an adder (exclusive OR circuit) 11,
In the case of a mismatch, the “1” output is connected to the resistor 12 and the capacitor 1
3 is integrated by a time constant circuit consisting of
Compared to ₁ . In the synchronized state, the output of the adder 11 is always "0", so that the output of the comparator 14 is "0". FIG. 3 is a waveform diagram showing the above operation.

The electronic switch 8 is switched according to the determination result X ₂ , and switches to S ₂ when synchronization is lost. For switch S2, it captures the received signal X ₀ to the shift register, resynchronize the PN signal reproduction circuit. Here, if the received NRZ signal does not include an error, the contents of the shift register 10 are all the received NRZ signals.
Is replaced by the signal, X ₉ and X ₀ matches, so that the synchronization is established. (Hereafter, since X ₉ and X ₀ match, X
₁₁ "0" is followed, X ₂ is "0", the switch 8 is selected S _1, continue to play a PN signal in sync as circuits. )

However, in this conventional example, if fading occurs frequently and an error occurs in a received NRZ signal as in mobile radio, it is assumed that synchronization is lost each time, although time synchronization is achieved. Judgment will be made and synchronization will be restored. Then, as a result of inputting an erroneous received signal into the shift register 10, the shift register 10 is in an asynchronous state, and there is a disadvantage that the propagation characteristics cannot be measured stably. Especially in mobile communications, it is important to clarify the degradation characteristics of communication quality due to fading, but it is practically impossible to measure propagation characteristics in important situations in measuring propagation characteristics where severe fading is occurring. There was a disadvantage.

[0009]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a measuring instrument capable of stably measuring a propagation characteristic even in an environment where fading has fluctuated, which has been impossible in the past. An object of the present invention is to provide a receiver that does not easily lose synchronization in a short-time fading fluctuation.

Further, even if the propagation path is very complicated and multipath fading occurs, there is provided a receiver capable of synchronizing a reproduced PN signal with a received signal passing through the shortest path. The purpose is to:

[0011]

A pseudo-random signal (PN signal) synchronizing circuit according to the present invention comprises a pseudo-random signal (PN signal) reproducing means for reproducing a pseudo-random signal (PN signal) from a received data signal; A synchronization determining means for determining whether or not a pseudo random signal (PN signal) is synchronized by comparing an output of a signal (PN signal) reproducing means with the received data signal; The pseudo random signal (PN
Signal) is provided for monitoring whether or not a pseudo-random signal (PN signal) has been lost by the synchronization determining means. When it is confirmed that the received signal is correctly received, a synchronization correcting operation for synchronizing the pseudo random signal (PN signal) reproducing means with the pseudo random signal (PN signal) in the received data signal is performed.

Further, a time advance detecting circuit for comparing the time relationship between the pseudo random signal (PN signal) in the received data signal and the output of the pseudo random signal (PN signal) reproducing means is provided, When it is detected that the pseudo random signal (PN signal) is ahead of the output of the pseudo random signal (PN signal) reproducing means, the synchronization correction operation is immediately performed, and the pseudo random signal (PN) in the received data signal is detected. When it is detected that the PN signal) is delayed from the output of the pseudo random signal (PN signal) reproducing means, the synchronization correction operation is performed after a predetermined time constant.

In the operation, the pseudo random signal (PN signal) in the received data signal and the output of the pseudo random signal (PN signal) reproducing means are input to a pattern matching circuit, respectively. When a predetermined pseudo random signal (PN signal) is matched, a matching pulse is issued, and the determination time constant of the reception state determination circuit is changed according to the temporal order of the respective matching pulses.

[0014]

FIG. 1 is a diagram showing an embodiment of the present invention. In FIG. 1, as in FIG.
The Z signal is input to a PN signal reproduction circuit 1 and connected to a synchronization determination circuit 2. In the circuit, the electronic switch 8 if the synchronization is selects the side S1, if not synchronized issue a control signal X ₂ for selecting the side S2. When the switch selects the S1 side, the shift register 10
The gate circuit 9 outputs X ₁₀ is for calculating according to a predetermined rule of
And the output X ₉ is fed back to the shift register again.

The synchronization determination circuit 2 determines whether or not synchronization has been achieved by comparing X ₀ and X ₉ . The two are compared by an adder (exclusive OR circuit) 11,
In the case of a mismatch, the “1” output is connected to the resistor 12 and the capacitor 1
3 is integrated by a time constant circuit consisting of
Compared to ₁ . In the synchronized state, the output of the adder 11 is always "0", so that the output of the comparator 14 is "0".

When the synchronization is lost, the output of the comparator 14 becomes "1", and when the AND gate 4 is open, the switch is switched to the S2 side. If the switch is on the S2 side,
Captures the received signal X ₀ to the shift register, resynchronize the PN signal reproduction circuit.

FIG. 1 shows a reception monitoring circuit 3 in addition to the configuration of FIG.
Has been added. The output X ₃ of the monitoring circuit is input to the AND gate 4 together with the output X ₂ , and the control signal X 3
Generate ₄ Therefore, unlike FIG. 2, the control signal X ₄ is controlling the electronic switch. Thus, even if it is determined that the synchronization is lost in the synchronization decision circuit 2, as long as the output X ₃ for the reception monitoring circuit does not become "1", the switch will not be switched to the side S2.

The reception state monitoring circuit 3 comprises a PN signal detection circuit 5, a time advance detection circuit 6, and a reception signal judgment circuit 7. The PN signal detection circuit 5 includes the shift register 1
5, a gate circuit 16 and an adder 17 (exclusive OR circuit).

Shift register 15 and gate circuit 16
Complies with the same rules as the shift register 10 and the gate circuit 9 in the PN signal reproducing circuit 1, and when the PN signal is being received, the output X ₁₆ of the gate circuit 16 matches the received NRZ signal X ₀ . At this time, the output of the adder (exclusive OR circuit) 17 is “0”. The time advance detection circuit 6 checks the time relationship between the PN signal of the received NRZ signal X ₀ and the output X ₁ of the PN signal reproduction circuit 1. When the electronic switch 8 selects S1, the time relationship between X ₀ and X ₁ is nothing but the time relationship between the shift register 15 and the shift register 10.

The pattern matching circuit detects whether or not the pattern matches the same pattern. When the contents of the shift registers 10 and 15 match the specific pattern, the match pulse X ₁₉ , which indicates a pattern match, is detected. issue X _18.

The operation of the time advance detection circuit 6 will be described below with reference to FIG. Now, when X ₁₉ outputs a pulse earlier than X ₁₈ , the counter 20 is reset at X ₁₉ before the counter outputs, so the flip-flop 2
The output of 1 remains in the "0" state. On the other hand, when the direction of X ₁₈ issues a faster pulse than X _19, from the come pulse of X ₁₈ is until it is reset by X _19, counter output is "1"
, The output of the flip-flop 21 is in the “1” state.

Next, the operation state of each circuit with respect to time will be described with reference to FIG. Receiving state judgment circuit 7 checks the output X ₅ of the PN signal detecting circuit 5, when it is determined that the predetermined time or more PN signal is being sent, the output X ₇ "1"
To That is, in the circuit, the output X ₅ of the PN signal detection circuit 5, the diode 22, resistor 23, 24 and enters the time constant circuit composed of a capacitor 25, is compared with a predetermined value V ₂ in a comparator 26 with its output. The time constant of the receiver decision circuit 7 is controlled by the output X ₆ time proceeds detecting circuit changes. The value of each of the above resistors is represented by the following equation.
て い る It is set like the resistor 23. Therefore, the combination of the resistor 24 and the capacitor 25 has the shortest time constant, the combination of the resistor 28 and the capacitor 25 has the longest, and the combination of the resistor 23 and the capacitor 25 has the longest time constant.

The receiving electric field is sufficiently large and the PN signal is incorrect.
When it is received well. Output X of PN signal detection circuit 5
_FiveIs "0", and the output "1" is output from the comparator 26.
It is. However, at this time, the output of the synchronization determination circuit 2 is
Because of "0", the output X is output to the AND gate 4._FourIs "0"
The electronic switch is kept in the selected state with S1 selected.
You. That is, there is no need to resynchronize. Received electric field
As it goes down, the adder output X gradually_FiveIs due to disagreement
"1" starts to increase. At this time, charge the capacitor
The diode 22 is conducting because it is not
The short time constant circuit of the resistor 24 and the capacitor 25 works.
The output X of the reception state judgment circuit₇Is X_TwoFaster than response
Outputs “0” output and keeps the output for a period determined by the time constant.
Be held. Here, when the received electric field increases again, X_Five
Becomes "0", and the diode 22 is turned off. I
Therefore, the time constant is determined by the resistor 23 and the capacitor 25.
And suddenly X ₇Does not return to “1”.

On the other hand, if the received NRZ signal PN signal enters stable, time proceeds circuit accurately detects the time relationship between X ₁₈ and X _19. Here, if X ₁₈ is earlier than X ₁₉ , X ₆ becomes “1” and the electronic switch 27
Is turned on, and the low resistance 28 is connected in parallel to the time constant circuit, so that the time constant of the circuit is shortened.

Therefore, X ₂₅ returns to the “0” state at an early stage, and the reception state monitoring circuit switches the AND gate 4 for re-synchronizing operation of the PN signal reproduction circuit 1 in response to the output of the synchronization judgment circuit 2. A signal that opens X ₃ = “1” is output.

However, if X ₁₈ is later than X ₁₉ , the electronic switch 27 is OFF, and only the resistor 23 and the capacitor 25 are provided, and the time constant is very long, so that X ₂₅ returns to the “0” state. take time. Therefore, even if an output occurs in the synchronization determination circuit 2, the reception state monitoring circuit
The re-synchronization operation of the signal reproducing circuit 1 is not easily permitted.

By doing so, even if the synchronization determination circuit determines the loss of synchronization, the synchronization correction circuit does not immediately start the synchronization correction operation until a predetermined PN signal is detected in the received NRZ signal. Even in such an environment where the received electric field strength fluctuates frequently, it is possible to eliminate the situation where the synchronization correction operation occurs frequently and the measurement of the propagation characteristics becomes impossible. The synchronization correction is positively performed when the received PN signal is temporally ahead of the reproduced PN signal. This means that, in the multipath fading state, it synchronizes with the received signal that has passed through the shortest path.

[0028]

As described above, according to the present invention, even if the radio wave propagation environment is poor, the synchronization of the PN signal can be stably ensured. Measurement of the error rate and the like can be continued.

In order to synchronize with the path having the shortest delay time among propagation delays due to multipath, the reproduced PN signal can be used as a time coordinate axis for measuring a delay profile or the like.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a conventional synchronization correction circuit.

FIG. 3 is a diagram showing an operation of a conventional synchronous correction.

FIG. 4 is a diagram illustrating an operation of a time advance detection circuit.

FIG. 5 is a diagram showing an operation state of each circuit with respect to time according to the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 PN signal reproduction circuit 2 synchronization judgment circuit 3 reception state monitoring circuit 4 AND circuit 5 PN signal detection circuit 6 time advance detection circuit 7 reception state judgment circuit 8 electronic switch 9 gate circuit 10 shift register 11 adder (exclusive OR circuit) 14) comparator 15 shift register 16 gate circuit 17 adder (exclusive OR circuit) 18, 19 pattern match circuit 20 counter 21 flip-flop 26 comparator 27 electronic switch

Claims (3)

(57) [Claims] 1. A receiving apparatus for receiving a pseudo-random signal (PN signal) repeatedly transmitted, comprising: a pseudo-random signal (PN signal) reproducing means for reproducing a pseudo-random signal (PN signal) from a received data signal; Synchronization determining means for determining whether or not the pseudo random signal (PN signal) is synchronized by comparing the output of the random signal (PN signal) reproducing means with the received data signal; A receiving state monitoring means for checking whether or not the pseudo random signal (PN signal) is correctly received; determining that the synchronization is out of synchronization by the synchronization determining means; When it is confirmed that the pseudo random signal (PN signal) is correctly received, the pseudo random signal (PN signal) is reproduced. Pseudo random signal synchronization circuit, characterized in that to perform the synchronization corrective action to synchronize the stage pseudo random signal (PN signal) in the received data signal. 2. A time advance detecting circuit for comparing a time relationship between a pseudo random signal (PN signal) in the received data signal and an output of the pseudo random signal (PN signal) reproducing means, Pseudo random signal (PN signal)
Is detected to be ahead of the output of the pseudo random signal (PN signal) reproducing means, the synchronization correction operation is immediately performed, and the pseudo random signal (PN signal) in the received data signal is changed to the pseudo random signal (PN signal). 2. The pseudo-random signal synchronization according to claim 1, wherein when it is detected that the output is delayed from the output of the signal (PN signal) reproduction means, the synchronization correction operation is performed after applying a predetermined time constant. circuit. 3. A pseudo-random signal (PN signal) in the received data signal and an output of the pseudo-random signal (PN signal) reproducing means are respectively input to a pattern matching circuit. When a coincidence with the pseudo random signal (PN signal) occurs, a coincidence pulse is issued, and according to the temporal context of the respective coincidence pulses,
3. The pseudo random signal synchronization circuit according to claim 2, wherein a judgment time constant of the reception state judgment circuit is changed.