CN113064342B - Digital multi-beam signal processing system and time synchronization method - Google Patents
Digital multi-beam signal processing system and time synchronization method Download PDFInfo
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- CN113064342B CN113064342B CN202110279861.8A CN202110279861A CN113064342B CN 113064342 B CN113064342 B CN 113064342B CN 202110279861 A CN202110279861 A CN 202110279861A CN 113064342 B CN113064342 B CN 113064342B
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- G—PHYSICS
- G04—HOROLOGY
- G04R—RADIO-CONTROLLED TIME-PIECES
- G04R40/00—Correcting the clock frequency
- G04R40/06—Correcting the clock frequency by computing the time value implied by the radio signal
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
Abstract
The invention discloses a time synchronization method of a digital multi-beam signal processing system, which comprises the steps of obtaining homologous 1PPS signals, and acting the 1PPS signals on a main control FPGA 0; generating a first interrupt signal and a second interrupt signal; configuring a first frame number of the main control FPGA0, reading back a second frame number of the main control FPGA0, judging whether the first frame number is consistent with the second frame number, and if so, matching the first frame number with the second frame number to be a synchronous frame number; configuring a synchronous frame number to the sub FPGA to obtain a first sub synchronous frame number, and detecting whether the first sub synchronous frame number is consistent with a synchronous frame number wireless frame terminal or not; configuring a synchronous frame number to the sub FPGA through SPI total broadcasting to obtain a second sub synchronous frame number of the sub FPGA; reading back a second sub-synchronous frame number of the sub-FPGA in a backboard polling mode, comparing the second sub-synchronous frame number with the synchronous frame number, and if the comparison is consistent, successfully synchronizing the system time; the invention has the advantages of synchronizing the time of the digital multi-beam signal processing system and the signal frames on each FPGA board, and reducing the information frames between the sub-FPGAs without frame loss and errors.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a digital multi-beam signal processing system and a time synchronization method.
Background
When digital signals are processed in a large phased array multi-beam system, a plurality of FPGA resources are often required to work cooperatively to complete large-capacity signal and data processing, but the performance of the system is directly influenced by the signal and frame number time sequence synchronization and the like among the FPGA board cards when the digital signals are processed, a high-precision clock is often used as a time reference in the previous multi-beam signal processing system, a time reference is provided for each board card, the high requirement on the precision of a 10M clock is provided, and the further guidance and reference significance can not be provided for the frame synchronization of each FPGA.
Disclosure of Invention
The invention aims to provide a digital multi-beam signal processing system and a time synchronization method, which realize the time synchronization method of the system by configuring a synchronization frame number on a main control FPGA0 and configuring a corresponding synchronization frame number to a sub-FPGA through a main control FPGA 0.
The invention is realized by the following technical scheme:
a time synchronization method for digital multi-beam signal processing system includes
S1: acquiring homologous 1PPS signals, and applying the 1PPS signals to the main control FPGA 0;
s2: the main control FPGA0 generates a first interrupt signal and a second interrupt signal according to the 1PPS signal;
s3: configuring a first frame number of the main control FPGA0 according to the first interrupt signal, reading back a second frame number of the main control FPGA0 according to the second interrupt signal, judging whether the first frame number is consistent with the second frame number, if so, taking the first frame number and the second frame number as synchronous frame numbers, and entering step S4, otherwise, repeating the steps S1-S3;
s4: configuring a synchronous frame number to the sub-FPGA through the main control FPGA0 to obtain a first sub-synchronous frame number, detecting whether the first sub-synchronous frame number is consistent with a wireless frame terminal of the synchronous frame number, if so, successfully synchronizing the system time, otherwise, entering the step S5;
s5: configuring a synchronous frame number to the sub-FPGA through SPI total broadcasting when the main control FPGA0 wireless frame is in the second time slot, and obtaining a second sub-synchronous frame number of the sub-FPGA;
s6: and reading back the second sub-synchronous frame number of the sub-FPGA in a backboard polling mode, comparing the second sub-synchronous frame number with the synchronous frame number, if the second sub-synchronous frame number is consistent with the synchronous frame number, successfully synchronizing the system time, and otherwise, repeating the steps S1-S6.
In a traditional multi-beam system, a high-precision clock is used as a time reference to provide a time reference for each board card during digital signal processing, but in the using process of the method, the requirement on the high-precision clock is high usually, the manufacturing cost is high, and no effect is brought to frame synchronization among the FPGA boards.
Preferably, in the step S3, the specific method for configuring the first frame number of the master control FPGA0 includes:
initializing according to a frame signal of the main control FPGA 0;
and performing information distribution on the initialized frame signal and the frame head by taking the state of the first interrupt signal as a reference.
Preferably, the specific method for reading back the second sub-synchronization frame number of the sub-FPGA in the backplane polling manner includes:
and when the fourth time slot of the wireless frame of the main control FPGA0, a backboard polling mode is adopted, and the second sub-synchronous frame number of the sub-FPGA is read back through the SPI bus by taking the time slot as granularity.
Preferably, the first interrupt signal includes a first frame interrupt signal and a first slot interrupt signal.
Preferably, the second interrupt signal includes a second frame interrupt signal and a second slot interrupt signal.
The invention also discloses a digital multi-beam signal processing system, which comprises a time synchronization system;
the comprehensive processor is used for acquiring homologous 1PPS signals, acting the 1PPS signals on the main control FPGA0, and configuring frame numbers to the main control FPGA0 according to signals fed back by the main control FPGA 0;
the main control FPGA0 is used for generating a first interrupt signal and a second interrupt signal, feeding the first interrupt signal and the second interrupt signal back to the integrated processor, receiving a frame number configured by the integrated processor, matching a synchronous frame number, configuring the synchronous frame number to the sub-FPGA, and detecting whether the sub-synchronous frame number of the sub-FPGA is consistent with the synchronous frame number of the main control FPGA 0;
the sub FPGA is used for receiving the frame number configured by the main control FPGA0 and realizing the frame number synchronization with the main control FPGA 0;
and the back plate is used for connecting the main control FPGA with the sub-FPGAs through a lead.
Preferably, the time synchronization system comprises a plurality of sub-FPGAs.
By adopting the system provided by the invention, the synchronous frame numbers can be configured to a plurality of sub-FPGAs through the main control FPGA0, and real-time configuration transmission can be realized.
Compared with the prior art, the invention has the following advantages and beneficial effects:
by adopting the digital multi-beam signal processing system and the time synchronization method provided by the invention, the synchronization frame number is configured for the main control FPGA0, and the signal frames of the sub-FPGAs are synchronously matched through the main control FPGA0, so that the time of the digital multi-beam signal processing system and the signal frames on each FPGA board are synchronized, and the occurrence of frame loss and errors of the information frames between the sub-FPGAs can be reduced.
According to the time synchronization method provided by the invention, the FPGA of a certain main control board is selected as a reference mode, so that the interconnection and interaction between the system and the outside can be reduced, the throughput and the synchronization time of data in the synchronization process are reduced, and the synchronization precision of the system is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:
FIG. 1 is a schematic diagram of a time synchronization method
FIG. 2 is a system diagram
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples and accompanying drawings, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not meant to limit the present invention.
Example one
The embodiment discloses a time synchronization method for a digital multi-beam signal processing system, which comprises the following steps as shown in figure 1
S1: acquiring homologous 1PPS signals, and applying the 1PPS signals to the main control FPGA 0;
the same source 1 PPS-sec pulse signal is used as the synchronization pulse information, and 122.88M clock is used as the pulse acquisition clock.
S2: the main control FPGA0 generates a first interrupt signal and a second interrupt signal according to the 1PPS signal;
the first interrupt signal comprises a first frame interrupt signal and a first slot interrupt signal; the second interrupt signal includes a second frame interrupt signal and a second slot interrupt signal.
When the 1PPS second pulse signal acts on the main control FPGA0, the main control FPGA0 generates a frame interrupt signal and a slot interrupt signal under the action of the 1PPS second pulse signal, and the generated frame interrupt signal and slot interrupt signal are used for configuring a synchronization signal for the main control FPGA0, when a plurality of 1PPS second pulse signals act on the main control FPGA0, the main control FPGA0 generates different frame interrupt signals and slot interrupt signals, and the secondarily generated frame interrupt signal and slot interrupt signal are used for reading back the synchronization frame number generated by the main control FPGA0 and comparing the frame interrupt signals and the slot interrupt signals.
Frame interrupt signal is a method for microprocessor and peripheral equipment to carry out input/output control, the frame interrupt is that when the data frame length is used as interval, when the exchanger receives the head of a data frame, the exchanger only needs to find out the destination address of the frame, and then starts to forward the frame, and the time slot interrupt is that the time slot length is used as interval to carry out packet exchange.
S3: configuring a first frame number of the main control FPGA0 according to the first interrupt signal, reading back a second frame number of the main control FPGA0 according to the second interrupt signal, judging whether the first frame number is consistent with the second frame number, if so, taking the first frame number and the second frame number as synchronous frame numbers, and entering step S4, otherwise, repeating the steps S1-S3;
and reading back the second frame number of the master FPGA0 according to the feedback of the master FPGA 0.
The step is mainly to match the synchronous frame number of the main control FPGA0, and the matched synchronous frame number can control the sub-FPGAs through the main control FPGA0, so that the synchronous frame number on each sub-FPGA is synchronized with the frame number on the main control FPGA 0.
In step S3, the specific method for configuring the first frame number of the master control FPGA0 includes:
initializing according to a frame signal of the main control FPGA 0; and performing information distribution on the initialized frame signal and the frame head by taking the state of the first interrupt signal as a reference.
S4: configuring a synchronous frame number to the sub-FPGA through the main control FPGA0 to obtain a first sub-synchronous frame number, detecting whether the first sub-synchronous frame number is consistent with a wireless frame terminal of the synchronous frame number, if so, successfully synchronizing the system time, otherwise, entering the step S5;
after the configuration of the main control FPGA0 on the sync frame number of the sub FPGA is completed, the first sub sync frame number on the sub FPGA needs to be compared with the sync frame number on the main control FPGA0, and if the comparison is consistent, the system time synchronization is successful, and if the comparison is inconsistent, the next operation needs to be performed.
S5: configuring a synchronous frame number to the sub-FPGA through SPI bus broadcasting when the main control FPGA0 wireless frame is in the second time slot, and obtaining a second sub-synchronous frame number of the sub-FPGA;
when the synchronous frame number is configured to the sub FPGA through SPI bus broadcasting, an initialization process is firstly carried out, and parameter setting is carried out according to the second time slot time state of the SPI bus ship.
S6: and reading back the second sub-synchronous frame number of the sub-FPGA in a backboard polling mode, comparing the second sub-synchronous frame number with the synchronous frame number, if the second sub-synchronous frame number is consistent with the synchronous frame number, successfully synchronizing the system time, and otherwise, repeating the steps S1-S6.
The specific method for reading back the second sub-synchronous frame number of the sub-FPGA in a backboard polling mode comprises the following steps:
and when the fourth time slot of the wireless frame of the main control FPGA0, a backboard polling mode is adopted, and the second sub-synchronous frame number of the sub-FPGA is read back through the SPI bus by taking the time slot as granularity.
And polling by the backboard, wherein the processing boards where each FPGA is located are interconnected and communicated through the backboard, namely, the boards are synchronized and configured in a time division manner, and the time division manner refers to the periodic configuration of the boards according to a time sequence.
Example two
The present embodiment discloses a digital multi-beam signal processing system capable of implementing a time synchronization method according to an embodiment based on the first embodiment, as shown in fig. 2, the system includes;
the comprehensive processor is used for acquiring homologous 1PPS signals, acting the 1PPS signals on the main control FPGA0, and configuring frame numbers to the main control FPGA0 according to signals fed back by the main control FPGA 0;
in the multi-beam signal processing system, all hardware boards inside the multi-beam signal processing system are provided with a homologous 1PPS (pulse per second) and used as synchronous pulse information, a 122.88M clock is used as a pulse acquisition clock, when a 1PPS pulse signal is sent to each FPGA board, the FPGA on the processing board generates a frame interrupt signal and a time slot interrupt signal, and feeds the generated frame interrupt signal and time slot interrupt signal back to the comprehensive processor for processing by the comprehensive processor;
when the integrated processor receives the frame interrupt signal and the time slot interrupt signal of the processing board, a first frame number is configured to the main control FPGA0 according to the received feedback signal, a second frame number on the main control FPGA0 is read back according to the transmitted second frame interrupt signal and the time slot interrupt signal, whether the first frame number is consistent with the second frame number is detected, if so, the matching is successful, the first frame number and the second frame number are simultaneously used as synchronous frame numbers, and if not, the matching is not successful, the synchronous frame number matching of the main control FPGA0 needs to be repeated.
The main control FPGA0 is used for generating a first interrupt signal and a second interrupt signal, feeding the first interrupt signal and the second interrupt signal back to the integrated processor, receiving a frame number configured by the integrated processor, matching a synchronous frame number, configuring the synchronous frame number to the sub-FPGA, and detecting whether the sub-synchronous frame number of the sub-FPGA is consistent with the synchronous frame number of the main control FPGA 0;
after the matching of the frame numbers is completed, the main control FPGA0 matches the matched frame numbers to the sub-FPGA board in a signal transmission manner, and the main control FPGA reads the sub-synchronization frame numbers on the sub-FPGA within time, and compares the sub-synchronization frame numbers with the synchronization frame numbers, if the sub-synchronization frame numbers are consistent with the synchronization frame numbers, the frame signal synchronization of the system is successful, and if the sub-synchronization frame numbers are inconsistent with the synchronization frame numbers, the frame number information synchronization of the system is unsuccessful.
The sub FPGA is used for receiving the frame number configured by the main control FPGA0 and realizing the frame number synchronization with the main control FPGA 0;
and the back plate is used for connecting the main control FPGA with the sub-FPGAs through a lead. The time synchronization system comprises a plurality of sub-FPGAs.
The connections between the master FPGA0 and the sub FPGAs are wired, but they are made by connecting the individual FPGA boards through a backplane.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (7)
1. A method for time synchronization in a digital multi-beam signal processing system, comprising
S1: acquiring homologous 1PPS signals, and applying the 1PPS signals to the main control FPGA 0;
s2: the main control FPGA0 generates a first interrupt signal and a continuous second interrupt signal according to the 1PPS signal;
s3: configuring a first frame number of the main control FPGA0 according to the first interrupt signal, reading back a second frame number of the main control FPGA0 according to the second interrupt signal, judging whether the first frame number is consistent with the second frame number, if so, taking the first frame number and the second frame number as synchronous frame numbers, and entering step S4, otherwise, repeating the steps S1-S3;
s4: configuring a synchronous frame number to the sub-FPGA through the main control FPGA0 to obtain a first sub-synchronous frame number, detecting whether the first sub-synchronous frame number is consistent with a wireless frame terminal of the synchronous frame number, if so, successfully synchronizing the system time, otherwise, entering the step S5;
s5: configuring a synchronous frame number to the sub-FPGA through SPI total broadcasting when the main control FPGA0 wireless frame is in the second time slot, and obtaining a second sub-synchronous frame number of the sub-FPGA;
s6: and reading back the second sub-synchronous frame number of the sub-FPGA in a backboard polling mode, comparing the second sub-synchronous frame number with the synchronous frame number, if the second sub-synchronous frame number is consistent with the synchronous frame number, successfully synchronizing the system time, and otherwise, repeating the steps S1-S6.
2. The method according to claim 1, wherein the specific method step of configuring the first frame number of the master FPGA0 in S3 comprises:
initializing according to a frame signal of the main control FPGA 0;
and performing information distribution on the initialized frame signal and the frame head by taking the state of the first interrupt signal as a reference.
3. The method according to claim 2, wherein the specific method of reading back the second subframe number of the sub-FPGA in a backplane polling manner is:
and when the fourth time slot of the wireless frame of the main control FPGA0, a backboard polling mode is adopted, and the second sub-synchronous frame number of the sub-FPGA is read back through the SPI bus by taking the time slot as granularity.
4. A method for time synchronization of a digital multi-beam signal processing system according to any of claims 1 to 3 wherein said first interrupt signal comprises a first frame interrupt signal and a first slot interrupt signal.
5. The method according to claim 4, wherein said second interrupt signal comprises a second frame interrupt signal and a second slot interrupt signal.
6. A digital multi-beam signal processing system, characterized in that it is adapted to implement the time synchronization method according to any one of claims 1 to 5, said system comprising;
the comprehensive processor is used for acquiring homologous 1PPS signals, acting the 1PPS signals on the main control FPGA0, and configuring frame numbers to the main control FPGA0 according to signals fed back by the main control FPGA 0;
the main control FPGA0 is used for generating a first interrupt signal and a second interrupt signal, feeding the first interrupt signal and the second interrupt signal back to the integrated processor, receiving a frame number configured by the integrated processor, matching a synchronous frame number, configuring the synchronous frame number to the sub-FPGA, and detecting whether the sub-synchronous frame number of the sub-FPGA is consistent with the synchronous frame number of the main control FPGA 0;
the sub FPGA is used for receiving the frame number configured by the main control FPGA0 and realizing the frame number synchronization with the main control FPGA 0;
and the back board is used for connecting the main control FPGA0 with the sub-FPGAs through a lead.
7. A digital multi-beam signal processing system according to claim 6, characterized in that said system comprises several sub-FPGAs.
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