JPH05111083A - Inter-device synchronism settling system - Google Patents

Abstract

PURPOSE:To allow a slave device to highly reliably receive data for the device itself from time-divided multiplexed serial data even when a system is switched or disturbance is generated in a synchronizing signal generated from a master device in a doubled synchronism settling system among the master device and plural slave devices. CONSTITUTION:Each SLC has a bit synchronizing master clock counter 142, a frame synchronizing time slot counter 144, a multi-frame synchronizing frame counter 146 and a super multi-frame synchronizing multi-frame counter 148. These counters 142, 144, 146, 148 are driven synchronously with a master clock MCK, a frame clock FCK, a multi-frame clock MFCK, and a super multi-frame clock SMFCK generated from the SHC and the counters 144, 146, 148 respectively execute the counting of time slot numbers, frame numbers, and multi-frame numbers.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION In the present invention, a plurality of slave devices (lower devices) are self-selected from serial data of a plurality of channels which are time-division-multiplexed and sent from a redundant main device (upper device). The present invention relates to an inter-device synchronization establishment method for extracting data of a channel assigned to a device.

[0002]

2. Description of the Related Art Since a terminal system of a digital exchange is required to have high reliability, as shown in FIG. 5, SHC (Shelf Coupling) which is a common package for performing integrated control of shelves is shown.
mmon) is # 0 SHC20-0 and # 1 SHC20
-1, and when a failure occurs in the SHC of the active system, the SHC of the other standby system is switched to the active system, and as shown in FIG.
OM ₀ , LCOM ₁ , ... SLC ₀ , SLC ₁ , ... Which are subscriber line compatible packages under the control of LCOM _15.
・ For SLC ₇ (SLC; Subscriber Line Card)
A plurality of time-division-multiplexed serial data and various synchronization signals (timing clocks) necessary for extracting self-addressed data from the serial data are transmitted.

Each LOM _n (n = 0, 1, ... 15) is
As shown in FIG. 5, SHC 20-1 and 20-2 and 16 data buses (highways) DB0 _{0 to} DB 16 respectively
0 ₁₅ are connected in DB1 ₀ ～DB1 _15, the data bus _{DB0 n, DB1 n (n =} 0,1, ··· 15) , the
Between devices (SHC 20-1, 20-2 and each LCOM _{0 to} L
In order to reduce the number of signal lines between COM ₁₅ , time-division multiplexed (time sharing) signals for 8 lines (8 channels) (each channel signal is one time slot audio signal and 3
Transmission of time slot control signals). Further, each LCOM _n (n = 0, 1, ... 15) is an SHC
20-0, and SHC20-1, from SHC20-0,
20-1 and SLC ₀ , SLC ₁ , ..., SLC ₇ under the control of LCOM _n (n = 0, 1, ... 15) are required to establish a master clock (MCK) for establishing synchronization when exchanging data.
0, MCK1), frame clock (FCK0, FCK)
1), multi-frame clock (MFCK0, MFCK
1) and Super Multi Frame Clock (SMFC
K0, SMFCK1) is input.

As shown in FIG. 6, LCOM _n (n = 0,
1, ... 15) Subordinate SLC ₀ , SLC ₁ , ... S
LC ₇ is four types of clocks (timing clocks) MC sent from LCOM _n (n = 0, 1, ... 15)
K0 (MCK1), FCK0 '(FCK1'), MFC
K0 '(MFCK1'), SMFCK0 '(SMFCK
While synchronizing with 1 '), only the data assigned to each is extracted from the downlink highway (data bus (highway) DB shown in FIG. 6) and time-division multiplexed and transmitted to an uplink highway (not shown). ..

Further, in order to effectively use various information storage memory resources (not shown) in the SHC 20-0 (20-1), 16 data buses DB0 _{0 to} DB0 ₁₅ (DB1 ₀ to
As shown in FIG. 7, the DB1 ₁₅ ) transmits and receives data sequentially shifted every four time slots. That is, for example, LCOM ₀ is time slots 0 to 3 (# 0CC of line # 0 (channel 0)).
TCOM is received, LCOM ₁ receives time slots 28 to 31 of the line # 7 (channel 7) one frame before.
(# 7CCT) is received.

Here, the highway (data bus DB0₀
~ DB0₁₅, DB1₀~ DB1₁₅) Siri transmitted over
The format of the aldata is shown in FIG. Figure (g),
As shown in (h), one time slot TS_i(I = 0 to
31) is B ₀~ B₇8 bits (1 octet) of
And 32 more time slots TS₀~ TS₃₁By
1 frame F_j(J = 0 to 15) is configured ((e) in the figure)
 , (F)). And 16 frames F₀~ F₁₅By
1 multiframe MF_k(K = 0-5) is configured
(See (c) and (e) in the figure). And 6 more multi-frames
Super multi-frame SMF
(See Figures (a) and (c)).

One cycle of 1 bit is 488 ns (nanosecond)
It is a signal of seconds, that is, 2.048 MHz, and an MCK (master clock) having a frequency of 2.048 MHz is generated by the SHC 20-0 (20-1) in order to extract this bit information. Also, as described above, one time slot consists of 8 bits (1 octet), so one cycle is 3.9
It is 20625 μs (= about 8 × 488 ns), and similarly, 125 μ because one frame period consists of 32 time slots.
s (= 32 × 3.920625 μs), the cycle of one multiframe is 2 ms (125 μs × 16) because it consists of 16 frames, and the cycle of the super multiframe is 12 ms (= 2 ms × 6) because it consists of 6 multiframes.

The SHCs 20-0 and 20-1 are shown in (d), (b), and (a) of FIG. 125 for frame synchronization, multiframe synchronization, and supermultiframe synchronization, respectively.
Frame clock FCK (FCK0, FCK1) that generates a falling pulse at the beginning of the frame at μs intervals, 2
Multi-frame clock MFCK (MFCK0, which generates a falling pulse at the beginning of the multi-frame at ms intervals)
MFCK1), a super multi-frame clock SMFCK (SMFCK0, SMFCK) that generates a falling pulse at the beginning of the super multi-frame at 12 ms intervals
1) is generated.

By the way, as shown in FIGS. 9 (a) to 9 (d),
Each of the clocks SMFCK, MFCK, and FCK is a falling pulse whose pulse width is equal to one cycle (= 488 ns) of the master clock MCK.

By the way, as shown in FIG.
20-0, (20-1) to the data bus DB0, respectively
₀ , DB0 ₁ , ... DB0 ₁₅ (DB1 ₀ , DB1 ₁ ,
... LCOM ₀ , LCO via DB1 ₁₅ )
M _1, each line data transmitted to ··· LCOM ₁₅ (#
0CCT, # 1CCT, ... # 7CCT) are sequentially 4
Since each of the LCOM ₀ , LCOM ₁ , ..., LCOM ₁₅ is shifted and transmitted for each time slot, each LCOM ₀ , LCOM ₁ , ...
D), SMFCK ', MFCK', FCK 'whose generation timings are sequentially shifted by 4 time slots.
Each clock of SLC ₀ , SL under its own control
C _1, is supplied to the ··· SLC _7.

Here, SLC ₀ , SL under its control
C ₁ , ... SLC ₇ with the above FCK ', MFCK',
LCOM that supplies three types of SMFCK 'clocks
A block configuration of _n (n = 0 to 15) is shown in FIG.

As shown in the figure, each LCOM _n (n = 0
~ 15) one input terminal group I of the selector (SEL) 31
₀ to each data bus (highway) from SHC20-0
Data for eight lines (# 0CCT to # 7CCT) and four kinds of clocks MCK0, FCK0, MFCK0 and SMFCK0 time-division multiplexed on DB0 _{0 to} DB0 ₁₅ are input to the input terminal group I ₁ of many sides. Is each data bus (highway) DB1 _{0 to} D supplied from the SHC 20-1.
8 lines of data which are time division multiplexed on the B1 ₁₅ (# 0
CCT to # 7 CCT) and four types of clock MCK1,
FCK1, MFCK1 and SMFCK1 are input. The selector 31 includes an operation mode control circuit (ACT) 32.
A signal input to one of the input terminal group I _{0 and the} input terminal group I ₁ in accordance with a selection signal S added from the input signal group, that is, a signal group (DB0 ₀ to DB0 ₀ to DB0 ₁₅ , MCK0, FCK0, M
FCK0, SMFCK0) or a signal group (DB1 _{0 to} DB1 ₁₅ , MCK1, FC) supplied from SHC20-1.
Any one of the signal groups of K1, MFCK1 and SMFCK1) is selectively output. In this selection output, the master clock MCK0 (MCK1) and the time-division multiplexed data DB0 _{0 to} DB0 ₁₅ (DB1 _{0 to} DB1 ₁₅ ) are directly output to the external SLC ₀ , SLC ₁ , ..., SLC ₇ , Clock FCK0 (FCK1), MFCK0 (MF
CK1) and SMFCK0 (SMFCK1) are output to the internal counter unit 33.

The counter unit 33 has an LCOM ID (for example, "0" to "15") assigned to itself.
Based on the clock FC at the timing shown in FIG.
K '(FCK0, FCK1), MFCK' (MFCK
0, MFCK1), SMFCK '(SMFCK0, SM
FCK1) is generated and subordinate SLC ₀ , SLC ₁ , ...
・ Supply to SLC ₇ and above FCK ′, MF
CO output terminal (carry output terminal) and CI input terminal (carry input terminal) that generate CK 'and SMFCK' respectively
And have a plurality of presettable synchronous up counters connected in cascade.

Each SLC _i (i = 0 to 7) responds to each timing of the clocks MCK, FCK ', MFCK' and SMFCK 'supplied from the LCOM _n (n = 0 to 15) in which the SLC _i itself is accommodated. By recognizing a predetermined counter provided inside, the super multi-frame number, the multi-frame number, the frame number, the time slot number, and the bit number in the time slot of the data transmitted on the data bus DB are recognized. Then, the data to be sent to the subscriber line connected to itself is fetched (extracted) from the data bus DB and sent to the subscriber line.

The operation mode selection control circuit 32 uses the SH
Selection control of the selector 31 is performed based on the signals ACT ₀ and ACT ₁ input from the C20-0 and SHC20-1, respectively. That is, when the signal ACT ₀ output from the SHC 20-0 is active (when the SHC 20-0 is the active system), the signal group input to the input terminal group I ₀ is output from the SHC 20-1. Signal ACT
_{When 1} is active (when the SHC 20-1 is the active system), the selector 31 is controlled so that the signal group input to the input terminal group I ₁ is selectively output.

[0016]

[Problems to be Solved by the Invention] By the way,
System in which SHC (Shelf Common) is duplicated
Data bus DB for switching the current SHC system
0₀~ DB0₁₅(DB1 ₀~ DB1₁₅) Data list above
Each clock MCK0 (MCK1), FCK0 (FCK
1), MFCK0 (MFCK1), SMFCK0 (SM
FCK1) disturbance and ESD (Electro Static Dischar
ge: Each of the above clocks MCK due to factors such as electrostatic discharge)
0 (MCK1), FCK0 (FCK1), MFCK0
Disturbance of (MFCK1) and SMFCK0 (SMFCK1)
Occurs, each LCOM_nGenerated at (n = 0 to 15)
FCK '(FCK0', F
CK1 '), MFCK' (MFCK0 ', MFCK
1 '), SMFCK' (SMFCK0 ', SMFCK
In some cases, 1 ') cannot be generated. Therefore, any
LCOM_n(N = 1 to 16) Subordinate SLC_i(I = 0 to
For 7), clock FCK, MFCK or SMF
CK may be missing once. In this case, I mentioned above
As described above, SMFCK is a clock pulse generated every 12 ms.
Therefore, for the worst 12ms, the above SLC_i(I = 0 to 7)
It may cause malfunctions and poses a major problem in terms of reliability.
It was the subject.

Here, another problem that has conventionally occurred with the switching timing of the system will be described with reference to FIG. The # 0 system master clock MCK0 and the # 1 system master clock MCK1 are SHC20-0,
Since it is independently generated by SHC20-1, for example,
There may be a phase difference between the master clocks MCK0 and MCK1 as shown in FIGS. In this state, # 0 system SHC 20-0 to # 1 system SH
When the system switching to C20-1 occurs at the timing shown by the broken line in FIG. 11, each LCOM _n (n = 0 to 1)
The hexadecimal counter in the counter section 33 in 5) is shown in FIG.
After counting up at the timing shown in (4), it will be counted up again at the timing immediately after the system switching.

[0018] That is, the master clock MCK supplied to each LCOM _{n (n} = 0~15) is as shown in FIG. (E), the LCOM _{n (n} = 0~15), the figure ( DATA on the new system (# 1 system) data buses DB1 ₀ , DB1 ₁ , ..., DB1 ₁₅ at the timing as shown in f).
n (nth data) is mistakenly received as DATA n + 1 (n + 1th data) (that is,
The content of the hexadecimal counter for counting bits, which is counted up in synchronization with the rising edge of the master clock MCK, is different from the actual data number). As a result, one of the counters for counting the bit number, time slot number, frame number, and multi-frame number provided in the counter unit 33 of LCOM _n (n = 0 to 15) (not shown) or In the worst case, a mismatch occurs between all counter values and the actual number of the data on the highway. In the worst case, this mismatch occurs because the falling pulses of the clocks SMFCK, MFCK, and FCK sent by the SHF occur simultaneously. Frame synchronization is performed and FC in each LCOM _n (n = 0 to 15)
The counters for generating K ', MFCK' and SMFCK 'will continue until the decode value of a predetermined LCOMID is loaded.

In order to shorten the period of mismatch between the counter value and the actual data number, the clock SM
The SHC 20- is configured so that the system switching is performed immediately before the falling pulses of FCK, MFCK, and FCK occur simultaneously (for example, before several clocks of the master clock MCK).
A method of performing timing control at 0 (20-1) can be considered.

However, conventionally, each LCOM _n (n = 0 to 0)
15) various timing clocks (SMFCK, MFC) to be supplied to the SLC _i (i = 0 to 7) under it.
K, FCK), SHC20-0,2
It was impossible for 0-1 to uniformly perform the above timing control on all LCOM _{0 to} LCOM ₁₅ .

That is, for example, SHC20-0 (20
-1) timing clock SMFCK generated from
Simultaneous generation of MFCK and FCK is based on the data bus DB0.
The data on ₀ (DB1 ₀ ) is MF0 / F0 / TS0 / B.
Since it is generated at the same time when it changes to 0 (see FIG. 7), the system switching timing to each LCOM _n (n = 0 to 15) is
The data on the data bus DB0 _n (DB1 _n ) is MF5 /
If it is F15 / TS31 / B6-7,
SHC0 / MF0 / F0 / B0 from SHC switched to the active system 1-2 clocks after the master clock MCK
The falling pulses of the clocks SMFCK, MFCK, and FCK indicating the beginning of each LCOM _n (0 to
Each LCOM _n (n = 0 to 15) in order to be input as a load signal of the above-mentioned decoded value to the counter unit 33 in 15).
It is possible to minimize the discrepancy between the counter value generated from each counter for counting the bit number, the time slot number, the frame number, and the multi-frame number in the counter section 33 of FIG. However, from each LCOM _n (n = 0 to 15) to each DOM _n (n =
SMF supplied to subordinate SLC _i (0 to 7)
Clock SMFCK for 0 / MF0 / F0 / B0 synchronization
The sync falling pulse of / MFCK / FCK is generated by sequentially shifting by 4 time slots in the order of LCOM ID (= n) assigned to each LCOM _n (n = 0 to 15), as shown in FIG. Therefore, for example, the data on the data bus DB of LOM ₀ is MF5 / F15 / T31 /
When the system is switched during B6 to ₇ , SLC _i (i = 0 to 7) under the control of LCOM 7 has 28 time slots more than SLC _i (i = 0 to 7) under the control of LCOM _0. With the delay, the simultaneous falling pulses of the clocks SMFCK, MFCK and FCK are supplied. Therefore, LC
SLC _0, SLC ₁ under OM _7, ··· SLC ₇ is,
During the 28 time slots (a period of about 125 μs), the counter value does not match the actual data number. Similarly, SLC _i under LCOM _j (j = 1 to 7)
(I = 0 to 7) is for 4 × j time slots,
The counter value does not match the actual data number.

As described above, in the conventional system, the SL under the control of any LCOM _n (n = 0 to 15) is accompanied by the switching of the system.
In C (SLC _{0 to} SLC ₇ ), it is inevitable that synchronization with the data on the highway is not correctly established and erroneous reception occurs. However, the erroneous reception of data due to the switching of the system in this way is a fatal defect for data transmission that requires high reliability.

According to the present invention, even if the system is switched, the slave device (eg, the SLC) is the main device (eg, the SH device).
C) The data addressed to itself can be correctly received from the data of the time-division-multiplexed multiple channels transmitted in C) with high reliability, and even if a clock disturbance occurs, each slave device can extract the data. Sync signal for
The purpose is to reduce the probability of occurrence of a situation in which the clocks FCK, MFCK, SMFCK) are missing.

[0024]

1 and 2 are explanatory views of the principle of the present invention. The present invention relates to dual main units 1-1 and 1-2 and highways 2-1 to 2-N or 2-1 'to 2-N' from the main units 1-1 and 1-2.
A plurality of shared devices 3 which receive time-division-multiplexed data of a plurality of channels via the same and also input various synchronization signals for extracting the data of each channel from the data.
1 to 3-N and each shared device 3-1 to 3-N,
From each of the shared devices 3-1 to 3-N, the main devices 1-1 and 1-
2 is the highway 2-1 to 2-N, 2-1 'to 2-
A system having a plurality of slave devices 4-1 to 4-M for receiving time-division-multiplexed data of a plurality of channels transmitted via N'and extracting data addressed to itself from the received data. It is premised on the inter-device synchronization establishment method for exchanging data between the master devices 1-1 and 1-2 and the slave devices 4-1 to 4-M in FIG.

Then, each slave device 4-i (i = 1 to 1)
M) is transmitted from the shared device 3-j (j = 1 to N) in which the self is accommodated by the various synchronization signals (timing clocks) transmitted from the main devices 1-1 and 1-2. Generates a synchronization signal (timing clock) for extracting the data addressed to itself from the time-division-multiplexed data of multiple channels, and receives the data addressed to itself while synchronizing with the synchronization signal. Is characterized by.

The main devices 1-1 and 1-2 are highways 2-1.
.. 2-N or 2-1 'to 2-N', the time-division-multiplexed data of a plurality of channels is, for example, digitally encoded voice at least for each channel as described in claim 2. The data is data including one time slot, and the data received by each slave device 4-1 to 4-M is the data to be transmitted to the lines 5-1 to 5-M connected to itself.

The lines 5-1 to 5-M connected to the slaves 4-1 to 4-M are subscriber lines, for example. Further, the time-division-multiplexed data is, for example, in a super multi-frame unit made up of J consecutive multi-frames made up of I consecutive frames consisting of M channel time slots as described in claim 4. The data is serially transmitted. In this case, the main devices 1-1 and 1-2 have the master clock for 1-bit synchronization of the time slot, the frame clock for frame synchronization, and the multi-frame synchronization multi-frame. A frame clock and a super multi-frame clock for super multi-frame synchronization are used as the various synchronization signals via the shared devices 3-1 to 3-N.
Slave devices 4-1 to subordinates of each shared device 3-k (k = 1 to N)
4-M.

[0028]

According to the present invention, each slave device 4-1 to 4-M is
From the various synchronization signals generated by the main device 1-1 or 1-2, among the data of the time-division-multiplexed channels transmitted from the shared devices 3-1 to 3-N in which the self device is accommodated A synchronization signal for extracting data addressed to itself is generated, and the data addressed to itself is received while synchronizing with the synchronization signal.

In this way, each slave device 4-1 to 4-M
Various synchronization signals generated by the main device 1-1 or 1-2 are directly captured, and from the various synchronization signals thus captured, the main device 1-1 or 1-2 outputs the time-division-multiplexed multiple channels. Since the synchronization signal for extracting the data addressed to itself is generated from the data, even if the above-mentioned various synchronization signals are disturbed, the synchronization signal is lost due to the influence of the disturbance 4-i (i = 1 to 1). The number of M) can be reduced as compared with the conventional case. Further, the main device 1-1 or 1-2 performs system switching at an optimum timing, so that various synchronization signals are lost due to system switching that has conventionally occurred, or synchronization deviation with data on the highway. It is possible to prevent erroneous reception of data due to.

[0030]

Embodiments of the present invention will be described below with reference to the drawings. The overall configuration is similar to that shown in FIG.

In this embodiment, each LCOM _n (n =
0 ~ 15) and each LCOM _n and its subordinate SL
The connection configuration of C ₀ , SLC ₁ , ..., SLC ₇ is as shown in FIG.

As shown in the figure, the LCOM _{n of} this embodiment is
(N = 0 to 15) is an operation mode control circuit (ACT Cont) having the same function as the selector (SEL) 131 and the conventional operation mode control circuit (ACT) 32 shown in FIG.
rol) 132.

The selector 131 is the operation mode control circuit 1
According to the selection signal S added from 32, the SLC under its own control
₀ , SLC ₁ , ... SLC ₇ compared to conventional LCOM
Similarly to the selector 31 of _n (n = 0 to 15), the master clock MCK0 (MCK1) and each data bus DB0
_The time-division multiplexed data for 8 lines (8 channels) (# 0CCT to # 7CCT) is supplied from _n (DB1 _n ), and the mask clock MCK0 (SHC20-1) is also supplied. The MCK1), the frame clock FCK0 (FCK1), the multi-frame clock MFCK0 (MFCK1), and the super multi-frame clock SMFCK0 (SMFCK1) are directly supplied to the subordinate SLC ₀ , SLC ₁ , ..., SLC ₇ .

Then, SLC _i (i = 0) shown in FIG.
4 to 7) show the structure of the main part of the present invention according to the present invention. As shown in the figure, SLC _i (i = 0 to 7) includes a bit counter (Bit Counter) 142 which is an octal counter and a time slot counter (TS Counter) 14 which is a 32-ary counter.
Frame counter, which is a hexadecimal counter
er) 146 and a multi-frame counter (Multi-Frame Counter) 148 which is a hexadecimal counter.

In the bit counter 142, "1" (H level) is always inputted to the carry input terminal CI, and L
Master clock MCK (MCK0 or MCK1) supplied from SHC20-0 (SHC20-1) input to the clock terminal CK via COM _n (n = 0 to 15)
It is an octal counter that counts bit numbers from "0" to "7" in synchronization with. Then, it is reset to “0” in synchronization with the falling edge of the frame synchronization clock FCK sent from the SHC 20-0 (SHC 20-1) input to the load terminal L. The carry output terminal C0 is connected to the carry input terminal CI of the time slot counter 144.

The time slot counter 144 receives an SHC20-0 (SHC20) via LCOM _n every time a carry is carried from the bit counter 142.
-1) is a 32-bit counter that counts the time slot numbers from "0" to "31" in synchronization with the rising edge of the master clock MCK supplied from SHC20-0 like the bit counter 142. (SHC20
In synchronization with the falling edge of the frame clock FCK supplied from -1) to the load terminal L, a predetermined value is loaded from the correction circuit 149 described later. The carry output terminal C0 is connected to the carry input terminal CI of the frame counter 146.

The frame counter 146 supplies the master clock supplied from the SHC 20-0 (20-1) via LCOM _n each time a carry is carried from the time slot counter 144 to the carry input terminal CI. "0" to "1" in synchronization with the falling edge of MCK
5 "is a hexadecimal counter and counts the frame number up. Then, via the LCOM _n SHF20-0 (S
A predetermined value is loaded from the correction circuit 149 in synchronization with the falling edge of the multi-frame synchronization clock MFCK supplied from the HF 20-1) to the load terminal L.
The carry output terminal C0 is connected to the carry input terminal CI of the multi-frame counter 148.

The multi-frame counter 148 outputs SH via LCOM _n each time a carry is input from the frame counter 146 to the carry input terminal CI.
"0" -in synchronization with the rising edge of the master clock MCK supplied from C20-0 (SHC20-1)
It is a hexadecimal counter that counts frame numbers up to "5". Then, SHF20-0 via LCOM _n
A predetermined value is loaded from the correction circuit 149 in synchronization with the falling edge of the super multi-frame clock SMFCK supplied from (SHF20-1).
In addition, the carry output from the carry output terminal C0 is a super multi-frame clock SM.
It becomes FCK.

The correction circuit 149 has the SLC _i to which it belongs.
The SLC number assigned to (i = 0 to 7) is (0 to
127) Decode and SHC20 via LCOM _n
From −0 (SHC20-1) to the frame clock FCK,
When the multi-frame clock MFCK or the super multi-frame clock SMFCK is added, the time slot number, the frame number, and the multi-frame number to be loaded into the time slot counter 144, the frame counter 146, and the multi frame counter 148 are generated and output, respectively. It is a circuit to do. That is, for example, SHC20-0 (SHC20-1) is the LCO
Timing clock SMF in synchronization with the reception timing of the data of MF0 / F0 / TS0 / BD of SLC ₀ of M ₀
When controlling so that the falling edges of CK, MFCK, and FCK are generated, the correction circuit 149 of the SLC ₀ of LCOM _{0 has} the SLC assigned to that SLC _0.
The number (for example, "0") is decoded, and the decoded value "0" is output to all the data input terminals of the time slot counter 144, the frame number 146, and the multi-frame number 148. As a result, SL of LCOM ₀
To C _0, the timing clock SMFCK ₀ (SMFCK1) from SHC20-0 (SHC20-1), MFCK
Each time the falling edges of 0 (MFCK1) and FCK0 (FCK1) are simultaneously supplied, the SLC of LCOM _0
0 of time slot counter 144, the frame counter 146 and the multi-frame counter 148, are both "0" is loaded, LCOM SLC _{0 0} subsequent SHC20-0 (SHC20-1) data bus DB0
_Since the multi-frame number, the frame number, and the time slot number of the data output above ₀ can be correctly recognized by the count values of the multi-frame counter 148, the frame counter 146, and the time slot counter 144, respectively. You can correctly receive the data addressed to you. By the way, SHC20
-0 (SHC20-1) is, LCOM ₀ SLC under ₀
Timing clock SM at the above timing with reference to
FCK, MFCK, when at the same time to generate a falling edge of the FCK, the correction circuit 149 of SLC ₀ of LCOM ₁ decodes the SLC number assigned to the SLC ₀ (for example, "8"), LCOM ₁ SLC
“5” is output to the multi-frame counter 148 within ₀ , “15” is output to the frame counter 146, and “28” is output to the time slot counter 144. As a result, SHC2
0-0 (SHC20-1) is the timing clock SM
When the falling edges of FCK, MFCK, and FCK are generated at the same time, the multi-frame counter 148 and the frame counter 14 of SLC ₀ of LCOM ₁ are generated at that timing.
6. The time slot counter 144 is loaded with "5", "15" and "28", respectively. Similarly,
The correction circuit 149 for the SLC ₀ of LCOM ₇ is
_The SLC number (for example, "120") assigned to ₀ is decoded, and "5" is input to each data input terminal D of the multi-frame counter 148, frame counter 146, and time slot counter 144 in SLC _{0 of} LCOM _7. , “15”, “5” are output (above, refer to FIG. 7).

Next, the operation of the embodiment having the above configuration will be described. As described above, in this embodiment, each LCOM
Each SLC _i (i = 0 to 7) under the control of _n (n = 0 to 15) is different from the conventional SHC20-0 (SHC20-
1) Timing clocks SMFCK, M generated from
The FCK and FCK are directly input via LCOM _n (n = 0 to 15).

Therefore, system switching (from # 0 system to #
1 system or # 1 system to # 0 system), each LCO
Bit counter 142 and time slot counter 144 in SLC _i (i = 0 to 7) under M _n (n = 0 to 15)
Is the frame clock FC from the switched SHC.
As soon as K is generated, it is set to the correct value. That is, even if a mismatch between the counter value of the bit counter 142 or the counter value of the time slot counter 144 and the actual data number (bit number or frame number) on the data bus DB occurs due to system switching, all LCOM SLC under _n (n = 0 to 15)
_i (i = 0 to 7) is the first frame clock FCK generated from the SHC of the switched system, and the value of the bit counter 142 or the time slot counter 144 at the same time as the actual data on the data bus DB. Can be matched. Conventionally, each LCOM _n (n = 0 to 1
5) generated and output the frame clock FLK to be supplied to all SLC _i (i = 0 to 15) under its control from the frame clock FCK (FCK0 or FCK1) generated from the switched SHC of the system. So SHC
Timing clocks SMFCK, MFCK,
Data bus DB (DB0 _n or DB in synchronization with FCK
1 _n ) on which LCOM (eg LC
SLC _i (i = 0 to ₀ ) under the LCOM other than OM ₀ ).
In 7), the frame clock FCK was supplied with a delay of a minimum of 4 time slots and a maximum of 28 time slots.

The multi-frame clock MFCK,
Similarly, regarding the super multi-frame clock SMFCK, the multi-frame clock MFCK and the super multi-frame clock SMFCK generated by the SHC of the switched system are SLs under each LCOM _n (n = 0 to 15).
It is simultaneously supplied to C _i (i = 0 to 7). Therefore, the SLC _i (i = 0 to 7) under each LCOM _n (n = 0 to 15) are all correct at the same time by the first multi-frame clock MFCK and super-multi-frame clock SMFCK that generate SHC after system switching. Multi-frame synchronization and super multi-frame synchronization can be achieved.

Therefore, if the system switching is made to occur when the data on the data bus is MF5 / F15 / TS31 / B6-7, at most 1-
Although data may be erroneously received for 2 bits, the timing clock SMFCK / MFCK / FCK generated from the SHC of the system that has been immediately switched causes the SLC _i (i = _i ) under each LOM _n (n = 0 to 15). = 0
15-15), the bit counter 142, the time slot counter 144, the frame counter 146, and the multi-frame counter 148 are set to the correct values, so that all SLCs are correct bit sync, frame sync, multi-frame sync, and Super multiframe synchronization can be achieved and correct data reception (data extraction) can be performed. In addition, MF5 / F15 / TS in advance
By preventing meaningful data from being carried on 31 / B6 and B7, it becomes possible to prevent erroneous reception of data for all SLCs. Further, the system switching is performed from SHC such that falling edges of FCK, MFCK, and SMFCK are simultaneously generated MF0 / F0 / TS0 / B0.
By performing at a timing other than, it is possible to completely avoid at least the falling edges of FCK, MFCK, and SMFCK due to system switching for all SLCs.

Further, conventionally, each LOM is₀~ LCOM
₁₅But SLC under his control₀~ SLC₇On the other hand, Taimi
Ing clocks FCK, MFCK, SMFCK at once
Since it was being supplied, an arbitrary L was generated due to the occurrence of clock disturbance.
Timing clock FCK, MFCK or S by COM
If MFCK is missing, all SLs under the LCOM
C ₀~ SLC₇, The timing clock FCK,
Because MFCK or SMFCK is missing,
The probability of occurrence of SLC in which these clocks are missing was high.
However, in the present embodiment, each SLC has SHC (SH
Thailand supplied from C20-0 or SHC20-1)
Mining clock MCK, FCK, MFCK, SMFCK
The time slot number, frame number, and
Since the frame number is counted independently, the clock
The timing clock MCK, FCK,
Number of SLCs missing MFCK and SMFCK (SLC
Occurrence probability) is less than in the past. Also, in each SLC
Each timer counter (master clock counter, frame
Counter, multi-frame counter) count value is positive
It takes less time than before to restore the normal value.

The above embodiment is an example in which the present invention is applied to one device (one shelf) in a digital exchange.
The present invention is not limited to this, and can be applied to all systems in which a duplexed master device and a plurality of slave devices transmit and receive data by time-division multiplexed serial data of a plurality of channels.

[0046]

As described above, according to the present invention,
Each slave device generates various synchronization signals for extracting data addressed to itself (own channel) from time-division-multiplexed serial data of multiple channels by various synchronization signals generated by the master device, so system switching By performing the operation at appropriate timing, it is possible to prevent a situation in which various synchronization signals are lost in each slave device, and thus it is possible to prevent each slave device from receiving erroneous data.

Further, even if a disturbance of the synchronizing signal (clock) occurs due to system switching or ESD (electrostatic discharge), it becomes possible to reduce the probability of occurrence of slave devices in which various synchronizing signals are lost, and It is possible to shorten the time (recovery time) until the slave device can correctly synchronize with the data sent from the master device.

[Brief description of drawings]

FIG. 1 is a diagram for explaining the principle of the present invention (No. 1).

FIG. 2 is a diagram for explaining the principle of the present invention (No. 2).

FIG. 3 is a diagram showing a connection configuration of each LCOM and an SLC under the LCOM in one embodiment of the present invention.

FIG. 4 is a configuration diagram of a counter group provided inside each SLC.

FIG. 5 is a diagram showing a connection configuration of a duplexed SHC and each LCOM.

FIG. 6 is a diagram showing a connection configuration of each conventional LCOM and its subordinate SLC.

FIG. 7 is a diagram showing a data highway structure from SHC to each LOM.

FIG. 8 is a diagram showing a structure of time division multiplexed data transmitted by SHC.

FIG. 9: Timing clock SMFC generated by SHC
It is a figure explaining the pulse width of K, MFCK, and FCK.

FIG. 10 is an internal configuration diagram of a conventional LCOM.

FIG. 11 is a diagram illustrating erroneous reception of data that occurs due to system switching.

[Explanation of symbols]

 1-1, 1-2, 1-1 ', 1-2' Main device 2-1 to 2-N, 2-1 'to 2-N' Highway 3-1 to 3-N Shared device 4-1 to 4-M Slave device 5-1 to 5-M line

Claims (4)

[Claims] 1. A dual main unit (1-1, 1-2).
And the data of the multiple channels time-division multiplexed from the main devices (1-1, 1-2) through the highways (2-1 to 2-N or 2-1 'to 2-N'). In addition, a plurality of shared devices (3-1 to 3-3) that also input various synchronization signals for extracting data of each channel from the above data
-N) and each shared device (3-1, 3-N),
From each shared device (3-1 to 3-N), the main device (1-
1, 1-2) are the highways (2-1 to 2-N, 2-)
A plurality of slave devices (4-1) that receive time-division-multiplexed data of a plurality of channels transmitted via 1'-2-N ') and extract the data addressed to itself from the received data.
~ 4-M) in the system having the main device (1-
1, 1-2) and the slaves (4-1 to 4-M) for transmitting / receiving data between the slaves (4-i; i = 1 to M), , From the various synchronization signals transmitted by the main device (1-1, 1-2),
Shared device in which it is housed (3-j; j = 1 to N)
Generates a synchronization signal for extracting data addressed to itself from the time-division-multiplexed serial data of a plurality of channels, and receives the data addressed to itself while synchronizing with the synchronization signal. A method for establishing synchronization between devices, which is characterized in that 2. A time-division-multiplexed plurality which the main device (1-1, 1-2) sends out via a highway (2-1 to 2-N or 2-1 'to 2-N'). The channel serial data is data including at least one time slot of audio data digitally encoded for each channel, and the data received by each slave device (4-1 to 4-M) is connected to itself. 2. The inter-device synchronization establishment method according to claim 1, wherein the data is data to be sent to the connected lines (5-1 to 5-M). 3. The line (5-1 to 5-M) connected to the slave device (4-1 to 4-M) is a subscriber line. A method of establishing synchronization between devices. 4. The time-division-multiplexed data is data that is serially transmitted in units of super-multiframes in which J multiframes each including I consecutive frames each including a time slot for M channels are consecutively connected. The main device (1-1, 1-2) is configured such that the master clock for 1-bit synchronization of the time slot, the frame clock for the frame synchronization, the multi-frame clock for the multi-frame synchronization, and the super-multi. Using the super multi-frame clock for frame synchronization as the various synchronization signals, the sharing device (3-1 to 3-N)
4. The inter-device synchronization according to claim 1, 2 or 3, characterized in that the data is transmitted to the slave devices (4-1 to 4-M) under the control of each shared device (3-k; k = 1 to N) via the network. Establishment method.