JP2001265716A - Device and method for transmitting information - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information transmitter, with which the delay time of data to the synchronizing clock of a receiver is minimized, the number of slave devices to be connected with a little drive ability is not limited even when plural slave devices are connected to one master device, and the frequency of a communication clock or line length of a transmission line is not limited by the number of slave devices to be connected. SOLUTION: The slave device generates its own communication clock from a communication clock inputted from the outside and when connecting one master device and plural slave devices, the method of connecting the communication clock and data of the master device to the first slave device and connecting the communication clock and data of the first slave device to the next slave device is successively repeated. Then, the communication clock and data of the final slave device are connected to the master device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information transmitting apparatus for performing communication between a plurality of devices, and for example, for communication between a control board and a driver board in controlling a drive system of a laser printer or a copying machine. The present invention relates to an information transmission device and an information transmission method that can be applied.

[0002]

2. Description of the Related Art FIG. 4 shows an example of a conventional information transmission apparatus for performing serial communication between a pair of a master device and a slave device by transmitting data in synchronization with a unique communication clock. FIG. Referring to FIG. 4, the master device 1 includes an M reference clock generating unit 5 that generates an M reference clock that is a reference for a communication operation, an M communication clock generating unit 4 that generates an M communication clock from the M reference clock, and an M communication An M transmitter 3 that serially transfers M transmission data 2 as M data in synchronization with a clock, receives serial data transmitted by the slave device 8 in synchronization with a communication clock received from the slave device 8, and receives M reception data 6 , And an M receiver 7 for converting the In addition, slave
The device 8 includes an S reference clock generation unit 14 that generates an S reference clock serving as a reference for communication operation, an S communication clock generation unit 11 that generates an S communication clock from the S reference clock, and S transmission data in synchronization with the S communication clock. An S transmitter 10 serially transfers data 9 as S data.
An S receiver 13 receives the data in synchronization with the communication clock received from the device 1 and converts the received data into S received data 12. In this configuration, the master device 1 and the slave device 8 are usually of the same type.

[0003] First, a slave device
When transmitting data to the device 8, the M transmitter 3 adds, for example, a start bit before the M transmission data 2 and a parity bit and a stop bit after the M transmission data 2 according to a prescribed protocol. Data is transmitted to the slave device 8 as M data in order from the lower bit in synchronization with the falling edge of the generated M communication clock. The S receiver 13 of the slave device 8 sequentially receives the M data in synchronization with the rising edge of the M communication clock, and converts the data into the S received data 12.

[0004] Next, from the slave device 8 to the master device
Similarly, when transmitting data to the device 1, the S transmitter 10 adds, for example, a start bit before the S transmission data 9, a parity bit and a stop bit after the S transmission data 9 according to a prescribed protocol, and generates an S communication clock. Data is transmitted to the master device 1 as S data in order from the lower bit in synchronization with the falling edge of the S communication clock generated by the means 11. Master device 1
The M receiver 7 sequentially receives the S data in synchronization with the rising edge of the S communication clock and converts it into the M received data 6.

FIG. 5 is a block diagram showing an example of a conventional information transmitting apparatus for performing serial communication by exchanging data between a pair of master device and slave device in synchronization with a communication clock transmitted by the master device. FIG. Referring to FIG. 5, the master device 1
M reference clock generating means 5 for generating an M reference clock as a reference for communication operation, M communication clock generating means 4 for generating an M communication clock from the M reference clock, and transmitting M transmission data 2 in synchronization with the M communication clock An M transmitter 3 that serially transfers data, and an M receiver 7 that receives serial data transmitted by the slave device 8 in synchronization with an M communication clock and converts it into M received data 6. The slave device 8 is an S transmitter 10 that serially transfers the S transmission data 9 as S data in synchronization with a communication clock received from the master device 1, and transmits the serial data transmitted by the master device 1 to the master device 1. And an S receiver 13 which receives the data in synchronization with the communication clock received from the receiver and converts the received data into S received data 12. In this configuration, the slave device 8 has a simpler structure than the master device 1.

First, the master device 1 sends the slave
When transmitting data to the device 8, the M transmitter 3 adds, for example, a start bit before the M transmission data 2 and a parity bit and a stop bit after the M transmission data 2 according to a prescribed protocol. Data is transmitted to the slave device 8 as M data in order from the lower bit in synchronization with the falling edge of the generated M communication clock. The S receiver 13 of the slave device 8 sequentially receives the M data in synchronization with the rising edge of the M communication clock, and converts the data into the S received data 12.

Next, from the slave device 8 to the master device
When transmitting data to the device 1, the S transmitter 10 adds, for example, a start bit before the S transmission data 9, a parity bit and a stop bit after the S transmission data 9 according to a prescribed protocol, and sets the falling edge of the M communication clock. , And transmits the data to the master device 1 as S data in order from the lower bit in synchronization with. The M receiver 7 of the master device 1 sequentially receives the S data in synchronization with the rising edge of the M communication clock generated inside the master device 1 and converts the S data into the M received data 6.

FIG. 6 shows a conventional system in which one master device and a plurality of slave devices are connected in parallel, and each device performs serial communication by transmitting data in synchronization with a unique communication clock. It is a block diagram showing an example of an information transmission device. Referring to FIG. 6, one master device 15 has a slave device a16 having ID = 1, a slave device b17 having ID = 2, I
A slave device c18 having D = 3 is connected in parallel, and the M communication clock and M data transmitted by the master device 15 are transmitted to the slave device a16 and the slave device c16.
The receivers of the device b17 and the slave device c18 receive the S communication clock and the S data transmitted by the slave device a16, the slave device b17, and the slave device c18, respectively, to the common device connected to the receiver of the master device 15. The communication line is connected by means such as a wired OR using an open collector or an open drain or a tri-state buffer.

First, when data is transmitted from the master device 15 to, for example, the slave device a16, the master device 15 sends an ID indicating that the transmission destination is the slave device a16 according to a prescribed protocol.
= 1 is transmitted in synchronization with the M communication clock output from the master device 15 itself. The slave device a16, the slave device b17, and the slave device c18 compare the ID data included in the M data received from the master device 15 with the ID of each slave device itself, and validate the received data only when they match. Is processed as important data.

Next, for example, when transmitting data from the slave device a16 to the master device 15, the slave device a16 transmits S data in synchronization with the S communication clock output from the slave device a16 itself. The slave device b17 and the slave device c18 receive a command received from the master device 15 or a selection signal (not shown) independent of the communication line.
The S communication clock and S data output are open or high impedance, and are in a state where they do not compete with the communication of the slave device a16.

FIG. 7 shows a conventional serial communication in which one master device and a plurality of slave devices are connected in parallel and data is exchanged in synchronization with a communication clock generated by the master device. It is a block diagram showing an example of an information transmission device. Referring to FIG.
Slave device having ID = 1 to two master devices 15
Device a16, slave device b with ID = 2
17, the slave device c18 having ID = 3 is connected in parallel, and the M communication clock and M data transmitted by the master device 15 are transmitted by the slave device a16, the slave device b17, and the slave device c18. The S data transmitted and received by the slave device a16, the slave device b17, and the slave device c18 are respectively transmitted to the common communication line connected to the receiver of the master device 15 by a wired OR using an open collector or an open drain. The connection is made using a means such as a tri-state buffer.

First, when data is transmitted from the master device 15 to, for example, the slave device a16, the master device 15 sends an ID indicating that the transmission destination is the slave device a16 according to a prescribed protocol.
= 1 is transmitted in synchronization with the M communication clock output from the master device 15 itself. The slave device a16, the slave device b17, and the slave device c18 compare the ID data included in the M data received from the master device 15 with the ID of each slave device itself, and validate the received data only when they match. Is processed as important data.

Next, for example, when data is transmitted from the slave device a16 to the master device 15, the slave device a16 outputs M
Although the S data is transmitted in synchronization with the communication clock, the slave data is transmitted in advance by a command received from the master device 15 or a selection signal (not shown) independent of the communication line.
The output of the S communication clock and the S data of the device b17 and the slave device c18 are open or high impedance, and do not compete with the communication of the slave device a16.

[0014]

In a conventional information transmission apparatus in which a pair of master device and slave device perform communication by transmitting data in synchronization with a unique communication clock, each device communicates with a master device and a slave device. Since the receiver of the device on the side synchronizes with the communication clock of the device on the transmission side, the possibility of occurrence of synchronization deviation between the synchronization clock of the receiver and the received data is extremely low, and high-speed communication with a communication clock of high frequency is possible However, since the master device and the slave device must each have a reference clock generation means, that is, an oscillator and a transmission circuit, the circuit configuration of the slave device becomes as complicated as the master device. , Which contributed to the cost increase.

Further, in a conventional information transmission apparatus which performs communication between a pair of master device and slave device by exchanging data in synchronization with a communication clock transmitted by the master device, the slave device side is used as a reference. Since there is no need to have a clock generation means, that is, an oscillator or an oscillation circuit, there is an advantage that the circuit configuration of the slave device can be simplified. However, since the communication clock transmitted by the master device becomes the synchronization clock of the receiver inside the master device and the synchronization clock of the transmitter of the slave device, the delay of the communication clock inside the master device is negligibly small. On the other hand, the communication clock received by the slave device is delayed by the bus driver and receiver included in the transmission path from the master device via the transmission line to the slave device, and by the transmission line itself. Uses a communication clock having a delay with respect to the synchronization clock of the receiver of the master device as the synchronization clock of the transmitter. Also, data transmitted by the slave device in synchronization with the communication clock received from the master device is transmitted from the slave device to the master device via the transmission line in the same manner as the communication clock received from the master device. Buses included in the transmission path to
A delay due to the driver and the receiver and a delay due to the transmission line itself occur. Therefore, the data received by the master device from the slave device has a delay corresponding to the round trip of the transmission path with respect to the synchronization clock of the receiver of the master device. Therefore, a synchronization error occurs between the synchronization clock when the receiver of the master device receives data and the data received from the slave device, so that a timing that satisfies the data setting time and data holding time of the receiver is set. It is necessary to determine the frequency of the communication clock in consideration of this, and there has been a problem that the increase in communication speed is limited.

Conventional information for performing serial communication by connecting one master device and a plurality of slave devices in parallel and transmitting data in synchronization with a unique communication clock. In the transmitting device, the receiver of the receiving device synchronizes with the communication clock of the transmitting device in the same manner as in the case of a one-to-one information transmitting device of the master device and the slave device. The advantage of connecting multiple slave devices in parallel with the master device is that the master device must be connected to all slave devices. And the input capacity and transmission path capacity of all slave devices. The problem is that the number of slave devices that can be connected is limited by the input capacity of the slave device and the capacity of the transmission path because the total is the load capacity driven by the master device.The number of slave devices connected in parallel As the load increases, the rise and fall of the communication clock slows down, increasing the
The problem is that the number of devices must be limited or the frequency of the communication clock must be reduced to a level that does not affect signal dullness.Because there are branch points in the transmission line, signal reflection at the branch point The inconsistency in the arrival time of the reflected wave from the device causes a disturbance in the signal waveform, which hinders an increase in the communication speed and limits the length of the transmission line.

Conventional information for performing serial communication by connecting one master device and a plurality of slave devices in parallel and exchanging data in synchronization with a communication clock transmitted by the master device. In the transmission device, the master device and the slave device are one-to-one.
In addition to the problem that the data received by the master device from the slave device has a delay corresponding to the round trip of the transmission path with respect to the synchronization clock of the receiver of the master device, a plurality of slave devices・
There has been the aforementioned problem caused by connecting the device to the master device in parallel.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and has as its object to provide a low-cost, high-speed system that minimizes the delay time of data from a transmitting device with respect to a synchronization clock of a receiver of a receiving device. It is to provide a simple information transmission device. In addition, one master
Even when multiple slave devices are connected to a device, the number of slave devices that can be connected with a small drive capacity is not limited, and the frequency of the communication clock and the line length of the transmission line are limited by the number of slave devices connected. It is an object of the present invention to provide a low-cost, high-speed information transmission device that does not require any communication.

[0019]

SUMMARY OF THE INVENTION An object of the present invention is to provide a reference clock generating means for generating a reference clock, a communication clock generating means for generating a communication clock from the reference clock, and transmitting data to a slave device in synchronization with the communication clock. A master device having a transmitter for transmitting data transmitted by the slave device and a receiver for receiving data transmitted from the slave device in synchronization with a communication clock received from the slave device; and transmitting data transmitted by the master device or another slave device to the master device. A slave comprising: a receiver for receiving data in synchronization with a communication clock received from a device; a communication clock generator for generating a communication clock from a reference clock input from the outside; and a transmitter for transmitting data in synchronization with the communication clock. Information transmission device consisting of devices Oite is achieved by the slave device generates its own communication clock as a reference clock a communication clock received from the master device or other slave devices. Further, in an information transmission device including one master device and a plurality of slave devices, a first slave device receives a communication clock and data transmitted by the master device, and the first slave device Generates the communication clock of the first slave device itself using the communication clock received from the master device as the reference device as the reference clock, and transmits the communication clock and data transmitted by the first slave device to the next device. This is achieved by sequentially repeating the method of receiving by the slave device, and receiving the communication clock and data transmitted by the last slave device by the master device.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing one embodiment for realizing an information transmission device according to the present invention.

In FIG. 1, the present embodiment has a pair of masters.
This shows a case where each device performs serial communication by transmitting data in synchronization with a unique communication clock between the device and the slave device, and the master device 1 uses an M reference clock as a reference for communication operation. M reference clock generating means 5 for generating, M communication clock generating means 4 for generating M communication clock from M reference clock, M transmitter 3 for serially transferring M transmission data 2 as M data in synchronization with M communication clock, slave The serial data transmitted by the device 8 is transferred to the slave device 8
And an M receiver 7 that receives the data in synchronization with the communication clock received from the MPU and converts the received data into M received data 6. The slave device 8 generates an S communication clock from the communication clock received from the master device 1.
A communication clock generating means 11; an S transmitter 10 for serially transferring S transmission data 9 as S data in synchronization with the S communication clock; and a serial clock transmitted by the master device 1 in synchronization with a communication clock received from the master device 1. S to be received and converted to S reception data 12
The communication clock received from the master device 1 is connected to the S receiver 13 and the S communication clock generation means 11 inside the slave device 8.

Next, the operation of this embodiment will be described. First,
A case where data is transmitted from the master device 1 to the slave device 8 will be described. In the present embodiment, the M reference clock generating means 5 is a programmable frequency divider, which divides the frequency of a system clock (not shown) externally supplied to the master device 1 and generates a clock having a frequency according to the setting. Is generated and supplied to the M communication clock generating means 4 as the M reference clock. The M communication clock generating means 4 supplies the M reference clock to the M transmitter 3 as a synchronous clock without dividing the M reference clock, and outputs the M reference clock as the M communication clock without dividing the M reference clock via a built-in bus driver. Send to device 8. The M transmitter 3 adds, for example, a start bit before the M transmission data 2 and a parity bit and a stop bit after the M transmission data 2 according to a prescribed protocol, and outputs the falling edge of the M communication clock transmitted by the M communication clock generating means 4. The data is transmitted to the slave device 8 through the built-in bus driver as M data in order from the lower bit in synchronization with. The S receiver 13 of the slave device 8 has M
A communication clock is supplied as a synchronous clock, and M
The M data is sequentially received in synchronization with the rising edge of the communication clock, and is converted into S reception data 12.

Next, from the slave device 8 to the master device
A case where data is transmitted to the device 1 will be described. The S communication clock generating means 11 supplies the M communication clock received from the master device 1 to the S transmitter 10 without dividing the frequency as a synchronous clock, and does not divide the M communication clock via the built-in bus driver. To the master device 1 as an S communication clock. The S transmitter 10 adds, for example, a start bit before the S transmission data 9, a parity bit, and a stop bit after the S transmission data 9 in accordance with a prescribed protocol, and generates a falling edge of the S communication clock transmitted by the S communication clock generating means 11. The data is transmitted to the master device 1 through the built-in bus driver as S data in order from the lower bit in synchronization with the data. The S communication clock is supplied to the M receiver 7 of the master device 1 as a synchronization clock. The S data is sequentially received in synchronization with the rising edge of the S communication clock, and is converted into the M reception data 6. By repeating the above operation, the master device 1 and the slave device 8 communicate data with each other. Since the M communication clock transmitted by the master device 1 is the reference clock of the S communication clock generated by the slave device 8, the slave device 8 transmits the data in addition to the data transmitted by the master device 1. Is transmitted, the master device 1 needs to transmit the M communication clock.

In the present embodiment, the M reference clock generating means 5 is a programmable frequency divider, but may be a simple frequency divider, a transmitter or a transmitter circuit. Further, although the M communication clock generation means 4 is used without dividing the M reference clock, it may be divided and used. Although the S communication clock generating means 11 uses the M communication clock received from the master device 1 without dividing the frequency, the S communication clock generating means 11 may use the M communication clock after dividing the frequency. However, if the M communication clock is divided and used by the S communication clock generation means 11, the communication speed from the slave device 8 to the master device 1 is lower than the communication speed from the master device 1 to the slave device 8. Therefore, a better communication speed can be obtained by using the frequency division without dividing. Although the M transmitter 3 and the S transmitter 10 have built-in bus drivers, they may have external bus drivers. Further, in the present embodiment, an example of the communication protocol is shown, but the present invention does not specify the content of the communication protocol,
Any communication protocol may be used.

FIG. 2 is a block diagram showing another embodiment for realizing the information transmitting apparatus according to the present invention. In FIG. 2, the present embodiment relates to a case where one master device and a plurality of slave devices are connected, and each device performs serial communication by transmitting data in synchronization with a unique communication clock. The communication clock and data transmitted by the master device 15 are received by the slave device a16 having ID = 1, and the slave device a16
The communication clock and data transmitted by the slave device b17 having ID = 2 are received by the slave device b17.
The communication clock and data transmitted by 17 are received by the slave device c18 having ID = 3, and the communication clock and data transmitted by the slave device c18 are received by the master device 15.

Next, the operation of this embodiment will be described.
The master device 15 has an ID indicating an ID of a slave device to be communicated with according to a prescribed protocol.
Data including D data is transmitted in synchronization with a communication clock output from the master device 15 itself. The slave device a16 generates the communication clock of the slave device a16 itself from the communication clock received from the master device 15 and converts the received data as transmission data to the communication clock of the slave device a16 itself, as in the above-described embodiment. The data is sequentially transmitted to the slave device b17 in synchronization. Similarly, the slave device b17 generates its own communication clock from the communication clock received from the slave device a16, and uses the received data as transmission data as the slave device b1.
7 Slave device c in synchronization with its own communication clock
18 sequentially. Similarly, the slave device c18 generates a communication clock of the slave device c18 itself from the communication clock received from the slave device b17, and uses the received data as transmission data.
In synchronization with the communication clock of device c18 itself, the master
Send to device 15. Slave device a16,
Slave device b17, slave device c18
Compares the ID data included in the data received from the master device 15 or the preceding slave device with the ID of each slave device itself, and processes the data as valid data only when the IDs match, but transfers the data to the next stage. Is I
Regardless of whether D matches or not, the communication is circulated to the master device 15. In the present embodiment, I means an ID of a slave device designated as a communication target.
A series of data transmitted by the master device 15 using a communication protocol including D data and a command for designating data transmission from the master device to the slave device or data transmission from the slave device to the master device. When the master device 15 receives a series of data whose contents are added or changed by the slave device to be communicated with the data, the master device 15 completes a set of communication.

For example, if the master device 15 is a slave device,
When communicating with the device a16, the master device 15
Is a command for designating ID = 1 indicating ID = 1 for specifying the slave device a16 and data transmission from the master device 15 to the slave device a16 or data transmission from the slave device a16 to the master device 15. Is transmitted in synchronization with the fall of the communication clock transmitted by the master device 15. The slave device a16 sequentially receives the data transmitted by the master device 15 in synchronization with the rising edge of the communication clock received from the master device 15, and converts the data into received data. During this process, the slave device a16 checks the ID data defined by the communication protocol, for example, the second and third bits, and matches the ID = 1 of the slave device a16. The data currently received is valid data for the slave device a16, and executes processing according to the command. Also, the slave device a16 transmits the communication clock received from the master device 15 to the slave device b17 as the slave device a16's own communication clock, and every time 1-bit data is received from the master device 15, The data is transmitted to the slave device b17 in synchronization with the falling edge of the communication clock of the slave device a16. At this time, the data transmitted from the slave device a16 to the slave device b17 is data in which the slave device a16 to be communicated adds or changes the bits defined in the communication protocol in response to the command, and Are transmitted as it is from the master device 15. The slave device b17 sequentially receives the data transmitted by the slave device a16 in synchronization with the rising edge of the communication clock received from the slave device a16,
Convert to received data. During this process, the slave
The device b17 checks the ID data defined by the communication protocol, for example, the second and third bits, but does not match the ID = 2 of the slave device b17. Therefore, the currently received data is invalid data for the slave device b17, and the received data is ignored. However, the slave device b17 uses the communication clock received from the slave device a16 to communicate with the slave device b17 itself. The data is transmitted to the slave device c18 as a clock. Each time 1-bit data is received from the slave device a16, the data is transmitted to the slave device c18 in synchronization with the falling edge of the communication clock of the slave device b17. I do. At this time, the slave device b17 transmits the data received from the slave device a16 to the slave device c.
18 and transmitted as it is. The slave device c18 sequentially receives the data transmitted by the slave device b17 in synchronization with the rising edge of the communication clock received from the slave device b17, and converts it into received data. During this process, the slave device c18 checks the ID data specified by the communication protocol, for example, the second and third bits, but does not match the ID = 3 of the slave device c18. Therefore, since the currently received data is invalid data for the slave device c18, the received data is ignored.
The slave device c18 is the slave device b17
The communication clock received from the slave device c18
It transmits to the master device 15 as its own communication clock, and every time 1-bit data is received from the slave device b17, the master device 1 synchronizes with the falling edge of the communication clock of the slave device c18.
5 to send the data. At this time, the slave device c1
8 transmits the data received from the slave device b17 to the master device 15 as it is. The master device 15 sequentially receives the data transmitted by the slave device c18 in synchronization with the rising edge of the communication clock received from the slave device c18, and converts the data into received data.

In the present embodiment, the destination of each device is only one device, and the drive capability of each device only needs to be able to drive one load device. Since each slave device serves as a communication buffer, the The rising or falling of the signal does not slow down due to the increase in the number of connected devices. Further, since the communication line has a structure having no branch point, there is no need to consider the reflection at the branch point or the line length from the branch point to the load device. Further, in the present embodiment, the case where the number of slave devices is three has been described, but the number of slave devices may be any number. Further, in this embodiment, an example of the communication protocol has been described, but the present invention does not specify the content of the communication protocol, and any communication protocol may be used.

FIG. 3 is an explanatory diagram for explaining a delay caused by a communication path in the information transmitting apparatus according to the present invention.
FIG. 3A is a diagram modeling a transmission path between the master device and the slave device when each device communicates by transmitting data in synchronization with a unique communication clock. The transmission path of the M communication clock transmitted from the master device to the slave device in 3 (a) includes the MC bus driver 19, the MC transmission line 20, and the MC bus receiver 21, and transmits from the master device to the slave device. The transmission path of M data to be transmitted is the MD bus driver 22, the MD transmission line 23,
The transmission path of the S communication clock transmitted from the slave device to the master device includes the SC bus driver 27, the SC transmission line 26, and the SC bus.
The transmission path of S data transmitted from the slave device to the master device comprises a bus
It comprises a bus driver 30, an SD transmission line 29, and an SD bus receiver. Here, the MC bus driver 19
The delay time due to the MC transmission line 20 is tdmcl, the delay time due to the MC bus receiver 21 is tdmcbr, the delay time due to the MD bus driver 22 is tdmdbd, and the delay time due to the MD transmission line 23 is tdmd.
l, the delay time due to the MD bus receiver 24 is tdmdbr,
The delay time of the SC bus driver 27 is represented by tdscbd, S
The delay time of the C transmission line 26 is tdscl, the delay time of the SC bus receiver 25 is tdscbr, the delay time of the SD bus driver 30 is tdsdbd, and the SD transmission line 29 is
Is defined as tdsdl and the delay time due to the SD bus receiver 28 as tdsdbr, the delay time tdmc due to the transmission path of the M communication clock is tdmc = tdmcbd + tdmcl + tdmcbr The delay time tdmd due to the transmission path of the M data is tdmd = tdmdbd + tdmdl + tdmdbr S communication clock The delay time tdsc due to the transmission path is tdsc = tdscbd + tdscl + tdscbr The delay time tdsd due to the S data transmission path is tdsd = tdsdbd + tdsdl + tdsdbr. Next, the data delay time td with respect to the communication clock in the receiving device as shown in FIG.
think of. When transmitting data from the master device to the slave device, the delay time tdm of the M data with respect to the M communication clock in the slave device is the difference between the delay time tdmd due to the transmission path of the M communication clock and the delay time tdmd due to the transmission path of the M data. Where tdm = tdmd−tdmc, and the delay time tdmcl and M
Since the delay time tdmdl due to the D transmission line 23 can usually be considered to be almost equal, tdm = (tdmdbd-tdmcbd) + (tdmdbr-tdmcbr). Similarly, when transmitting from the slave device to the master device, the delay time tds of the S data with respect to the S communication clock in the master device is the delay time tdsc due to the transmission path of the S communication clock and the delay time tdsd due to the transmission path of the S data. However, since the delay time tdscl due to the SC transmission line 26 and the delay time tdsdl due to the SD transmission line 29 can be generally considered almost equal, tds = tdsd−tdsc = (tdsdbd−tdscbd) + ( tdsdbr-tdscbr). Here, tdmdbd-tdmcbd and tdmdbr-td
Since mcbr, tdsdbd-tdscbd, and tdsdbr-tdscbr are differences in delay time between bus drivers or bus receivers, they can be easily reduced to several nsec or less.

[0030]

According to the present invention, there is provided an information transmission apparatus for performing communication between a master device and a slave device by transmitting data in synchronization with a unique communication clock. Generates its own communication clock using the communication clock received from the master device or another slave device as the reference clock as the receiver's synchronization clock.
The slave device does not need the reference clock generation means, and the receiving device performs reception in synchronization with the communication clock generated by the transmitting device. It has become possible to configure a low-cost and high-speed information transmission device that minimizes the data delay time. Further, in an information transmission device including one master device and a plurality of slave devices, a first slave device receives a communication clock and data transmitted by the master device, and the first slave device Generates the communication clock of the first slave device itself using the communication clock received from the master device as the preceding device as a reference clock, and generates the first slave device's own communication clock.
A method in which the next slave device receives the communication clock and data transmitted by the device is sequentially repeated,
When the master device receives the communication clock and data transmitted by the last slave device, when a plurality of slave devices are connected to one master device, even if the drive capability of each device is reduced, There is no limit on the number of slave devices that can be connected, and it is possible to configure a low-cost, high-speed information transmission device where the frequency of the communication clock and the line length of the transmission line are not limited by the number of connected slave devices. It is.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing another embodiment of the present invention.

FIG. 3 is an explanatory diagram for explaining a delay due to a communication path according to the present invention.

FIG. 4 is a block diagram illustrating an example of a conventional information transmission device.

FIG. 5 is a block diagram illustrating an example of a conventional information transmission device.

FIG. 6 is a block diagram illustrating an example of a conventional information transmission device.

FIG. 7 is a block diagram illustrating an example of a conventional information transmission device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Master device, 2 ... M transmission data, 3 ... M transmitter, 4 ... M communication clock generation means, 5 ... M reference clock generation means, 6 ... M reception data, 7 ... M receiver, 8 ... M receiver, 9 ... S transmission data, 10 ... S transmitter, 11 ... S communication clock generation means, 12 ... S
Received data, 13 ... S receiver, 14 ... S reference clock generation means, 15 ... Master device, 16 ... Slave
Devices a, 17: slave device b, 18: slave device c, 19: MC bus driver, 20
... MC transmission line, 21 ... MC bus receiver, 22 ... M
D bus driver, 23 ... MD transmission line, 24 ... MD bus receiver, 25 ... SC bus receiver, 26 ... SC
Transmission line, 27: SC bus driver, 28: SD bus receiver, 29: SD transmission line, 30: SD bus
driver.

Claims (2)

[Claims] 1. A reference clock generating means for generating a reference clock, a communication clock generating means for generating a communication clock from the reference clock, a transmitter for transmitting data to the slave device in synchronization with the communication clock, and a slave device Device having a receiver for receiving data transmitted by the device in synchronization with a communication clock received from the slave device, and a communication clock for receiving data transmitted by the master device or another slave device from the device. Information transmission device having a slave device comprising: a receiver for receiving data in synchronization with a communication clock generator for generating a communication clock from a reference clock input from outside; and a transmitter for transmitting data in synchronization with the communication clock At the slave device But the information transmission device, characterized in that a generating means for generating its own communication clock communication clock received from the master device or other slave devices as a reference clock. 2. The information transmitting apparatus according to claim 1, comprising one master device and a plurality of slave devices, wherein the communication clock and data transmitted by the master device are received by the first slave device. The method in which the next slave device receives the communication clock and data transmitted by the first slave device sequentially, and the master device receives the communication clock and data transmitted by the last slave device. An information transmission method characterized by the following.