JPH0916517A - Bus interface - Google Patents

Abstract

PURPOSE: To freely increase/decrease the number of slave machines by connecting to a master machine via an RS232C interface. CONSTITUTION: The master machine 10 is connected to a first slave machine 11(1) via a cable 12. A branch circuit 13 is provided in the first slave machine 11(1), and the master machine is connected to the port P1 of the slave machine. Also, one port P3 out of two remaining ports is connected to the internal circuit of the first slave machine 11(1), and the remaining port P2 to the next slave machine 11(2). Data from the master machine 10 is transferred to the first slave machine 11(1) and the next slave machine 11(2) simultaneously. The data outputted from the first slave machine 11(1) and the one outputted from the next slave machine 11(2) are transmitted from the port P1 to the master machine 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus interface that expands and uses functions such as a serial bus interface of RS232C standard.

[0002]

2. Description of the Related Art An RS232C standard interface cable, which is often used as an interface of an information processing apparatus, comprises a cable having a predetermined connection and a pair of connectors provided at both ends thereof. However, there is also a system in which, for example, a plurality of slave units are connected to one master unit, and each slave unit transmits / receives data to / from the master unit. In such a system, the master unit and all the slave units are connected via a changeover switch at one end of the interface cable, and the connection destination is selected by the control of the switch. There is also a configuration in which a plurality of communication ports are provided in a master unit and each communication port is connected to a different slave unit through a different interface cable.

[0003]

The conventional serial bus interface as described above has the following problems to be solved. As described above, when the changeover switch is used to realize the 1-to-N communication, it is necessary to newly take measures against noise generated when the switch is changed over. Also, the number of ports that can be switched is limited by the configuration of the switch. On the other hand, in the method in which a plurality of communication ports are provided in advance on the master unit, the communication ports are wasted when the number of slave units connected to the master unit is small, and when there are many slave units, the master port is limited by the number of communication ports. There is a child device that cannot be directly connected to the device. Therefore, in any case, there is a problem that the expandability is poor.

[0004]

The present invention employs the following structure to solve the above problems. The bus interface of the present invention sequentially connects a master unit and a plurality of slave units in series via a branch circuit provided in each slave unit. In the branch circuit,
An input port that accepts data transmitted from the master unit to the slave unit, an output port that accepts data transmitted from the master unit to itself via this input port, and a master unit via the input port An output port that transfers the data transmitted from the other device to the succeeding device as it is,
An input port for inputting the data transmitted from itself to the master unit, an input port for receiving the data transmitted from other slave units to the master unit, and the slave unit from the slave unit via these input ports. And an output port for outputting data transmitted to the machine.

Further, another bus interface connects a master unit and a plurality of slave units in series in order via a branch circuit provided in each slave unit. The branch circuit has an input port that receives the control signal transmitted from the master unit to the slave unit, an output port that receives the control signal transmitted from the master unit to itself via this input port, and an input port. An output port that transfers the control signal transmitted from the master unit to another slave unit through the port to the succeeding slave unit as it is, and an input port that inputs the control signal transmitted from itself to the master unit. , An input port that accepts control signals transmitted from other slave units to the master unit, and an output port that outputs control signals transmitted from the slave units to the master unit via these input ports. When the control signals transmitted from multiple slave units to the master unit compete with each other, it is determined which control signal from the slave unit is input to the branch circuit first, and the control signal is generated in the branch circuit. The response signal comes first, the control signal Comprising a conflict adjustment circuit to return to the force the handset.

[0006]

Operation: The master unit is connected to the first slave unit via the interface cable. A branch circuit is provided in the first child device, and the parent device is connected to the port P1. One of the remaining two ports, P3, is connected to the internal circuit of the first slave unit, and the remaining port, P2, is connected to the next slave unit. The data from the master unit is transferred to the first slave unit and the next slave unit at the same time. The data output from the first slave unit and the data output from the second slave unit are respectively set to ports P2 and P2.
It is input from P3 and is transmitted to the master unit together through the port P1. In this way, a plurality of slave units are sequentially connected in series via the branch circuit, and each transmits / receives data to / from the master unit via the branch circuit. The branch circuit allows you to add or remove slave units freely. Moreover, the master unit may have only one communication port, and all the slave units may have two communication ports to the outside.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the embodiments shown in the drawings. FIG. 1 is a block diagram showing a bus interface embodiment of the present invention. In this figure, a master device 10 which is an RS232C standard utilizing device and a plurality of slave devices 11 (1) to 11 (n) which transmit and receive data to and from the master device 10 are shown. A branch circuit 13 having the same configuration is provided in each of the child devices 11 (1) to 11 (n). Each branch circuit 13 is provided with three ports P1, P2, P3. For example, the branch circuit 1 of the first child device 11 (1)
3, the port 1 is connected to the master device 10 via the cable 12. The cable 12 is an RS232C interface. The port 2 is connected to the next child device 11 (2) via the cable 12. Remaining port P3
Is connected to its own internal RS232C standard utilization circuit 14. The other slaves are connected in exactly the same manner, and in the remaining slaves 11 (2) to 11 (n-1), the port P1 is connected to the immediately preceding slave through the cable 12, P2 is connected to the succeeding child device via the cable 12. The last cordless handset 11 (N) is port P1
Is connected to the immediately preceding slave 11 (N-1) via the cable 12, and the port P2 is open.

FIG. 2 shows a schematic operation explanatory diagram of the bus interface of the present invention. (A) of the figure shows the bus interface of the present invention, and (b), (c), and (d) show three types of comparative examples. In the case of the present invention shown in (a), as described above, the main unit 10 and the slave unit 11 are
(1) to 11 (n) are connected in series by a cable 12 and a branch circuit 13, respectively. Then, each of the slaves 11 (1) to 11 (n) is configured to be capable of transmitting / receiving control signals and data to / from the master 10 via the cable 12 and the branch circuit 13.

Here, the comparative example 1 shown in FIG.
An information processing apparatus 15 having a communication port 16 is shown connected to the information processing apparatus 15 by a cable 17.
If the interface having such a configuration is applied to 1: N, the interfaces are as shown in FIGS. 2 (c) and 2 (d). That is, in the example of (c), one information processing device 15 and three information processing devices 15 are mutually connected via the switch 18. In this case, by switching the changeover switch 18, the information processing device 15 on the left side and one of the information processing devices 15 on the right side are connected.

The example shown in (d) is the information processing device 1 on the left side.
9 shows an example in which three communication ports 16 are provided, and each communication port and the information processing device 15 on the right side are connected by separate cables 17. In this example, the information processing device 19 on the left side requires communication ports corresponding to the number of information processing devices on the right side. If the examples shown in (c) and (d) are compared with the example shown in (a), the configuration of the device of the present invention is simplified, and in the case of the device of the present invention, the slave units are connected in series. Thus, there is an effect that the number of child devices 11 can be freely increased or decreased.

FIG. 3 shows an explanatory diagram of the branch circuit. The branch circuit shown in the above embodiment has such a configuration. As shown in (a) of the figure, the branch circuit 13 connects the master device 10, the first slave device 11, and another slave device to each other. This branch circuit 13 receives data from the master device 10 and the slave device 1
1 and the data transmission function of transmitting from the upstream to the downstream of the other handset, and the data transmitted from the handset 11 and the data of the other handset to the base unit 10 from the downstream to the upstream. With the data transmission function to go. FIG.
Shown in (b) is a specific connection diagram of the downlink unit 21 that performs data transmission from upstream to downstream. Also,
(C) is a connection diagram of the upstream section 22 that transmits data from downstream to upstream. The down-link unit 21 is configured to invert the signal input from the port P1 by the inverter 23, further invert it by the inverter 24 and output it to the port P2, and invert it using the inverter 25 to output it to the output port P3. . That is, this circuit is configured to output the signal input to the port P1 to the port P2 or the port P3 as it is. In general, the signal input side inverter 23 is called a receiver and the output side inverters 24 and 25 are called drivers. However, since the level of a digital signal causes a problem, they are all called inverters below.

As shown in the figure, the signal input to the port P1 is 1-SD, the signal output from the port P2 is 2-RD, and the signal output from the port P3 is 3-R.
Labeled D. The contents of this signal will be described later. The upstream section 22 shown in (c) includes an inverter 26 that inverts a signal input from the port P2 and an inverter 27 that inverts a signal input from the port P3. The outputs of the inverter 26 and the inverter 27 are input to the inverter 29 via the AND gate 28, inverted, and output to the port P1. In addition, here port P2
2-SD, the signal input to port P3 is 3-SD, the signal output from port P1 is 1-RD
Displayed.

FIG. 4 is an explanatory diagram of the operation of the branch circuit. (A) of this figure shows the contents of the signal concretely.
(B) is a downlink unit 21 that performs data transmission from the master unit to the slave unit.
4C is an explanatory diagram of signals of the upstream section 22 for data transmitted from the slave unit to the master unit. As shown in FIG. 4B, the signal 1-SD input from the parent device to the branch circuit has a value of "1" or "0". On the other hand, the output signal 2-RD of the port P2 and the output signal 3-RD of the port P3 both take the same value as the signal input to the port P1. The results are shown in the figure.

Further, as shown in (c), the signal 2-SD input from the port P2 takes a value of "0" or "1", and the signal 3-SD input from the port P3 is also "0". Alternatively, it takes a value of "1". Four types of cases are shown in FIG. 4C in consideration of the combination of both. In each case, the signal 1-RD output from the port P1 is as shown in the figure. That is, a signal whose content is "0" is output to the port P1 only when the signals input to the port P2 and the port P3 are both "0", and otherwise a signal of "1" is output to the port P1. Will output. Therefore, FIG.
The circuit shown in (c) is configured to output the signal going from the downstream side to the upstream side as it is.

Due to the function of such a branch circuit, FIG.
As shown in FIG. 11, the slave units 11 (1) connected in series with each other
To 11 (n), the data transmitted from the master unit 10 reaches all the slave units, and each slave unit 11 (1) to 11 (n).
The data transmitted from the master device 10 to the master device 10 is always
To enter. Even in such a state, only one slave can transmit data to the master 10 at the same time.
Therefore, it is necessary to prevent contention of data transmission between two or more slave units. Therefore, for example, a well-known polling selection method is used for the master unit and the slave unit so that only the slave unit designated by the master unit is allowed to transmit data. Further, or when data collision occurs, it is recognized and detected, and processing for invalidating or correcting the data is performed. If this function is provided on the base unit side, the above-mentioned bus interface can be effectively used. In addition to this, in order to distinguish each slave unit from the master unit, a fixed address is set in each slave unit, and software assisting means is provided for performing an address match during communication between the master unit and slave unit. You can do it like this.

In addition to the above, for example, RS23 in a branch circuit
It is also possible to delete each inverter that serves as a 2C driver receiver and set the electrical specifications to the TTL level. Also, the interface of the port P3 in the branch circuit is set to TTL.
And set the communication level with the RS232C circuit in the cordless handset to TT
By setting to L, the internal circuit of the slave unit and the branch circuit may be connected at the TTL level to simplify the circuit. It is assumed that the number and combination of the above-described downlink section 21 and uplink section 22 are selected as determined by the interface specifications of RS232C.

FIG. 5 shows a block diagram of a modification of the bus interface of the present invention. In this embodiment, a slave unit control circuit 5 is newly added to the device shown in FIG. That is,
The slave unit control circuit 5 includes a master unit 10 and a first slave unit 11.
It is inserted in the cable 12 connecting (1).
The slave unit control circuit 5 is a circuit that generates a data receivable signal to be output from the master unit and returns it to the slave unit when a control signal for a transmission request output from the slave unit side is input. It is a generally well-known circuit for automatically returning a response signal.

The branch circuit is further provided with a control signal branch section in addition to the data transfer circuit described above. FIG. 6 shows a connection diagram of such a control signal branching unit. This control signal branching unit also has ports P1, P2 and P3, just like the branching circuit for data transmission. The port P1 is connected to the master unit side, the port P2 is connected to another slave unit side, and the port P3 is connected to its own slave unit.

In this circuit, an inverter 31 for inverting the control signal from the master unit input from the port P1, an AND gate 32 for outputting this signal to the port P2,
An AND gate 34 for outputting to the port P3, an inverter 33 that inverts the output of the AND gate 32 and sends it to the port P2, and an inverter 35 that inverts the signal output from the AND gate 34 and outputs it to the port P3. There is.
Further, an inverter 36 for inverting a signal input from the port P2 and an inverter 37 for inverting a signal input from the port P3 are provided to transmit a control signal transmitted from the child device to the parent device. . Both inverters 3
The outputs of 6 and 37 are input to the AND gate 38, and the outputs thereof are inverted by the inverter 39 and output to the port P1.

In addition, the circuit includes inverters 36 and 37.
Contention adjustment circuit 4 for receiving the output of the AND gate, generating a signal for contention adjustment, and controlling the opening and closing of the AND gates 32 and 34.
0 is provided. The competition adjustment circuit 40 has a well-known connection that outputs a constant signal by combining a pair of NAND gates 41 and 42 and receiving one output from the other output. Thus, when the transmission request signal is input from the port P2 or the port P3 to the master device, the AND gate 32 outputs the response signal returned as a response from the master device only to the port that issued the request. , 34 are controlled.

FIG. 7 shows an operation explanatory diagram of the control signal branch. In the figure, (a) shows the input / output signals of the respective ports described above, and (b) and (c) show operation explanatory diagrams of the competition adjustment circuit. As shown in the figure, the contention adjusting circuit 40 opens the AND gate 32 on the side of the other handset when the transmission request is made from one of the handset, for example, the handset on the side of the port P2, while opening the AND gate 32 on the other side. Close 34. by this,
As shown in (b) of the figure, the response signal is transferred from the parent device side only to the child device side that has made the transmission request. (C) shows an example of a case where there is a transmission request from the slave unit on the port P3 side,
This time, the AND gate 34 is opened while the AND gate 32 is closed.

That is, as shown in FIG.
In contrast, when a plurality of slave units 11 (1) to 11 (n) are connected to each other and a data transfer request is issued from any of the slave units to the master unit 10, the master is routed via the control signal branching unit shown in FIG. The data transfer request is transmitted to the machine. In this case, the slave unit control circuit 5 shown in FIG. 5 receives the data transfer request signal from the slave unit, generates a response signal, and returns it to the slave unit as it is. Therefore, when the child device issues a data transfer request signal, a response is returned instantly without the judgment and arithmetic processing by the parent device 10. The response in this case is transmitted only to the child device which has issued the transfer request by the contention adjusting circuit 40 shown in FIG. Therefore, since no response is input to other slaves, only one slave can transfer data to the master. Here, consider a case where two or more handset units issue data transfer requests one after another. In this case, the competition adjustment circuit 40 operates so as to transfer the response signal only to the side to which the request signal is input first, so that the competition adjustment can be performed.

The present invention is not limited to the above embodiments. Although the RS232C interface is illustrated as the bus interface in the above example, it can be widely applied to other well-known bus interfaces. Also in the above embodiment, in order for the master to identify each slave, it is preferable to add another code for address identification to each slave. Further, although the above-described embodiment shows an example in which the present invention is used for one-to-N communication, a similar configuration can be adopted when there are a plurality of parent devices and a plurality of child devices. Further, the connection of the competition adjustment circuit can be freely changed as long as it has a similar function.

[0024]

According to the bus interface of the present invention described above, a branch circuit is provided in each slave unit, and the slave units are connected in series from the master unit via each branch circuit so as to connect the master unit and the slave unit. Since it has a configuration that enables data transmission and reception of control signals,
A bus connection with a large number of child devices becomes possible without providing many communication ports in the parent device. Also, by providing a certain contention adjustment circuit in the branch circuit, it becomes possible for the slave unit that has requested the data transmission earliest to transmit data to the master unit. It can be a bus interface that can adjust contention.

[Brief description of the drawings]

FIG. 1 is a block diagram of a bus interface of the present invention.

FIG. 2 is a schematic operation explanatory diagram of a bus interface of the present invention.

FIG. 3 is an explanatory diagram of a branch circuit.

FIG. 4 is an operation explanatory diagram of a branch circuit.

FIG. 5 is a block diagram of a modification of the bus interface of the present invention.

FIG. 6 is a connection diagram of a control signal branching unit.

FIG. 7 is an operation explanatory diagram of a control signal branching unit.

[Explanation of symbols]

 10 parent device 11 (1) to 11 (N) child device 12 cable 13 branch circuit 14 internal RS232C standard utilization circuit

Claims (2)

[Claims] 1. A master unit and a plurality of slave units are sequentially connected in series via a branch circuit provided in each slave unit, wherein the branch circuit includes a master unit to a slave unit. An input port that receives data transmitted to the parent device, an output port that receives data transmitted from the parent device to itself via this input port, and an external port from the parent device via the input port Output port that directly transfers the data transmitted to the succeeding slave unit, an input port that inputs the data that is transmitted from itself to the master unit, and is transmitted from another slave unit to the master unit. A bus interface comprising an input port for receiving data and an output port for outputting data transmitted from a slave unit to a master unit via these input ports. 2. A master unit and a plurality of slave units are serially connected in series via a branch circuit provided in each slave unit, wherein the branch circuit is connected from the master unit to the slave units. An input port that receives a control signal transmitted to the master unit, an output port that receives a control signal transmitted from the master unit to the self unit via this input port, and another port from the master unit via the input port. An output port that transfers the control signal transmitted to the slave unit to the succeeding slave unit as it is, an input port that inputs the control signal transmitted from itself to the master unit, and another slave unit to the master unit. Equipped with input ports that accept control signals transmitted from the slave unit and output ports that output control signals transmitted from the slave unit to the master unit via these input ports. Control signals transmitted to each other competed Equipped with a competition adjustment circuit that determines which control signal from the slave unit is input to the branch circuit first and returns the response signal generated in the branch circuit to the slave unit to which the control signal was input first. Bus interface characterized by