JP2833801B2 - Data multiplex transfer method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data multiplex transfer method for fixed-length data in an asynchronous transfer mode in wideband ISDN.

[Conventional technology]

Conventionally, this type of data multiplex transfer system includes a contention prevention circuit that analyzes a data transmission request input for data from all multiplexed lines and outputs a data transmission permission signal only to one line. Was.

FIG. 4 is a circuit diagram showing an example of a conventional data multiplex transfer system.

In FIG. 4, the conventional data multiplexing transfer system employs a contention prevention circuit 41 for four data transmission request inputs by four 4-input AND circuits, four 2-input AND circuits and one 4-input OR. And a selection circuit 42 for selecting one of the four input data by the circuit.

[Problems to be solved by the invention]

The above-described conventional data multiplex transfer method has a contention prevention circuit that analyzes a data transmission request input signal for data from all lines to be multiplexed and outputs a data transmission permission signal only to one line only. So
In order to control the priority of input data, it is necessary to prepare a special circuit, and there is a disadvantage that the expandability of the contention prevention circuit is poor when the number of data input lines increases.

[Means for solving the problem]

According to the data multiplex transfer method of the present invention, the (i-1) -th data (i-th data) including a busy bit input to the first input terminal is used.
>1; i = 0, i.e., all "0" data. )
Or the i-th data including a busy bit inputted to the second input terminal is selected by the synchronization signal when the data transmission request signal of the i-th data is received. The i-th data is selected only when the busy bit of the i-th data is detected as "0", and a data transmission permission signal is sent to the transmission source of the i-th data to transmit the i-th data. From the output terminal of the i-th data selection device, which outputs the data from the output terminal of the i-th data selection device, or the busy bit input to the second input terminal. When the data transmission request signal of the (i + 1) th data is received, the synchronization signal is used to select either the (i + 1) th data or the (i + 1) th data from the output terminal of the (i) th data selection device. The i + 1-th data is selected only when "0" is detected in the data busy bit, and a data transmission permission signal is sent to the (i + 1) -th data transmission source to output the (i + 1) -th data. And an (i + 1) th data selection device to be transmitted from the terminal.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of a selecting device which is a component of the present embodiment in FIG. 1, and FIG. 6 is a time chart of signals input / output to each input / output terminal of the selection device.

In FIG. 1, this embodiment has four selection devices 1-1, 1-1.
-2, 1-3 and 1-4, and the selecting device 1-
Synchronous signal input terminals SY are connected to 1, 1-2, 1-3 and 1-4 respectively.
NC, a first data string input terminal DIN1, a second data string input terminal DIN2, a data string transmission request input terminal REQ, a data transmission permission output terminal ACK to the outside (FIFO memory),
A data string output DOUT for outputting a data string selected from the first or second data string, and a data string output terminal DOUT of the selecting device 1-1 for inputting the highest-order data string is connected to the next stage. It is connected to the first data string input terminal DIN1 of the selection device 1-2, and so on.
DOUT is configured to be connected to the first data string input terminal DIN1 of the selection device 1-4 for inputting the lowest data string.

FIG. 1 shows a selection device 1-1, 1-2, 1 in the present embodiment.
Reference numerals -3 and 1-4 indicate the circuit configuration of the selection device 1 shown in FIG.

In FIG. 2, the selecting device 1 in the present embodiment is the first device.
A selection circuit 11 for selecting either the first data string A input to the data string input terminal DIN1 or the data string B input to the second data string input terminal DIN2 in FIG. A flip-flop circuit (hereinafter referred to as F / F) 12 which outputs a set signal by a synchronization signal when there is no data string transmission request signal (REQ), And a two-input AND circuit 14 that outputs a data transmission enable signal (ACK) in response to a set signal.

Next, the operation of the selection device shown in FIG. 2 will be described with reference to FIG.

In the following description, a data string is a data string of a predetermined fixed length.

As shown in FIG. 3, the first data string and the second data string each have a busy bit 3 at the beginning, and when the busy bit 3 is "1", it indicates that there is data.
"0" indicates that there is no data.

Now, when a first data string including valid data "A" is input to DIN1, even if a synchronization signal is input to SYNC, the busy bit of the first data string is "1". Even if the transmission request signal REQ is active (“1”), the F / F is not set, so that the data transmission permission signal A does not become active (“1”), and DOUT contains valid data “A”. Is output. When the next sync signal is input,
When empty data is input to the first data string, the busy bit is "0", so F / F12 is set, the data transmission enable signal ACK becomes active ("1"), and DIN2 is valid. A second data string including data B is input and DOUT
Outputs a second data string including valid data “B”.

Next, the operation of the present embodiment shown in FIG. 1 will be described with reference to FIG. 2 and FIG.

Since the column input terminal DIN1 of the first data is fixed to "0", the selecting device 1-1 sets the data sequence transmission request signal REQ
Is input, the data transmission enable signal ACK is stored in the FIFO memory 2
-1, and the data string from the FIFO memory 2-1 is output from DOUT of the selection device 1-1. Selector 1-2 first
Is input to the data string input terminal DIN1 of the selection device 1-1. For example, even if the data sequence transmission request signal REQ from the FIFO memory 2-2 is input to the selection device 1-2, Since the F / F 12 is not set as shown in FIG. 2, the data transmission permission signal ACK is not transmitted to the FIFO memory 2-2, and therefore, the selection device 1-2 is not transmitted from the DOUT of the selection device 1-2.
-1 is transmitted from the FIFO 2-1. Less than,
The selecting devices 1-3 and 1-4 operate in the same manner as the selecting device 1-2, and finally the selecting devices 1-4 are output from the DOUT of the selecting device 1-4.
The data string of FIFO2-1 from 1 is output.

That is, the data sequence of the first priority is output from the selection device 1-1, transferred to the selection device 1-4, and the data of the first priority from DOUT of the selection device 1-4 is output. I do.

Similarly, the selecting device 1-2 outputs the second-priority data sequence from the FIFO 2-2 when there is no first-priority data sequence, and the selecting device 1-3 outputs the first-priority data sequence. When there is no data sequence of the second and third places, the data of the third place in the priority order is output from the FIFO 2-3, and the selecting device 1-4 outputs the data of the first place, the second place and the third place in the priority order. In both cases, the least significant data string from FIFO2-4 is output.

From the above results, from the DOUT of the selection device 1-4, each FIFO memory 2-D according to the priority order according to the presence / absence of upper data.
The data strings from 1,2-2,2-3,2-4 are multiplexed and transferred.

[Effects of the Invention] As described above, according to the present invention, the data from the i-th data selection device input to the first input terminal or the (i + 1) -th data input from the second input terminal A special priority control circuit can be selected by selecting an i + 1-th data selection device that sends out the (i + 1) -th data from the output terminal only when the busy bit of the i-th data is “0”. The first priority is given to the line connected to the second data input terminal of the first stage data selection device, and the second priority is given to the line connected to the second data input terminal of the next stage data selection device.
Has the effect that a priority control configuration can be naturally given such as giving the second priority to the line connected to the data input terminal of the data input terminal. In addition, since the connection of the data selection device is repetitive, the expandability is good, There is an effect that the number of data input lines can be easily increased.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of a selection device which is a constituent element of this embodiment in FIG. 1, and FIG. FIG. 4 is a circuit diagram showing an example of a conventional data multiplexing transfer method. 1,1-1,1-2,1-3,1-4, ... selection device, 2-1,2-2,2-
3,2-4 ... FIFO memory, 3 ... Busy bit, 11 ...
Selection circuit, 12 ... Flip-flop circuit (F / F), 13 ...
... 3-input AND circuit, 14 ... 2-input AND circuit, 41 ...
Contention prevention circuit, 42 selection circuit.

Claims (1)

(57) [Claims] 1. An (i-1) -th data including a busy bit input to a first input terminal (i is an integer of i> 1, and if i = 0, all data is "0") or The selection of either the i-th data including the busy bit input to the second input terminal or the i-th data is performed by a synchronization signal when a data transmission request signal of the i-th data is received.
The i-th data is selected only when the busy bit of the i-th data is detected as "0", and a data transmission permission signal is sent to the transmission source of the i-th data to transmit the i-th data. From the output terminal of the i-th data selection device, which outputs the data from the output terminal of the i-th data selection device, or the busy bit input to the second input terminal. When the data transmission request signal of the (i + 1) -th data is received, the synchronization signal is used to select the (i + 1) -th data or any one of the (i + 1) -th data. Only when “0” is detected, the i-th
An (i + 1) th data selection device for selecting the (+1) th data, transmitting a data transmission permission signal to the (i + 1) th data transmission source, and transmitting the (i + 1) th data from an output terminal. A data multiplex transfer method characterized in that data having a small number of i-numbers is preferentially transmitted.