JPH0427243A - Atm cell concentrating system - Google Patents

Atm cell concentrating system

Info

Publication number
JPH0427243A
JPH0427243A JP2131827A JP13182790A JPH0427243A JP H0427243 A JPH0427243 A JP H0427243A JP 2131827 A JP2131827 A JP 2131827A JP 13182790 A JP13182790 A JP 13182790A JP H0427243 A JPH0427243 A JP H0427243A
Authority
JP
Japan
Prior art keywords
control circuit
buffer memories
atm cell
output request
input ports
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2131827A
Other languages
Japanese (ja)
Inventor
Shigenori Nagara
長良 繁徳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2131827A priority Critical patent/JPH0427243A/en
Publication of JPH0427243A publication Critical patent/JPH0427243A/en
Pending legal-status Critical Current

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  • Data Exchanges In Wide-Area Networks (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)

Abstract

PURPOSE:To add the function for concentrating an ATM cell by providing a buffer memory corresponding to an input port, and a competition control circuit for inputting an output request signal outputted therefrom, and executing the competition control of an output request signal by the competition control circuit. CONSTITUTION:Now, when an ATM cell arrives in plural input ports, and is accumulated in buffer memories 1, 2, 3 and 4 corresponding to the respective input ports, the buffer memories 1, 2, 3 and 4 send out Reqs 6, 9, 12 and 15 to a competition control circuit 5. The competition control circuit 5 selects one signal, for instance, the Req 6 from in the received Reqs 6, 9, 12 and 15, and sends out an Ack 8 to the buffer memory 1 which sends out its Req 6. The buffer memory 1 which receives the Ack 8 sends out an accumulated Cell 7 to the competition circuit 5. In such a way, the Cells 7, 11, 13 and 16 accumulated in the buffer memories 2, 3 and 4 are sent out, by which the number of pieces of transmission lines can be decreased without changing a transmission speed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はATMセル集線方式に関し、特に複数の入力ポ
ートが入力するATVセル列を一つの出力ポートに出力
させるATMセル集線方式に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an ATM cell line concentration system, and more particularly to an ATM cell line concentration system in which an ATV cell string inputted by a plurality of input ports is outputted to a single output port.

〔従来の技術〕[Conventional technology]

従来のATMスイッチ網では、ATMセル集線方式につ
いて特に考慮したものは無く、若し必要があれば、AT
Mセルに付けたラベルの表示に従って伝達されるとき、
自動的に成された経路選択が集線機能と同等の効果を発
生するようにすればよいと考えていた。しかしながら実
際にATMスイッチ網を考慮するとき、入力されたAT
Mセルを、いかに能率良く次段に伝達するかが重要課題
であり、ハードの経済化については、あまり考慮したも
のではなかった。
In conventional ATM switch networks, there is no special consideration given to the ATM cell concentration method, and if necessary, ATM
When transmitted according to the label attached to the M cell,
The idea was that automatically route selection would have the same effect as the concentrator function. However, when actually considering an ATM switch network, the input AT
The important issue was how to efficiently transmit the M cell to the next stage, and little consideration was given to making the hardware economical.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のATMスイッチ網では、ATMセルの伝
達については考慮しているが、実際には、個々の回線の
ATMセルの呼量が少ないため、集線方式を使用して伝
送速度を変えずにATMセルを伝達する伝送線の本数を
減少させることが可能であり、ATMスイッチ網内に取
入れても機能上は十分に満足する場合でも、これまでA
TMスイッチ網の構成上に取入れられた集線機能がない
ため、ハードをより多く使用するスイッチ網構成としな
ければならないという問題点がある。
In the conventional ATM switch network described above, the transmission of ATM cells is taken into account, but in reality, the number of calls for ATM cells on individual lines is small, so a line concentration method is used to transfer the ATM cells without changing the transmission speed. Although it is possible to reduce the number of transmission lines that transmit ATM cells, and it is functionally satisfactory even if incorporated into the ATM switch network, until now A
Since there is no line concentration function incorporated into the configuration of the TM switch network, there is a problem in that the switch network configuration must use more hardware.

本発明の目的は、複数の入力ポートに対応する複数のバ
ッファメモリと、この複数のバッファメモリが出す出力
要求信号を入力する競合制御回路とを設け、この競合制
御回路は前述の複数のバッファメモリが出す出力要求信
号の競合制御を行うことにより、ATVスイッチ網に使
用して、ハードを大幅に増加させずにATVセルを集線
する機能を付加することができるATMセル集線方式を
提供することにある。
An object of the present invention is to provide a plurality of buffer memories corresponding to a plurality of input ports and a contention control circuit that inputs output request signals issued by the plurality of buffer memories, and this contention control circuit is configured to provide a plurality of buffer memories that correspond to a plurality of input ports. To provide an ATM cell concentration system that can be used in an ATV switch network to add a function of concentrating ATV cells without significantly increasing hardware by controlling competition between output request signals issued by the ATM. be.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のATMセル集線方式は、ATMスイッチ網での
ATVセル集線方式において、複数の入力ポートに対応
する複数のバッファメモリと、前記複数のバッファメモ
リが出す出力要求信号を入力する競合制御回路とを有し
、前記競合制御回路は前記複数のバッファメモリが出す
出力要求信号の競合制御を行い、前記出力要求信号を出
したバッファメモリの一つに出力許可信号を送出するこ
とにより前記複数の入力ポートが入力するATMセル列
を一つの出力ポートに出力させる集線機能を実現する構
成である。
The ATM cell concentration method of the present invention is an ATV cell concentration method in an ATM switch network, which includes a plurality of buffer memories corresponding to a plurality of input ports, and a contention control circuit that inputs output request signals issued by the plurality of buffer memories. and the contention control circuit performs contention control on output request signals issued by the plurality of buffer memories, and transmits an output permission signal to one of the buffer memories that has issued the output request signal, thereby controlling the number of inputs of the plurality of inputs. This configuration realizes a line concentration function in which an ATM cell string inputted by a port is outputted to one output port.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例のブロック図である。FIG. 1 is a block diagram of one embodiment of the present invention.

複数の入力ポートに対応するバッファメモリl。Buffer memory l corresponding to multiple input ports.

2.3.4は、それぞれ競合制御回路5に接続し、出力
要求信号(以下Reqと記す)6,9.12゜15を送
出することができ、競合制御回路5の出力する出力許可
信号(以下Ackと記す)8゜11.14.17を受信
すると、受信したバッファメモリ1,2,3.4の中の
一つがATMセル出力データ(以下Ce1lと記す)7
,10゜13.16の中の一つを送出する。
2.3.4 are connected to the competition control circuit 5, respectively, and can send out output request signals (hereinafter referred to as Req) 6, 9.12°15, and output permission signals ( When 8°11.14.17 (hereinafter referred to as Ack) is received, one of the received buffer memories 1, 2, and 3.4 receives ATM cell output data (hereinafter referred to as Ce1l) 7.
, 10°13.16.

次に動作について説明する。Next, the operation will be explained.

今、複数の入力ポートにATMセルが到着し、それぞれ
の入力ポートに対応するバッファメモリ1.2,3.4
に蓄積されると、バッファメモリ1.2,3.4は、競
合制御回路5にReq6゜9.12.15を送出する。
Now, ATM cells arrive at multiple input ports, and buffer memories 1.2 and 3.4 correspond to each input port.
, the buffer memories 1.2 and 3.4 send Req6°9.12.15 to the contention control circuit 5.

競合制御回路5は、受信したR e q 6 、9 、
1 ’2 、  l 5の中から、つの信号例えばRe
q6を選択し、そのReq6を送出したバッファメモリ
1にA c k 8を送出する。Ack8を受信したバ
ッファメモリ1は、蓄積しているCe117を、競合制
御回路5に送出する。
The competition control circuit 5 receives the received Req 6, 9,
1 '2, l 5, one signal e.g. Re
Selects Req6 and sends A c k 8 to buffer memory 1 that sent Req6. The buffer memory 1 that has received Ack8 sends the accumulated Ce117 to the competition control circuit 5.

このようにして、順次、バッファメモリ2.3゜4に蓄
積されているCe1llO,13,16を送出し、これ
によって、伝送速度を変えずに伝送線の本数を減少させ
ることが可能となる。
In this way, Ce1llO, 13, and 16 stored in the buffer memory 2.3.4 are sequentially sent out, thereby making it possible to reduce the number of transmission lines without changing the transmission speed.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は、複数の入力ポートに対
応する複数のバッファメモリと、この複数のバッファメ
モリが出す出力要求信号を入力する競合制御回路とを設
け、この競合制御回路は前述の複数のバッファメモリが
出す出力要求信号の競合制御を行うことにより、ATM
スイッチ網に使用して、ハードを大幅に増加させずにA
TMセルを集線する機能を付加することができる効果が
有る。
As explained above, the present invention includes a plurality of buffer memories corresponding to a plurality of input ports, and a contention control circuit that inputs output request signals issued by the plurality of buffer memories, and this contention control circuit is configured as described above. By controlling the contention of output request signals issued by multiple buffer memories, ATM
Can be used in switch networks to achieve A without significantly increasing hardware.
This has the effect of adding a function of concentrating TM cells.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例のブロック図である。 1.2.3.4・・・・・・バッファメモリ、5・・・
・・・競合制御回路、6.9.12.15・・・・・・
出力要求信号(Re q) 、 7..10.13.1
6・−−−−−ATMセル出力データ(Ce I I)
、8,11,14゜17・・・・・・出力許可信号(A
ck)。 代理人 弁理士  内 原  晋
FIG. 1 is a block diagram of one embodiment of the present invention. 1.2.3.4...Buffer memory, 5...
...Conflict control circuit, 6.9.12.15...
Output request signal (Req), 7. .. 10.13.1
6.----ATM cell output data (Ce II)
, 8, 11, 14° 17...Output permission signal (A
ck). Agent Patent Attorney Susumu Uchihara

Claims (1)

【特許請求の範囲】[Claims] ATMスイッチ網でのATMセル集線方式において、複
数の入力ポートに対応する複数のバッファメモリと、前
記複数のバッファメモリが出す出力要求信号を入力する
競合制御回路とを有し、前記競合制御回路は前記複数の
バッファメモリが出す出力要求信号の競合制御を行い、
前記出力要求信号を出したバッファメモリの一つに出力
許可信号を送出することにより前記複数の入力ポートが
入力するATMセル列を一つの出力ポートに出力させる
集線機能を実現することを特徴とするATMセル集線方
式。
An ATM cell concentration system in an ATM switch network includes a plurality of buffer memories corresponding to a plurality of input ports, and a contention control circuit that inputs output request signals issued by the plurality of buffer memories, the contention control circuit comprising: performing competition control of output request signals issued by the plurality of buffer memories;
The present invention is characterized in that by sending an output permission signal to one of the buffer memories that has issued the output request signal, a line concentration function is realized in which the ATM cell strings inputted by the plurality of input ports are outputted to one output port. ATM cell concentration method.
JP2131827A 1990-05-22 1990-05-22 Atm cell concentrating system Pending JPH0427243A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2131827A JPH0427243A (en) 1990-05-22 1990-05-22 Atm cell concentrating system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2131827A JPH0427243A (en) 1990-05-22 1990-05-22 Atm cell concentrating system

Publications (1)

Publication Number Publication Date
JPH0427243A true JPH0427243A (en) 1992-01-30

Family

ID=15067029

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2131827A Pending JPH0427243A (en) 1990-05-22 1990-05-22 Atm cell concentrating system

Country Status (1)

Country Link
JP (1) JPH0427243A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0653989A (en) * 1992-07-29 1994-02-25 Nec Corp Atm cell multiple circuit
US7678876B2 (en) 2004-12-02 2010-03-16 Dsm Ip Assets B.V. Hydroxy-aromatic compound, process for the preparation thereof, and use of the compound

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0653989A (en) * 1992-07-29 1994-02-25 Nec Corp Atm cell multiple circuit
US7678876B2 (en) 2004-12-02 2010-03-16 Dsm Ip Assets B.V. Hydroxy-aromatic compound, process for the preparation thereof, and use of the compound

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