JPH0696017A - In-device wiring method - Google Patents

Abstract

PURPOSE:To decrease the number of wirings required to transfer parallel signals among respective packages in a device and to easily change the wirings. CONSTITUTION:In synchronism with a synchronous signal 5 and a clock signal 6 in the device, the parallel signals sent out of the respective packages 1A, 1B, and 1C are converted by interface circuits 2A, 2B, and 2C into serial signals; and the signals to be connected by the individual packages among all the converted serial signals are registered in the memories 13 of the respective interface circuits 2A, 2B, and 2C, the signals to be connected are latched from all the converted serial signals, and then serial/parallel conversion is performed again to secure connections among the packages.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring method in a device,
In particular, the present invention relates to an in-device wiring method for ensuring signal connection between packages by means of a parallel signal output from each package in a device containing a plurality of packages.

[0002]

2. Description of the Related Art A conventional wiring method in this type of device is shown in FIG.
As shown in FIG. 3, wiring is provided so as to connect parallel signals between the plurality of packages in the device, in the case of FIG. 3, the three packages A101, B102 and C103 in a one-to-one relationship. .

[0003]

In the conventional wiring method in the device, since the signals are connected so that the signals between the packages in the device are connected in a one-to-one correspondence, the number of wires in the device is remarkably large. However, there is a drawback in that the wiring must be changed unconditionally when the number of packages in the device is changed.

It is an object of the present invention to provide an in-device wiring method that eliminates the above-mentioned drawbacks, significantly reduces the number of wires in the device, and eliminates the need to change the wiring for changing the package.

[0005]

According to the method of wiring in a device of the present invention, a parallel signal sent from a plurality of packages in the device is synchronized with a synchronizing signal and a clock signal in the device on one serial signal line. And each of the plurality of packages has a built-in memory, registers the position of the signal on the serial signal line to be connected to the self-package in the memory, latches the signal, and performs serial / parallel conversion The signal connection between the packages in the apparatus is performed by applying the above.

Further, the in-device wiring method of the present invention has a structure in which the signal on the serial signal line is latched on the basis of ensuring synchronization with a synchronization signal and a clock signal in the device.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention. Figure 1
In the embodiment shown in FIG. 1, an intra-device connection method that enables parallel signal input / output between three packages in the device is taken as an example, and an interface that interfaces three packages 1A, 1B and 1C and signals between the packages. Circuit 2
A, 2B and 2C, a synchronizing signal 5 in the apparatus, a clock signal 6 in the apparatus, and a multiplexed serial signal line 7 for multiplexing and transferring a serial signal obtained by converting a parallel signal exchanged between packages.

In addition, the interfaces 2A, 2B and 2
C is a parallel / serial converter 8 for converting a parallel signal into a serial signal, an n-ary multiplexing counter 9, an output signal transmission counter 10, a comparator 11, an output signal transmission setting switch 12, and each. A memory 13 for registering connection required signals for each package, and a shift register 14
In addition to the latch circuit 15 and the gate circuit 18 for controlling the output gate, an AND gate 20 is provided.

Next, the operation of this embodiment will be described.

The n parallel output signals 3 are supplied to the parallel / serial converter 8 and converted into serial signals in synchronization with the output count value of the n-ary multiplexing counter 9 driven by the synchronizing signal 5 and the clock signal 6. Gate circuit 18
Entered in.

The output signal transmitting counter 10 operates according to the output count value of the n-ary multiplex counter 9 and the synchronizing signal 5, and sends the output count value to the comparator 11.

The comparator 11 supplies the output signal transmission gate signal 17 to the gate circuit 18 when the value established by the output signal transmission setting switch 12 coincides with the input value, and the parallel / serial converter 8 operates. A serial signal having an n-bit structure is sent to the multiplexed serial signal line 7.

The multiplexed serial signal line 7 is connected to the shift registers 14 of the packages 1A, 1B and 1C.

The memory 13 is supplied with a memory address 16 set by the output count values of the n-ary multiplex counter 9 and the output signal sending counter 10, and is synchronized with the synchronizing signal 5 and the clock signal 6 in the memory. The data is read.

FIG. 2 shows the timing relationship among the synchronizing signal 5, the clock signal 6, the multiplexed serial signal and the memory address signal 16.

Of the multiplexed signals on the serial signal line 7 multiplexed by the package 1A, when connecting the signal of the 4th bit, data "1" is set at the address 4 of the memory 13.

When this setting is made, the memory address 16
Is “4”, the memory output signal 19 is read from the memory 13 as “1”, the clock signal 6 is supplied to the shift register 14 via the AND gate 20, and the multiplexed signal on the multiplexed signal line 7 Of these, the signal of the fourth bit is read into the shift register 14.

In this way, data "1" is set in the memory 13 for all signals that need to be connected, and all the signals to be connected are read into the shift register 14. The output of the shift register 14 is supplied to the latch circuit 15 and converted into a parallel input signal 4. In this way, the packages can be arbitrarily connected by setting the data in the memory 13.

[0019]

As described above, the present invention synchronizes with the synchronizing signal and the clock signal in the device, and multiplexes the parallel signals sent from each package in the device on one serial signal line. By registering the signals that need to be connected to the memory in each package, the signals can be connected between each package with only three wires, and the data settings in the memory can be used to set any signal between the packages. There is an effect that can be connected.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a timing chart of the synchronization signal, clock signal, multiplexed serial signal and memory address of FIG.

FIG. 3 is a block diagram showing a conventional in-device wiring method.

[Explanation of symbols]

 1A, 1B, 1C Package 2A, 2B, 2C Interface circuit 3 Parallel output signal 4 Parallel input signal 5 Synchronous signal 6 Clock signal 7 Multiplexed serial signal line 8 Parallel / serial converter 9 n-ary multiplexing counter 10 For output signal transmission Counter 11 Comparator 12 Output signal transmission setting switch 13 Memory 14 Shift register 15 Latch circuit 16 Memory address 17 Output signal transmission gate signal 18 Gate circuit 19 Memory output signal 20 AND gate

Claims (2)

[Claims] 1. A parallel signal transmitted from a plurality of packages in a device is multiplexed on a single serial signal line in synchronization with a synchronization signal and a clock signal in the device,
Further, each of the plurality of packages has a built-in memory, the position of the signal on the serial signal line to be connected to the package is registered in the memory, the signal is latched, and serial / parallel conversion is performed on the signal. An in-device wiring method characterized by performing signal connection between in-device packages. 2. The in-device wiring method according to claim 1, wherein the signal on the serial signal line is latched on the basis of ensuring synchronization with a synchronization signal and a clock signal in the device.