JPH02171050A - Isdn interface circuit - Google Patents

Abstract

PURPOSE:To compensate a delay time for a receiver and a driver and to allow the deviation in transmission/reception timing to be within the standards by providing a phase shift circuit shifting the phase of a lock signal stepwise and a selector. CONSTITUTION:A signal received by a receiver 1 is fed to a frame decomposing section 6 and a clock extraction section 2, a data is fed to a driver 3 from a frame composing section 7 via a FF 8 and the data is sent based on a clock signal extracted from the clock extraction section 2. In this case, a phase shift circuit 4 consists of a shift register or the like, a clock signal extracted by the clock extraction section 2 by a high speed clock signal is shifted to output plural clock signals having stepwise phase differences in parallel. Then the clock signal of a desired phase of plural clock signals is selected by a selector 5 to obtain a transition clock. Thus, the delay time of the receiver 1 and the driver 3 is compensated to allow the deviation of the transmission/reception timing to be within the standards.

Description

[Detailed description of the invention] [Summary] I5DN basic user network interface reference point S/
Regarding the ISDN interface circuit in T, the purpose is to compensate for the delay time of the receiver and driver and keep the deviation in transmission and reception timing within the standard. In an ISDN interface circuit at an interface reference point S/T having a driver that transmits a clock signal based on the clock signal extracted by the clock extracting section, the phase of the clock signal extracted by the clock extracting section is determined. The present invention includes a phase shift circuit that shifts in stages, and a selector that selects a clock signal phase-shifted by the phase shift circuit and applies it to the driver so as to compensate for the delay time of the receiver and driver.

[Industrial application field]

The present invention relates to an ISDN interface circuit in an I5DN basic user network interface reference point S/T.

In the I5DN (integrated service digital network), the allowable timing range between the received frame and the transmitted frame at the basic user network interface reference point S/T is standardized, and in order to meet this standard, It is necessary to configure an interface circuit.

[Conventional technology]

The I5DN basic user network interface has two 64 Kb/s B channels and 16
2 days + D with one D channel of K b / s
configuration is used.

FIG. 4 is an explanatory diagram of interface reference points, in which the network 31 includes an rsDN exchange, etc., and transmission lines 40 to 42.
via network terminal equipment (NTl) 32, 35.3 respectively.
7 is connected, and the interface reference point between the network termination device 32 and the network termination device (NT2) 33, which corresponds to a private branch exchange, is T, &14 termination C: between the ij device 33 and the l5DN terminal device (TEI) 34. Let S be the interface reference point between them. In addition, when an ISDN terminal device (station) 36 is connected to the network termination device 35, the interface reference points S and T are the same, so it is expressed as S/.

In addition, the existing terminal device (TE2) 39 is equipped with a terminal adapter (T
A) 38'c intermediary M414'A'AT137
In this case, the interface reference point between the network termination device 37 and the terminal adapter 38 is represented by S/bottom, and the interface reference point between the terminal adapter 38 and the existing terminal device 39 is represented by R. Ru.

FIG. 5 is an explanatory diagram of the frame structure at the interface reference point S/T, where one frame consists of 48 pips (1-(250 pi)).
μs) from the network termination device NT to the terminal device T.
The E force direction is transmitted in a configuration shown as NT-TE, and the power direction from the terminal device TE to the network termination device NT is transmitted in a configuration shown as TE-NT, using a 192 KHz clock signal.

Also, the transmitted and received frames have a 2-bit offset,
” is transmitted by a bipolar signal in which “0” is a pulse of positive and negative polarity, D is the D channel bit, and L
is the DC balance bit, F is the framing bit, Bl is B
Channel 1 data bit, B2 is the B channel 2 data bit, A is the bit used for activation, FA is the auxiliary frame bit, N is the auxiliary frame bit (binary complement n of FA), E is the D channel echo bit , S are 6M bits, and M is a multi-framing bit.

A plurality of terminal bags fiTE are connected to the network terminal equipment NT via 4-green lotuses with two transmitting lines and two receiving lines, and a 2-bit offset is specified at the interface reference point S/T. , its deviation Δ is −0.4 μs to +0.8
Since the range of μs is allowed, the transmission delay is set to 1.5 bits (7,8 μs), and the remaining 0.5 bits 1-(2,
6 μs) to the receiver 51 and driver 53 within the range of deviation Δ.
This method uses a delay due to

In addition, in the frame structure described above, when the own terminal device transmits, it retains the D channel bit D, and this D channel bit D is returned from the network terminal device NT and becomes the echo bit E. Compare with l-E, if they match, it means that no other terminal device is transmitting, and if they do not match, it means that another terminal device is transmitting and a collision has occurred, so transmission will be temporarily stopped. It is something to do.

Conventionally, the interface circuit in the terminal device TE has, for example, the configuration shown in FIG.
55 is an inverter, 56 is a frame disassembly section, and 57 is a frame assembly section. FIG. 7 is an explanatory diagram of the operation, in which (a) is the clock signal extracted by the clock extractor 52, fb) is the received data, fcl is the receiver output data, (dl is the driver input data, and te is the clock signal extracted by the clock extractor 52.
l indicates transmission data. In addition, Δt PLL is the delay time caused by the DPLL (digital phase locked loop) circuit in the clock extraction section 52, and tl is 1.5 bits (7, Lu
5) minute delay time, Δt,l is the delay time of the receiver 51, Δt is the delay time of the driver 53, Δtl,* is the sum of the delay time of the driver 53 and the delay time of the receiver 51.

If the received data applied to the receiver 51 is (bl), the data is output as shown in (C) after a delay time Δ1 of the receiver 51. This receiver output data is transmitted to the clock extractor 52 and frame decomposer 56. added to,
After the delay time At PLL by the DPLL circuit etc. in the clock extractor 52, the clock signal shown in (al) is extracted. Therefore, the clock signal is
Output after tIl+Δt PLL.

This clock signal is applied to clock terminal C of flip-flop 54 via inverter 55. Also, data from the frame assembly section 57 is applied to the data terminal of the flip-flop 54, and from the output terminal Q to the driver 53 (
The data shown in dl is added, and the data shown in (el) is output after a delay time Δt of the driver 53. Therefore, the transmission data is output from the driver 53 after a time of tl+AttlR+Δt2° from the received data.

As mentioned above, the timing from the received frame to the transmitted frame is defined as 2 bits (10.4 .mu.s), and the deviation .DELTA. is allowed to range from -0.4 .mu.s to +0.8 .mu.s. Therefore, 1 bit (5.2 μs) of the 2 bits is given by the frame assembly section 57, and 0.5 bit (2.6 μs) is given by the flip-flop 54 by inverting the clock signal by the inverter 55. The remaining 0.5 bits (2
, 6 μs) and the deviation Δ from the receiver 5I and the driver 53.
This is given by the delay time of the DPLL circuit and the delay time of the DPLL circuit.

[Problem to be solved by the invention]

As mentioned above, in the ISDN interface circuit, the timing from the received frame to the transmitted frame is
bit, and its deviation Δ is -0,4
It is defined as μs to +0.8 μs. Also, the delay time of 1.5 bits is due to the delay of the clock signal, and the delay time of 0.5 bits is due to the delay time between the receiver 51 and the driver 53 and the DP.
This is given by the delay time due to the LL circuit,
Deviation Δ(-0,
4 μs to 100.8 μs).
1 and the driver 53 must be designed. Therefore, while providing a relatively large delay time, the slight deviation Δ
It is not easy to design the receiver 51 and driver 53, which operate at high speed, because the delay time is so small that they cannot be used.

An object of the present invention is to compensate for delay times of receivers and drivers, and to keep deviations in transmission and reception timing within specifications.

[Means to solve the problem]

The ISDN interface circuit of the present invention keeps the timing relationship between the received frame and the transmitted frame within deviation by adjusting the clock phase using a phase shift circuit, and will be explained with reference to FIG. .

The signal received by the receiver 1 is applied to the frame decomposition unit 6 and the clock extraction unit 2, the data is applied from the frame assembly unit 7 to the driver 3 via the flip-flop 8, and the clock signal extracted from the clock extraction unit 2 is applied. In the ISDN interface circuit in the interface reference point S/T that transmits data based on the 3
A selector 5 is provided for selecting the clock signal phase-shifted by the phase shift circuit 4 and applying it to the driver 3 so as to compensate for the delay time of the clock signal.

[Effect]

The phase shift circuit 4 is constituted by a shift register or the like, and shifts the clock signal extracted from the clock extraction section 2 using a high-speed clock signal, and outputs a plurality of clock signals having stepwise phase differences in parallel. The selector 5 selects a clock signal of a desired phase from a plurality of clock signals and uses it as a clock signal for transmission.

Therefore, even if the delay time is shortened by using the high-speed operation receiver 1 and driver 3, the selector 5 selects the clock signal whose phase has been shifted by the phase shift circuit 4, and the desired delay is within the deviation. You can easily get time.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention, in which 11 is a receiver, 12 is a clock extractor, 13 is a driver, and 14 is a block diagram of an embodiment of the present invention.
15 is a phase shift circuit, 15 is a selector, 16 is a frame disassembly section, 17 is a frame assembly section, 18 is a flip-flop, 20 is an inverter, and 21 is a shift register. Also, CLK is 192K extracted by the clock extraction section 12.
The Hz clock signal SCK is, for example, a 16×192=3072 KHz shift clock signal applied to the shift register 21.

The received data is sent to the clock extractor 1 via the receiver 11.
2 and the frame decomposition unit 16, a clock signal CLK is extracted by the clock extraction unit 12, and frame synchronization is achieved by detecting the framing bit F in the frame decomposition unit 16 according to the clock signal CLK,
B1. It is resolved into B2°D channels. Bl to send again
, B2, and D channels are assembled into a frame as shown in FIG. The data is applied to the clock terminal C of the driver 18, and the data is sent from the output terminal Q to the line via the driver 13.

The phase shift circuit 14 is constituted by an inverter 20 and a shift register 21, and the clock signal CLK from the clock extraction section 12 is inverted by the inverter 20 and applied to the shift register 21, and a shift clock signal S is generated.
The output terminals Q1 to Q of each stage are shifted at high speed by CK.
A clock signal whose phase is shifted from n is output. These clock signals are selectively outputted by a selector 15 controlled by a selection signal SL and applied to a clock terminal C of a flip-flop 18, and data is transmitted in synchronization with this clock signal.

FIG. 3 is an explanatory diagram of the operation of the embodiment of the present invention, in which +8) is the clock signal CLK extracted from the clock extraction section 12.
, +b) is the received data added to the receiver 11, F
is the framing bit, L is the DC balance bit, Bl is B
Indicates the data bits of the channel. Also (C) is receiver 1
1 output data, (d) is the clock signal inverted by the inverter 20, (e) is the shift clock signal SCK
, (f) to (1) are output clock signals of each stage of the shift register 21, (j) is data applied to the driver 13, and (k) is output data of the driver 13.

The clock signal CLK shown in (8) extracted by the clock extraction unit 12 is delayed by the delay time Δt PLL due to the DPLL (digital phase locked loop) circuit from the output data of the receiver 11 shown in (0), and
The output data of No. 1 is delayed by the delay time Δt of the receiver 11 from the received data shown in (b). The clock signal shown in (a) is inverted by the inverter 20 to become the clock signal shown in (d), which is shifted by the high-speed shift clock signal SCK shown in (e).

For the output clock signal of each stage of the shift register 21, for example, the output clock signal from the output terminal Q1 is selected by selecting the number of shift stages and the frequency of the shift clock signal,
As shown in (f), when matched with the phase of the output data of the receiver 11 of (C1, the output clock signals of the output terminals Q2, Q3, and Qn are fgl, (h), and (il), respectively, Δt , 2Δt.

The phase difference is nΔt, and for example, the output clock signals shown in (f) to (1) have a leading phase relationship with respect to the clock signal shown in (a). Here, Δt is the time for one phase of the shift clock signal SCK.

When the delay time Δt of the receiver 11 and the delay time Δt of the driver 13 are both zero, if the output clock signal from the output terminal Q1 of the shift register 21 is selectively outputted by the selector 15, the delay time Δt of the receiver 11 and the delay time Δt of the driver 13 are both zero. The timing is 2 bits.

However, in reality, each delay time is not zero, and the delay time may differ from the designed value due to manufacturing errors, etc. Therefore, for example, the delay time Δ1 of the driver 13. and,
When the sum of the delay time Δtll of the receiver 11 is within the range of 2Δ to 10 deviations Δ (−0.4 μs to 10.8 μs), the selector 15 is controlled by the selection signal SL,
When the output clock signal ((h) in FIG. 3) of the output terminal Q3 of the shift register 21 is selectively outputted, the data shown in (J) is added to the driver 13, and the data shown in (J) is added to the driver 13.
The data shown in kl is transmitted after a delay time Δ1D of
1, the time from the timing of the received frame to the timing of the transmitted frame is t2+ΔjDR2Δt, and Δt□−2Δt is the deviation Δ(−0,4μs~+0
．． 8 μs), it is possible to compensate for the delay time ΔLll+Δt between the receiver 11 and the driver 13, and make the timing from the received frame to the transmitted frame a 2-bit time within the range of the deviation Δ. . Therefore,
Sum of delay times ΔtDR between receiver 11 and driver 13
Whether the delay time is small or large, by controlling the selector 15 and selecting the phase-shifted clock signal, it is possible to compensate for the delay time.

In addition, the deviation Δ in that case corresponds to the period of the shift clock signal SCK, and is 16×192K as described above.
When using a shift clock signal of Hz = 3072KHz, Δt = 0.325 μs, so the deviation Δ is -0,
4 μs to +0.8 μs (can be kept within the D standard. In other words, by performing the phase shift in stages with a value that is at least less than the deviation Δ, the receiver 11 and driver 1
It becomes possible to compensate for the delay time with respect to 3 and to keep the compensation result within the deviation Δ. Further, the number of output terminals Ql''-Qn of the shift register 21 can be selected depending on the compensation range of the delay time between the receiver 11 and the driver 13, etc.

〔Effect of the invention〕

As explained above, the present invention includes a phase shift circuit 4 that shifts the phase of the clock signal extracted by the clock extractor 2 in stages using a shift register or the like, and a clock signal whose phase has been shifted by the phase shift circuit 4. A selector 5 for selective output is provided to compensate for the delay time between the receiver 1 and the driver 3, and it is possible to keep the transmission/reception timing within the deviation Δ.
This has the advantage of increasing the degree of freedom in designing the driver 3 and the driver 3.

For example, when using a high-speed receiver and driver, the delay time becomes very short, but the interface circuit must be assembled so that the timing from the receive frame to the transmit frame is 2 bits and within tolerance. Later, the selector 5 may select and set the phase-shifted clock signal.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is an explanatory diagram of the operation of an embodiment of the present invention.
Fig. 4 is an explanatory diagram of the interface reference point, Fig. 5 is an explanatory diagram of the frame configuration, Fig. 6 is a block diagram of the main part of the conventional example, and Fig. 7 is an explanatory diagram of the main part of the conventional example.
The figure is an explanatory diagram of the operation of a conventional example. 1 is the receiver, 2 is the clock extractor, 3 is the driver, 4
5 is a phase shift circuit, 5 is a selector, 6 is a frame disassembly section, 7 is a frame assembly section, and 8 is a flip-flop.

Claims (1)

[Claims] A receiver (1), a clock extraction section (2) that extracts a clock signal from a signal received by the receiver (1), and a transmission based on the clock signal extracted by the clock extraction section (2). In the ISDN interface circuit in the interface reference point S/T having a driver (3) for performing )
and a selector (5) that selects the clock signal phase-shifted by the phase shift circuit (4) and applies it to the driver (3) so as to compensate for the delay time of the receiver (1) and driver (3). An ISDN interface circuit characterized by being provided with.