JPS61236237A - Clock supply system - Google Patents

Abstract

PURPOSE:To supply a synchronizing clock to a subordinate station by applying phase conversion between a clock signal from a host station an output of a highly accurate backup oscillator provided to the subordinate station when all the clock signals from the host station are interrupted. CONSTITUTION:When both synchronizing input clocks 1, 2 from the host station are interrupted, a selector 3 selects an output clock of a backup oscillator 8 with high frequency accuracy automatically. Thus, the phase difference between the input clock 1 or 2 and the clock of the oscillator 8 is absorbed gradually by the phase synchronizing control action for a long time by a phase synchronizing oscillation circuit 4 having a phase comparison circuit 6 and a voltage controlled oscillator 5 as components and the phase fluctuation due to the changeover of the input clock is neglected in the output of the clock supply circuit. Finally, the output is subjected to phase synchronization with the clock of the oscillator circuit 8, and the clock having the frequency accuracy the same as that of the oscillation circuit 8 is obtained as an intra-station clock.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a clock supply method that can supply a synchronized clock signal to a lower station even if all clock signals from an upper station are cut off, and particularly relates to a This invention relates to an internal clock supply system at a lower station that receives a synchronized clock from an upper station in a time-division switch dependent synchronous network.

[Background of the invention]

For example, JP-A-59-125192 discloses a clock supply circuit according to this method, but when a voltage controlled oscillator with low frequency accuracy is used as a component of the clock supply circuit, its own It is undeniable that the running frequency becomes unstable.

That is, as shown in FIG. 2, the selector 3 selects one of the two duplicated synchronization input clocks 1.
The signal is inputted to the phase synchronization generation circuit 4 via the phase synchronization circuit 4. When the input clocks 1 and 2 are all cut off, the voltage controlled oscillator (
The free-running output of the VCO 5 is continuously supplied as a clock to the (lower) station via the buffer circuit 7. However, when using an inexpensive voltage-controlled oscillator with low frequency accuracy when free-running, there will be a difference in clock frequency between the upper and lower stations, and this discrepancy will cause frequent slips in transferred data. This will have a significant negative impact on transmission. For this reason, it has been considered to improve the frequency accuracy of the voltage-controlled oscillator when it is free-running, but in this case, the voltage-controlled oscillator would become extremely expensive, and the clock for lower-level stations would become very expensive. A new problem will arise that is economically unprofitable. Incidentally, reference numeral 6 in FIG. 2 indicates a phase comparator circuit consisting of an exclusive OR gate.

[Purpose of the invention]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a clock supply system that can economically supply synchronizing clocks to lower stations even when all input clocks for synchronization from upper stations are cut off.

[Summary of the invention]

For this purpose, the present invention provides that when all input clocks for synchronization are cut off, when inputting a clock with the same frequency to the voltage controlled oscillator for phase comparison instead of those clocks, the voltage controlled oscillator has high accuracy. This method focuses on the fact that at least a synchronous clock can be obtained.

In other words, if all the synchronization input clocks from the upper station are cut off, the high-precision backup oscillator installed in the lower station sends a clock whose frequency is the same as the synchronization input clock to the voltage controlled oscillator. It is designed to be input for phase comparison.

[Embodiments of the invention]

The present invention will be explained below with reference to FIG. FIG. 1 shows the configuration of an example of a clock supply circuit according to the present invention. As shown in the figure, what is substantially different from that shown in FIG. 2 is that the selector 3 selectively and automatically outputs the clock that is the output of the backup oscillator 8 in certain cases. . Furthermore, an expensive voltage controlled oscillator 5 is no longer required.

Now, to explain the circuit operation, when both the synchronization input clocks 1 and 2 from the upper station are disconnected, the selector 3 outputs the output of the backup oscillator 8 with high frequency accuracy housed in its own circuit. The clock is now automatically selected. Therefore, the input clock 1 (or 2) and the backup oscillator 8
The phase difference between the clock of This allows phase fluctuations due to input clock switching to be ignored. Ultimately, the output of the clock supply circuit is phase-synchronized with the clock of the backup oscillator 8, and a clock with frequency accuracy equivalent to that of the backup oscillator 8 is obtained as the local clock.

By inputting this economically obtainable high-accuracy lock to the voltage controlled oscillator for phase synchronization control in certain cases, a clock whose phase is synchronized with that clock is obtained as a tarock within the station. Therefore, the clock to the station can be provided with better precision than in the past, and moreover, it can be obtained economically.

〔Effect of the invention〕

As explained above, in the case of the present invention, even if all the synchronized clocks connecting the upper station and the lower station in the exchange synchronous network are disconnected, the frequency accuracy is almost the same as that of the upper station, and it is economical. Therefore, there is an effect that the slip in the transfer data between the upper station and the lower station is reduced to a point where it can be almost ignored.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of an example of a clock supply circuit according to the present invention, and FIG. 2 is a diagram showing the configuration of a conventional clock supply circuit. 1.2... Synchronization manual clock 3... Selector 5... Voltage controlled oscillator 6.
...Phase comparator circuit 8...Backup oscillator

Claims (1)

[Claims] The phase of any one of the multiple clock signals with the same frequency from the upper station is compared with the output of a voltage controlled oscillator for phase synchronization, and the phase of the output of the oscillator is controlled based on the phase deviation, thereby providing phase synchronization to the lower station. In a clock supply method that supplies a fixed clock signal, if all the clock signals from the upper station are cut off, the phase must be compared with the output of the high-precision backup oscillator installed in the lower station. A clock supply method characterized by obtaining a clock signal supplied to a lower station by a clock signal.