KR950005943B1 - Interface circuit between b-channel data transceiver and data terminal - Google Patents

Abstract

The circuit interfaces data of B1, B2 channel to asynchronous terminal. The interface circuit converts the serial data of B1, B2 channel to serial data of asynchronous data type and interfaces between B-channel data sender/receiver and asynchronous terminal. The interface circuit consists of an DASL(Digital Adapter for Subscriber Loops)(20), the first and the second serial input/outputs(22) (24), start bit removing blocks(28) (36), a B2-channel data stream converter(32), a B2-channel data converting sender(34) and clock gates(30) (38).

Description

Interface circuit between information channel data transceiver and terminal

1 is a conventional terminal interface circuit diagram

2 is a terminal interface circuit diagram according to the present invention.

3 is a B1 channel transmission waveform diagram of FIG.

4 is a B2 channel transmission waveform diagram of FIG.

5 is a data reception clock waveform diagram of the SIO shown in FIG.

6 and 7 are B1 and B2 channel data transmission waveform diagrams of the first and second SIOs shown in FIG.

The present invention relates to an interface circuit between an information channel data (B-Channel Data) transceiver and a data terminal, and in particular, to directly convert the information channel data into an asynchronous serial data format and to interface with an asynchronous data transmission terminal. It relates to a circuit.

The interface between subscriber and network standardized in ISDN enables various types of service by defined access method. The contents of accessing various items include services such as voice, document data, and images, which are connected to a terminal device that transmits and receives data so that communication is possible. Such ISDN is based on digital communication, and simultaneously provides services having various transmission rates between subscribers and subscribers or between subscribers and systems. To accommodate such various types of services smoothly, various bandwidth channels capable of carrying digital information are required.

The type of channel is divided into two B channels for user information, an information channel and a D channel for signal information according to the transmission of the information. The information channel is divided according to the communication speed and is mainly based on the B channel of 64 Kbps channel speed for telephone service. As described above, the B channel has a transmission rate of 64 Kbps and is used in a communication mode for circuit switching, packet switching, and transmission line for transmitting user information signal. This B channel is called a basic channel, which is a bit rate based on 8-bit PCM encoding of an audio signal.

In case of basic access, B1 and B2 channels have two channels (64Kbps each) and one signal D channel (16Kbps) as one connection structure. In the basic access as described above, two B-channels, B1 and B2 channels, are connected via a serial input / output (SIO) to interface data terminals for asynchronous data transmission and reception.

FIG. 1 is a circuit diagram of a conventional terminal interface, which shows 9600bps of B1 and B2 channels of B1 and B2 Channel Data Transmitter and Receiver (B-CH T / R) 12 or the like. An example of an implementation of a terminal equipment (TE) that is interfaced with an SIO that operates at a baud rate other than that.

In FIG. 1, reference numeral 12 in the drawing denotes B-CH T / R, and 14 denotes an SPC (Serial to parallel converter) 14a and 14c and a PSC (Parallel to Serial conveter) 14b and 14d. A data converter for outputting serial data converted to serial, 16 is an asynchronous terminal for transmitting and receiving asynchronous data, and 18 is a timing control circuit.

When the data of B1 and B2 channels having a transmission rate of 64 Kbps, that is, 128 Kbps serial data are output from the B-CH T / R 12, the SPC 14a in the data converter 14 inputs them. At this time, the SPC 14a converts the data inputted in series at the speed controlled by the timing control circuit 18 in parallel and outputs the same to the PSC 14b. The PSC 14b serially converts the input parallel data under the control of the timing control circuit 18 and outputs the serial data to the asynchronous terminal 16. 128 Kbps outputted from the B-CH T / R 12 by the SPC 14a and PSC 14b respectively converting the serial input into parallel data and the parallel input in series under the control of the timing control circuit 18. (B1 and B2 channel data streams) can be converted into data at a transmission rate of 64 Kbps and output to the asynchronous terminal 16. At this time, the asynchronous terminal 16 adjusts the data of the B1 and B2 channels converted into data of 64 Kbps to a baud rate of 19.2 Kbps, 9.6 Kbps, 4.8 Kbps and the like.

On the contrary, when the data is transmitted from the asynchronous terminal 16 to the B channel of the B-CH T / R 12, the data is converted into the SPC 14c and the PSC 14d to interlace the data. However, there is a problem that the circuit configured as shown in FIG. 1 must have a data converter 14 composed essentially of SPC and PSC. That is, by interfacing the data of the B channel with the data converter 14 having a circuit configuration such as the SPC and the PSC, the circuit is complicated, and power consumption is increased due to an increase in the number of devices for speed conversion. .

Accordingly, an object of the present invention is to provide a circuit capable of interfacing data of B1 and B2 channels, which are basic transmission data of 64 Kbps, with an asynchronous terminal with a simple logic gate configuration.

Another object of the present invention is to provide a circuit capable of interfacing between a B-channel data transceiver and an asynchronous terminal by converting serial data of B2 and B2 into serial data of an asynchronous data type.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is an interface circuit diagram according to the present invention. Its configuration is as follows.

The frame synchronization signal FC and the first and second synchronization signals Fsa and FSb for outputting the B1 and B2 channel data, respectively, are sequentially output in synchronization with the frame synchronization signal FC, and the frame synchronization signal (FS) A digital adapter for subscriber loops (DASL) 20 for receiving synchronized B1 and B2 channel data and a serial data in the form of asynchronous serial data, respectively, and are gated to the first and second transmission control signals. First and second serial input / output devices (hereinafter referred to as “SIO”) 22 and 24 which output asynchronous serial data in synchronization with a clock, and frames output from the DASL 20. A B1 channel data conversion transmitter 26 for inputting a synchronization signal FC, a first synchronization signal FSa, and B1 channel data to generate a first transmission control signal, and inserting and transmitting a start bit to the B1 channel data. And control of the first and second synchronization signals FSa and FSb output from the DASL 20. The start bit removal transmitters 28 and 36 which remove the start bits included in the serial data transmitted from the first and second SIOs 22 and transmit them to the B channel receiving terminal BX of the DASL 20. ), The frame synchronization signal FC output from the DASL 20, and the clock BCLK shift the duration of the B1 channel data to generate a B2 channel data stream enable signal. A B2 channel data stream transmitter 32 for outputting a transmission enable signal including a start bit signal by a first synchronization signal FSa, and B2 output from the DASL 20 in response to the transmission enable signal. A B2 channel data conversion transmitter for generating a second transmission control signal and inserting the start bit into the channel data and transmitting the B2 channel data including the start bit to the second SIO 24 by the second transmission control signal ( 34) with, The inverted clock BCLK of the DASL 20 is transferred to the first SIO 22 and the first in response to the first and second transmission control signals output from the B1 and B2 channel data conversion transmission numbers 26 and 34, respectively. It consists of clock gates 30 and 38 which serve as a transmission clock of the 2SIO 24.

In the configuration of FIG. 1, the B1 channel data conversion transmitter 26 includes an AND gate G2 that gates the B1 channel data by the inverted frame synchronization signal FC output from the DASL 20, and the DASL 20 of the DASL 20. The start bit is transmitted in response to the output of the first transmission control signal for controlling the transmission of the B1 data including the start bit by logically combining the frame synchronization signal FC and the first synchronization signal Fsa, and the AND gate G2. It is composed of a transmission gate (G5) for outputting the B1 channel data gated from the) to the receiving end of the first SIO (22).

The B2 channel data stream transmitter 32 performs a NAND gate G6 for negatively multiplying the frame synchronization signal FC and the clock BCLK output from the DASL 20, and outputs a load signal to the head of the frame; A PSC (36) for shifting the serial data of the B1 channel data to the clock (BCLK) and serially converting the duration data of the B1 channel data in response to the load signal output of the NAND gate (G6), and outputting a B2 channel data stream enable signal; And a NAND gate G7 for outputting a transmission enable signal including a start signal by performing a negative logic multiplication on the B2 channel data stream enable signal output from 36) and the first synchronization signal FSa.

The B2 channel data-changing transmitter 34 inverts the output of the NAND gate G7 and outputs it as a start bit generation control signal and the transmission enable signal output from the NAND gate G7. An AND gate G9 for gating and outputting B2 channel data output from the DASL 20, a start bit output from the inverter G10, and a second synchronization signal FSb output from the DASL 20. A gate G8 for transmitting a second transmission control signal to the clock gate 38 and a B2 output from the AND gate G9 in response to an output of the transmission control signal of the gate G8. It consists of a transmission gate (G11) for outputting the channel data to the receiving end of the second SIO (24).

In the second diagram, the DASL 20 is an example of using the US semiconductor maker TP3401.

3 is a B1 channel data transmission waveform diagram of FIG. 2, FIG. 4 is a B2 channel transmission waveform diagram of FIG. 2, and FIG. 5 is a data reception clock waveform diagram of the SIO shown in FIG. 6 and 7 are B1 and B2 channel transmission waveform diagrams of the first and second SIOs shown in FIG.

Hereinafter, an operation example of FIG. 2 according to the present invention will be described in detail with reference to the accompanying drawings.

From the respective terminals of the DASL 20 of FIG. 2, the first synchronous signal Fsa and the clock BCLK, the B1 channel data and the frame as shown in FIGS. 3A, 2B, 2C, and 2F, respectively. When the synchronizing signal FC is output, the inverter G1 inverts the frame synchronizing signal FC as shown in FIG. 2F as shown in FIG. 2F as shown by (2e), and the inverted frame synchronizing signal / FC (where "/" Output of the inverted output terminal " BAR " is output to the AND gate G2. The AND gate G2 inputs the B1 channel data (FIG. 2C) synchronized with the first synchronization signal FSa to the transfer gate G5, which is a three-state buffer by the signal of FIG. 3F. At this time, the OR gate G3 logically combines the frame synchronization signal FC as shown in FIG. 3F and the first synchronization signal FSA as shown in FIG. 3A as shown in FIG. The transmission control signal G30 is inputted to the control terminal of the transmission gate G5 and the clock gate 30 which is an AND gate.

Accordingly, the first transmission control signal G30 output from the oragate G3 as shown in FIG. 3G is "high" before the signal like FIG. 3C from the AND gate G2 is output. Will output as status. Therefore, the transmission gate G5 receives the initial " low " start bit signal SB (initial output of the AND gate G2) by the first transmission control signal G30 and receives the reception terminal RXD of the first SIO 22. After transmission, the AND gate G2 converts and outputs the B1 channel data gated and output by the first synchronization signal Fsa as shown in FIG. 3D. That is, the B1 channel data is converted into a signal including the start bit SB, such as asynchronous serial data, and transmitted to the receiving terminal RXD of the first SIO 22.

As shown in FIG. 3D, the data receiving clock terminal RXCA of the first SIO 22 receiving the B1 channel data G50 having the start bit SB inserted therein is shown in FIG. 2b>, the output of the inverter G12 which inverts the clock BCLK output from the DASL 20 as shown in FIG. 5B is input. At this time, the first SIO 22 is connected to the third (2d) and (figure 4c) from the transfer gate (G5) at the moment when the clock BCLK output from the inverter (G12) becomes the rising edge. The serial data of the converted B1 channel outputted together is received as valid data.

On the other hand, the first and second synchronization signals Fsa and FAb as shown in Figs. 3a and 3b are outputted from the respective terminals of the DASL 20, and at the same time, as shown in Figs. When the same clock BCLK, B1, B2 channel data, and frame synchronization signal FC as shown in (3e) are outputted, the NAND gate G6 is connected to the frame synchronization signal FC and the fourth diagram in FIG. The clock BCLK of (3c) is negatively multiplied and outputs a load signal G60 as shown in FIG. 3G to the load terminal PC of the PSC 36. Therefore, the NAND gate G6 supplies the load signal G60 to the PSC 36 every 125 sec (output cycle of the frame synchronization signal FC).

At this time, the PSC 36 loads data input to the data terminals A to H by the load signal G60 of FIG. 3G output from the NAND gate G6 into an internal register, and then inputs the data. The loaded data is loaded into an internal register by a clock BCLK, and the loaded data is serially shifted 8 bits by an input clock BCLK to output a data stream enable signal as shown in FIG. The reason why the PSC 36 outputs the data stream enable signal as shown in FIG. 4i by the 8-bit shift of the input clock BCLK to the output terminal QH is B2 output from the DASL 20. This is because the channel data is shifted 8 bits from the frame synchronizing signal FC.

As described above, the B1 channel data conversion transmitter 26 operates to transmit the B1 channel data to the SIO 22 until the PSC 36 completes the 8-bit shift as shown in FIG. Done. When the PSC 36 completes 8-bit shift of the input data and outputs a logic " high " data stream enable signal to the output terminal / QH as shown in FIG. The data stream enable signal is negatively multiplied by the first synchronization signal FSa in FIG. 3A to output a transmission control signal G70 as shown in FIG. 4J. At this time, the inverter G10 inverts the transmission control signal of FIG. 3J as illustrated in FIG. 4K and outputs the start bit generation control signal G100.

The start bit generation control signal G100 output from the inverter G10 is input to the oragate G8. Therefore, the OR gate G8 logically combines the start bit generation control signal G100 and the second synchronization signal FSA output from the DASL 20 as shown in FIG. The same second transmission control signal G80 is supplied to the control terminal of the transmission gate G11.

In the state of operation as described above, the AND gate G9 initially outputs a "low" start bit by the "low" transfer enable signal G70 output from the NAND gate G7 described above. When the enable signal G70 becomes " high ", the B2 channel data output as shown in FIG. 4d (d) from the terminal Br of the DASL 20 is gated. Accordingly, the second transmission gate G11 for inputting the second transmission control signal G80 as the control terminal as shown in FIG. 4L to the control terminal is a B2 channel including the start bit SB as shown in FIG. The data G110 is transmitted to the receiving terminal RXD of the second SIO 24.

As shown in FIG. 4 (d), the data reception clock terminal RXCA of the second SIO 24 receiving the B2 channel data G110 having the start bit SB inserted therein is also shown in FIG. The output G120 of the inverter G12 that inverts the clock BCLK output from the DASL 20 as shown in FIG. At this time, when the clock BCLK output from the inverter G12 becomes a rising edge, the second SIO 24 may move from the transmission gate G11 to the fourth view 3m (FIG. 4c). The serial data G110 of the converted B2 channel, which is output together, is received as valid data. Accordingly, the first and second synchronization signals FSa and FSb having 1/2 cycles of the frame synchronization signal FC, the clock signal BCLK, and the frame synchronization signal FC are alternated from the DASL 20. When the signal is output as a call, the B1 and B2 channel data having the start bits inserted by the operations of the B1 channel data conversion transmitter 26, the B2 channel data stream transmitter 32, and the B2 channel data conversion transmitter 34, respectively, Are output to the second SIOs 22 and 24, respectively.

In the meantime, the first SIO 22 and the second SIO 24 which input the B1 channel data and the B2 channel data transmitted as shown in FIGS. 3 and 4, respectively, transmit serial data to the B1 and B2 channels, respectively. This is input to the receiving terminal BX of the DASL 20 by the following operation. For example, if the aforementioned inverter G12 inverts the clock BCLK outputted from the DASL 20 as shown in FIG. 6 (5b) as shown in FIG. 6 (5c) and outputs it to the AND gate 30, The AND gate 30 sets the inverted clock BCLK as shown in FIG. 6E by the first transmission control signal G30 outputted from the OR gate G3 as shown in FIG. 6D (5d). 1 Outputs to the transmit clock terminal TXCA of the SIO22. At this time, the first SIO 22 outputs a total of 9 bits (start, 8 bits, stop bits) to the transmission terminal as shown in FIG. 6 (g) by the clock signal gated from the AND gate 30.

When serial data such as FIG. 6F is output from the output terminal TXD of the first SIO 24, the serial data of FIG. 6F is input to the transmission gate 28. The control of the transmission gate 28 is controlled by the first synchronous signal FSa (FIG. 5A), which is a frame synchronization signal of the B1 channel of the DASL 20, so that only 8 bits of data of the DASL 20 are controlled. It is supplied to the data receiving terminal BX. Referring to FIG. 7, the data output from the data transmission terminal TXD of the second SIO 24 is transmitted to the B2 channel.

When the inverter G12 inverts the clock BCLK output from the DASL 20 as shown in FIG. 7B and outputs it to the AND gate 38, the AND gate 38 is separated from the OR gate G8. The inverted clock BCLK is outputted to the transmission clock terminal TXCA of the second SIO 24 as shown in FIG. 7E by the second transmission control signal G80 output as shown in FIG. 7C. do. At this time, the second SIO 24 outputs a total of 9 bits (start, 8 bits, stop bits) to the transmission terminal as shown in FIG. 7F by the clock signal gated from the AND gate 38. When serial data as shown in FIG. 7F is output from the output terminal TXD of the second SIO 24, the serial data of FIG. 7F is input to the transfer gate 36. The control of the transmission gate 36 is controlled by the second synchronization signal FSb (FIG. 7A), which is a frame synchronization signal of the B2 channel of the DASL 20, so that only 8-bit data of the DASL 20 is controlled. It is supplied to the data receiving terminal BX.

As described above, the present invention can simply configure an interface between a B-channel data transceiver and a terminal by interfacing B1 and B2 channel data to an asynchronous terminal using only a simple logic gate without using a data conversion element.

Claims (4)

The frame synchronization signal FC and the first and second synchronization signals Fsa and FSb for outputting the B1 and B2 channel data, respectively, are sequentially output in synchronization with the frame synchronization signal FC. (FS) DASL 20 for receiving synchronized B1 and B2 channel data, and first, second SIO 22 for receiving data in asynchronous serial data format and outputting asynchronous serial data in synchronization with a transmission clock, respectively ( 24. An interface circuit between an information channel data transceiver and a terminal, comprising: a frame synchronization signal FC of the synchronization signal output terminal connected between a synchronization signal output terminal of the DASL 20 and a B channel transmission terminal; B1 channel for inputting B1 channel data output from the first synchronization signal FSa and the B channel transmission terminal of the DASL 20 to generate a first transmission control signal and inserting a start bit into the B1 channel data for transmission. Data conversion transmitter 26) connected between the serial data transmission terminals of the first and second SIOs 22 and 24 and the B channel receiving terminal BX of the DASL 20, and are output from the DASL 20. 1, start bit removal transmitters 28, 36 for removing the start bits included in the serial data input by the control of the second synchronization signal FSa or FSb and transmitting them to the B-channel receiving terminal BX. ) Is connected between the synchronization signal output terminal and the clock terminal BCLK of the DASL 20, and is output by a signal output from the frame synchronization signal FC and the clock terminal BCLK of the synchronization signal output terminal. B2 for shifting the duration of B1 channel data to generate a B2 channel data stream enable signal and for outputting a transmission enable signal including a start bit signal by the first synchronization signal FSa from the synchronization signal output terminal. A channel data stream transmitter 32 and the data A second transmission control signal is generated at the same time as the start bit is inserted into the B2 channel data output from the DASL 20 in response to the transmission enable signal outputted from the output terminal of the stream transmission unit 32, B2 channel data conversion transmission unit 34 for transmitting the B2 channel data including the start bit to the second SIO 24 by the second transmission control signal, and is output from the clock terminal BCLK of the DASL 20. The inverted clock of the clock is input to each one terminal, and is input to the one terminal in response to the input of the first and second transmission control signals output from the B1 and B2 channel data conversion transmitters 26 and 34, respectively. And the clock gates (30) and (38) for providing the inverted clocks to be the transmission clocks of the first SIO (22) and the second SIO (24). The B1 channel data conversion transmitter 26 gates the B1 channel data of the DASL 20 by an inverted frame synchronization signal FC of the synchronization signal output terminal of the DASL 20. A gate G2 and a synchronization signal output terminal of the DASL 20 for logically combining the frame synchronization signal FC and the first synchronization signal Fsa to control transmission of B1 channel data including a start bit; A start bit is transmitted in response to the output of one transmission control signal, and the B1 channel data gated from the AND gate G2 is configured as a transmission gate G5 output to the receiving end of the first SIO 22. Interface circuit between information channel data transceiver and terminal. 3. The B2 channel data stream transmission unit 32 according to claim 2, wherein the B2 channel data stream transmission unit 32 negatively multiplies the frame synchronization signal FC and the clock BCLK output from the DASL 20, and outputs a load signal at the head position of the frame. In response to a signal output, the NAND gate G6 and the load signal of the NAND gate G6 are shifted in series by shifting the duration data of the B1 channel data by a clock from the clock terminal BCLK to perform a B2 channel data frame. A PSC 36 outputting an enable signal, a B2 channel data stream enable signal output from the PSC 36 and a first synchronous signal FSa are negatively multiplied to output a transmit enable signal including a start signal. An interface circuit between an information channel data transceiver and a terminal, comprising: a NAND gate (G7). 4. The inverter G10 according to claim 2 or 3, wherein the B2 channel data conversion transmitter 24 inverts the output of the NAND gate G7 and outputs it as a start bit generation control signal. An AND gate G9 for gating and outputting B2 channel data output from the DASL 20 by an enable signal output from G7, a start bit output from the inverter G10, and an output from the DASL 20. A gate G8 for transmitting the second synchronization signal FSb to the second gate control signal to the clock gate 38 and a start bit in response to the transmission control signal output of the gate G8. And a transmission gate (G11) for outputting the B2 channel data output from the AND gate (G9) to a receiving end of the second SIO (24).