KR19990060650A - Data transmission timing adjusting circuit between the digital transmission device and the central processing unit for its control - Google Patents

Abstract

end. The technical field to which the invention described in the claims belongs

A data transmission timing adjusting circuit between a digital transmission device and a central processing unit for control thereof.

I. The technical problem to be solved by the invention

Even when the data transmission timing of the digital transmission device is different, accurate data transmission can be performed without changing hardware or software.

All. Summary of Solution of the Invention

By providing different communication clocks of the digital transmission device and the central processing unit, even when the data transmission timing of the digital transmission device is different, the correct data is always delivered to the central processing unit without changing the same hardware or software.

la. Important uses of the invention

It is used when the data transmission timing of the digital transmission device controlled by the central processing unit is different from each other.

Description

Data transmission timing adjusting circuit between the digital transmission device and the central processing unit for control thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital transmission device and a central processing unit (hereinafter referred to as a CPU) for control thereof, and more particularly, to a data transmission timing adjusting circuit between a digital transmission device and a CPU.

Typically, digital transmission devices, such as the Digital Adapter for Subscribe Loop (DASL), are controlled by the CPU. Accordingly, data is transmitted and received between the digital transmission device and the CPU. Examples of such digital transmission devices include DASL TP3404 and TP3407, which are ICs (Integrated Circuit) chips manufactured and sold by National Semiconductor Corporation (hereinafter referred to as NS Corporation).

The above-mentioned DASL and CPU, which are NS's digital transmission devices, are connected to each other as shown in FIG. In FIG. 1, the DASL 100 includes a data input terminal CI, a data output terminal CO, a clock input terminal CCLK, a data valid signal input terminal CS, and an exception processing signal output terminal INT, and the CPU 102 transmits the data transmission terminal TX. And the data receiving terminal RX, the clock input terminal CLK, the data valid signal output terminal ENABLE, and the exception handling signal input terminal IRQ. The data input terminal CI and the data transmission terminal TX, the data output terminal CO and the data receiving terminal RX, the data valid signal input terminal CS and the data valid signal output terminal ENABLE, and the exception processing signal output terminal between the DASL 100 and the CPU 102. The INT and exception processing signal input terminals IRQ are connected to each other, and each of the clock input terminals CCLK and CLK inputs a clock CLOCK, which is a timing signal for data transmission between the DASL 100 and the CPU 102, from the outside.

In the DASL 100, the data input terminal CI is a terminal for inputting data transmitted from the CPU 102, the data output terminal CO is a terminal for transmitting data to the CPU 102, and the clock input terminal CCLK. Is a terminal for inputting a clock clock, the data valid signal input terminal CS is a terminal for inputting a data valid signal from the CPU 102, and the exception processing signal output terminal INT is an exception processing for transmission to the CPU 102. This is a terminal to output a signal. The data transmission terminal TX in the CPU 102 is a terminal for transmitting data to the DASL 100, the data receiving terminal RX is a terminal for receiving data transmitted from the DASL 100, and the clock input terminal CLK is This is a terminal for inputting clock clock, and the data valid signal output terminal ENABLE is a terminal for transmitting a data valid signal to the DASL 100, and the exception signal input terminal INT is a terminal for inputting an exception processing signal from the DASL 100. to be.

Basically, data is transferred between the DASL 100 and the CPU 102 at the timing shown in FIG. 2. In the DASL 100, all data transmission is performed by shifting data through the data input terminal CI and simultaneously outputting data through the data output terminal CO. For data transmission with the DASL 100, the data valid signal input terminal CS must be low for 8 clock clocks. At this time, the output data is at the falling edge of the clock CLOCK input to the clock input terminal CCLK, and the data input to the DASL 100 is at the rising edge of the clock CLOCK input to the clock input terminal CCLK. Shift is input. In order to output data from the DASL 100, 8-bit data must be input to the data input terminal CI as shown in FIG. If there is exception processing in the DASL 100, the output of the exception processing signal output terminal INT goes low.

However, according to the advancement of the NS DASL technology, the actual timing is different as shown in FIGS. 3 and 4. Figure 3 shows the data input and output timing diagram of the old DASL of NS Corporation. In the state where the data valid signal input terminal CS is low, data is input from the time ta1 to the data input terminal CI, and the clock of the clock input terminal CCLK is therefrom. It can be seen that data is output to the data output terminal CO at ta2 after 1 1/2 cycles of the clock. Figure 4 shows the data input and output timing diagram of the new version DASL of NS, the data is input from the time tb1 into the data input terminal CI when the data valid signal input terminal CS is low, the clock of the clock input terminal CCLK therefrom. It can be seen that data is output to the data output terminal CO at tb2 after 1/2 cycle of the clock. 3 and 4, Tw represents an 8-bit data recognition range of the CPU 102.

3 and 4, when the data output from the data output terminal CO of the DASL 100 compares ta2 and tb2 between the old version and the new version, a difference occurs by one clock. By one clock difference, the transmission data value of the DASL 100 and the reception data value of the CPU 102 are different from each other. When the DASL 100 is an old version, the CPU 102 receives 9 bits and ignores the first 1 bit and then treats only 8 bits as data. In contrast, when the DASL 100 is a new version, the CPU 102 receives 8 bits and treats it as data.

As such, since the data transmission timing is different depending on the version, when the DASL 100 is implemented with the same hardware, accurate data is not transmitted to the CPU 100. Accordingly, hardware or software had to be changed according to whether the DASL 100 was new or old.

If the data transmission timing of the digital transmission device controlled by the CPU, such as the NS DASL of NS, is different from each other, if the same hardware is implemented, the correct data is not transferred to the CPU.

Accordingly, an object of the present invention is to provide a transmission timing adjusting circuit capable of accurate data transmission without changing hardware or software even when data transmission timings of digital transmission devices are different.

1 is a configuration diagram of a connection between a conventional digital transmission device and a central processing unit;

2 is a timing diagram of data transmission between the DASL and the CPU of FIG.

3 is a data input and output timing diagram of the old version DASL,

4 is a timing diagram of data input and output of the new version DASL;

5 is a data transmission timing adjusting circuit diagram according to an embodiment of the present invention;

6 is a data input and output timing diagram of the DASL of FIG. 5;

7 is a data input and output timing diagram of the central processing unit of FIG. 5.

The present invention for achieving the above object is characterized by providing different communication clocks of the digital transmission device and the central processing unit. This ensures that the correct data is always delivered to the central processing unit without changing the same hardware or software even if the data transmission timings of the digital transmission devices are different.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description and the annexed drawings, numerous specific details are set forth in order to provide a more thorough understanding of the present invention, such as specific circuit configurations or operation timings. It will be apparent to those skilled in the art that the present invention may be practiced without these specific details. And a detailed description of known functions and configurations that may unnecessarily obscure the subject matter of the present invention will be omitted.

5 is a diagram illustrating a data transmission timing adjusting circuit according to an exemplary embodiment of the present invention, wherein the DASL 100 and the CPU 102 are the same as those of FIG. 1 described above, and a new inverter 104 is added. . That is, the data input terminal CI and the data transmission terminal TX, the data output terminal CO and the data receiving terminal RX, the data valid signal input terminal CS and the data valid signal output terminal ENABLE, and the exception processing signal output between the DASL 100 and the CPU 102. The connection between the terminal INT and the exception handling signal input terminal IRQ is the same as in FIG. However, the clock CLOCK is directly input to the clock input terminal CCLK of the DASL 100, while the clock CLOCK is inverted and input to the clock input terminal CLK of the CPU 102 by the inverter 104.

The data transfer timing of the DASL 100 is as shown in FIG. 6, and the data transfer timing of the CPU 102 is as shown in FIG. 7. As shown in FIGS. 6 and 7, both the DASL 100 and the CPU 102 execute data input on the rising edge of the clock clock and output on the falling edge. In FIG. 6, when the data valid signal input terminal CS is low, data is inputted from the time point tc1 to the data input terminal CI, and from thereafter, data is input to the data output terminal CO at the time point tc2, which is 1/2 of the clock clock of the clock input terminal CCLK. You can see that the data is output. In FIG. 7, data is output from the time point td1 to the data transmission terminal CI with the data valid signal output terminal ENALBE low, and data is input to the data receiving terminal td2 after one cycle of the clock clock of the clock input terminal CCLK. Able to know. 6 and 7, it can be seen that only a 1/2 cycle difference remains between the time tc2 and the time td2.

As such, by providing the communication clocks of the DASL 100 and the CPU 102 differently, the difference of one clock is changed to the difference of one half of the clock. That is, the effect that the communication clock supplied to the CPU 102 through the inverter 104 is delayed by 1/2 cycle with the communication clock supplied to the DASL 100 is generated.

Therefore, even when data transmission timings of a digital transmission device controlled by a CPU, such as DASL of NS, are different from each other, accurate data is always delivered to the CPU 102 without changing the same hardware or software.

Meanwhile, in the above description of the present invention, specific embodiments have been described, but various modifications can be made without departing from the scope of the present invention. In particular, in the embodiment of the present invention has been applied to the case of transferring data between the NS DASL and the CPU of the NS company, in the case that the transmission timing is changed in this way, all of the same may be applied. Therefore, the scope of the invention should not be defined by the described embodiments, but should be defined by the equivalent of claims and claims.

As described above, the present invention provides the communication clocks of the digital transmission device and the CPU differently so that even when the data transmission timing of the digital transmission device is different, the correct data is always delivered to the CPU without changing the same hardware or software. There is an advantage to this.

Claims (2)

A circuit for adjusting data transmission timing between a digital transmission device and a central processing unit for control thereof, A digital transmission device for transmitting and receiving data at a timing synchronized with a clock input to a clock input terminal; A central processing unit which transmits and receives data with the digital transmission device at a timing synchronized with a clock input to a clock input terminal; And an inverter for inverting a clock applied to a clock input terminal of the digital transmission device and applying the same to a clock input terminal of the central processing unit. The data transmission timing adjusting circuit according to claim 1, wherein said digital transmission device is DASL.