KR940005004A - Interface circuit between transmission channel data transceiver and terminal - Google Patents

Interface circuit between transmission channel data transceiver and terminal Download PDF

Info

Publication number
KR940005004A
KR940005004A KR1019920015397A KR920015397A KR940005004A KR 940005004 A KR940005004 A KR 940005004A KR 1019920015397 A KR1019920015397 A KR 1019920015397A KR 920015397 A KR920015397 A KR 920015397A KR 940005004 A KR940005004 A KR 940005004A
Authority
KR
South Korea
Prior art keywords
channel data
signal
output
dasl
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
KR1019920015397A
Other languages
Korean (ko)
Other versions
KR950005943B1 (en
Inventor
안재선
Original Assignee
정용문
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 정용문, 삼성전자 주식회사 filed Critical 정용문
Priority to KR1019920015397A priority Critical patent/KR950005943B1/en
Publication of KR940005004A publication Critical patent/KR940005004A/en
Application granted granted Critical
Publication of KR950005943B1 publication Critical patent/KR950005943B1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Communication Control (AREA)

Abstract

B채널 데이터를 비동기 직렬 데이터 형태로 직접 변환하여 비동기 데이터 송수터미널과 인터페싱하는 회로에 관한 것이다.The present invention relates to a circuit for directly converting B-channel data into an asynchronous serial data format and interfacing with an asynchronous data transmission terminal.

상기의 인터페이싱회로는 B1,B2채널의 데이터를 송수신하는 송수신기로부터 출력되는 B1,B2채널의 데이터 스트림을 분리하고, 상기 분리된 데이터 스트림 각각에 스타트 비트를 삽입함과 동시에 상기 스타트 비트가 삽입된 B1,B2채널의 데이터를 B1,B2채널의 동기하여 분리된 직력 데이터 입출력장치로 각각 전송한다.The interfacing circuit separates the data streams of the B1 and B2 channels output from the transceiver for transmitting and receiving the data of the B1 and B2 channels, and inserts the start bits into each of the separated data streams and simultaneously inserts the start bits into the B1. The data of the B2 channel is transferred to the serial data input / output device in synchronization with the B1 and B2 channels, respectively.

그리고, 상기 직렬 데이터 입출력장치로 부터 각각 출력되는 직렬 데이터를상기B1,B2채널의 동기신호에 동기하여 상기 송수신기로 전송도록 동작된다.The serial data output from the serial data input / output device is transmitted to the transceiver in synchronization with the synchronization signals of the B1 and B2 channels.

상기와 같은 구성으로 B1,B2채널의 데이터를 직렬 데이터를 입출력하는 터미널에 인터페싱함으로써 인터페이스회로를 간단히 구성할 수 있다.With the above configuration, the interface circuit can be easily configured by interfacing the data of the B1 and B2 channels to a terminal for inputting and outputting serial data.

Description

전송채널 데이터 송수신기와 터미널간의 인터페이스 회로Interface circuit between transmission channel data transceiver and terminal

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 터미널 인터페이스 회로도,2 is a terminal interface circuit diagram according to the present invention;

제3도는 제2도의 B1채널 송신 파형도,3 is a B1 channel transmission waveform diagram of FIG.

제4도는 제2도의 B2채널 송신 파형도,4 is a B2 channel transmission waveform diagram of FIG.

제5도는 제2도에 도시된 SIO의 데이터 수신 클럭 파형도.5 is a data reception clock waveform diagram of the SIO shown in FIG.

Claims (4)

프레임 동기신호(FC)와, Bl,B2채널 데이터를 각각 출력하기 위한 제1,제2동기신호(FSa) (FSb)를 상기 프레임 동기신호(FC)에 동기하여 순차 출력하고, 상기 프레임 동기신호(FS)동기된 Bl, B2채널 데이터를 수신하는 DASL(20)과 비동기 직렬 데이터 형태의 직렬 데이터를 각각 수신하고, 송신클럭에 동기하여 비동기 직렬 데이터를 출력하는 제1, 제2 SIO (22) (24)을 구비한 정보 채널데이터 송수신기와 터미널간의 인터페이스 회로에 있어서, 상기 DASL(20)로 부터 출력되는 프레임 동기 신호(FC)와 제1동기신호(FSa)와 B1채널 데이터를 입력하여 제 1송신제어신호를 발생함과 동시에 상기 B1채널 데이터에 스타트 비트를 삽입하여 전송하는 Bl채널데이 터 변환송신부(26)와, 상기 DASL(20)로 부터 출력되는 제1, 제2동기 신호(FSa) (FSb)의 제어에 의해 상기 제1, 제2 SIO(22)로 부터 각각 송신되는 직렬데이터에 포함된 스타트 비트를 제거하여 상기DASL (20)의 B2채널 수신단자(BX)로 전송하는 스타트 비트 제거 전송기(28) (36)와, 상기 DASL(20)로 부터 출력되는 프레임 동기신호(Fc)와, 클럭(Bclk)에 의해 Bl채널 데이터의 듀레이션을 시프트하여 B2채널 데이터의 듀레이션을 시프트하여 B2채널 데이터 스트림 인에이블 신호를 발생함과 동시에 상기 제1동기 신호(FSa)에 의해 스타트 비트 신호가 포함되는 전송 인에이블 신호를 출력하는 B2채널 데이터 스트림 전송부(32)와, 상기 전송인에이블 신호에 응답하여 상기 DASL(20)로 부터 출력되는 32채널 데이터에 스타트 비트를 삽입함과 동시에 제2송신 제어 신호를 발생하고, 상기 스타트 비트가 포함된 B2채널 데이터를 상기 제2송신 제어 신호에 의해 제2SIO(24)로 전송하는 B2채널 데이터 변환 송신부(34)와, 상기 B1, B2채널 데이터 변환 송신부(26) (34)로 부터 각 출력되는 제1,제2송신 제어 신호에 응답하여 상기 DASL(20)의 반전클럭(BCLK)를 상기 제1SIO(22)와 제2SIO(24)의 송신클럭으로 제공하는 클럭 게이트(30) (38)로 구성함을 특징으로 하는 회로.The frame synchronization signal FC and the first and second synchronization signals Fsa and FSb for outputting the Bl and B2 channel data, respectively, are sequentially output in synchronization with the frame synchronization signal FC, and the frame synchronization signal (FS) First and second SIOs 22 receiving DASL 20 for receiving synchronized Bl and B2 channel data and serial data in the form of asynchronous serial data, respectively, and outputting asynchronous serial data in synchronization with the transmission clock. An interface circuit between an information channel data transceiver having a terminal (24) and a terminal, comprising: a frame synchronization signal (FC) outputted from the DASL 20, a first synchronization signal (FSa), and a B1 channel data input thereto; A Bl channel data conversion transmitter 26 for generating a transmission control signal and inserting and transmitting a start bit into the B1 channel data and the first and second synchronization signals FSa output from the DASL 20. From the first and second SIO 22, respectively, under the control of (FSb) Start bit removal transmitters 28 and 36 for removing start bits included in serial data to be transmitted to the B2 channel receiving terminal BX of the DASL 20, and frames outputted from the DASL 20. The duration of the Bl channel data is shifted by the synchronization signal Fc and the clock Bclk to shift the duration of the B2 channel data to generate a B2 channel data stream enable signal and simultaneously to the first sync signal Fsa. Inserts a start bit into a B2 channel data stream transmitter 32 for outputting a transmit enable signal including a start bit signal and 32 channel data output from the DASL 20 in response to the transmit enable signal. And a B2 channel data conversion transmitter 34 for generating a second transmission control signal and transmitting B2 channel data including the start bit to the second SIO 24 by the second transmission control signal. In response to the first and second transmission control signals output from the B1 and B2 channel data conversion transmitters 26 and 34, the inverted clock BCLK of the DASL 20 is transferred to the first SIO 22 and the second SIO. And a clock gate (30) provided for the transmission clock of (24). 제1항에 있어서. 상기 Bl채널 데이터 변환송신부(26)는 DASL(20)로 부터 출력되는 반전 프레임 동기신호(FC)에 의해 Bl채널 데이터를 게이트하는 앤드게이트(G2)와, 상기 DASL(20)의 프레임 동기신호(FC)와 제1동기신호(FSa)틀 논리합하여 스타트 비트를 포함하는 Bl데이터의 전송을 제어하는 제1송신 제어신호의 출력에 응답하여 스타트 비트를 전송하고, 상기 앤드게이트(G2)로 부터 게이팅되는 Bl채널 데이터를 제1SIO(22)의 수신 단으로 출력하는 전송게이트(G5)로 구성함을 특징으로 하는 회로.The method of claim 1. The Bl channel data converting and transmitting unit 26 includes an AND gate G2 that gates the Bl channel data by an inverted frame synchronizing signal FC output from the DASL 20, and a frame synchronizing signal of the DASL 20. The start bit is transmitted in response to the output of the first transmission control signal for controlling the transmission of the Bl data including the start bit by OR of the first synchronization signal (FSa) and the first synchronization signal (FSa), and gating from the AND gate G2. And a transmission gate (G5) for outputting the B1 channel data to the receiving end of the first SIO (22). 제2항에 있어서, 상기 B2채널데이터 스트림 전송부(32)는 상기 DASL(20)로 부터 출력되는 프레임 동기신호(FC)와 클럭 (BCLK)를 부논리곱하여 프레임의 선두위치에 로드신호를 출력하는 낸드게이트(G6)와, 상기 낸드게이트(G6)와 로드신호 출력 에 응답하여 B1채널 데이터의 듀레이션 데이터를 상기 클럭(BCLK)로 시프트하여 직렬 변환하여 B2채널 데이터 스트림 인에이블 신호를 출력하는 PSC(36) 상기 PSC(36)를부논리곱하여 스타트 신호가 포함되는 전송 인에이블 신호를 출력하는 낸드게이트(G7)로 구성함을 특징으로 하는 회로.3. The B2 channel data stream transmitter 32 outputs a load signal to a head position of a frame by negatively multiplying a frame synchronization signal FC and a clock BCLK output from the DASL 20. PSC for outputting the B2 channel data stream enable signal by shifting the serial data of the B1 channel data to the clock BCLK in series in response to the NAND gate G6 and the NAND gate G6 and the load signal output. (36) A circuit comprising: a NAND gate (G7) for outputting a transmit enable signal including a start signal by performing a negative logic on the PSC (36). 제2항 또는 제3항에 있어서, B2채널데이터 변환 송신부(34)는 상기 낸드게이트(G7)의 출력을 반전하여 스타트 비트 발생제어 신호로 출력하는 인버터(G10)와, 상기 낸드게이트 (G7)로 부터 출력되는 전송 인에이블 신호에 의해 상기 DASL(20)로 부터 출력되는 B2채널 데이터를 게이팅 출력하는 앤드게이트(G9)와, 상기 인버터 (G10)으로 부터 출력되는 스타트 비트와 상기 DASL (20)로 부터 출력되는 제2동기 신호 (FSb)를 논리합하여 제2 송신 재어신호를 상기 클럭게이트(38)로 전송하는 게이트(G8)와, 상기 게이트(G8)의 전송제어신호 출력에 응답하여 스타트 비트를 출력하고 상기 앤드게이트 (G7)로 부터 출력되는 B2채널 데이터를 상기 제2SIO (24)의 수신단으로 출력하는 전송게이트(G11)로 구성함을 특징으로 하는 회로.The inverter G10 according to claim 2 or 3, wherein the B2 channel data conversion transmitter 34 inverts the output of the NAND gate G7 and outputs it as a start bit generation control signal, and the NAND gate G7. An AND gate G9 for gating and outputting the B2 channel data output from the DASL 20 by a transmission enable signal output from the DASL, a start bit output from the inverter G10, and the DASL 20. A gate G8 for logically combining the second synchronization signal FSb output from the gate and transmitting the second transmission control signal to the clock gate 38, and a start bit in response to the transmission control signal output of the gate G8. And a transmission gate (G11) for outputting the B2 channel data output from the AND gate (G7) to a receiving end of the second SIO (24). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920015397A 1992-08-26 1992-08-26 Interface circuit between information channel data transceiver and terminal Expired - Fee Related KR950005943B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920015397A KR950005943B1 (en) 1992-08-26 1992-08-26 Interface circuit between information channel data transceiver and terminal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920015397A KR950005943B1 (en) 1992-08-26 1992-08-26 Interface circuit between information channel data transceiver and terminal

Publications (2)

Publication Number Publication Date
KR940005004A true KR940005004A (en) 1994-03-16
KR950005943B1 KR950005943B1 (en) 1995-06-07

Family

ID=19338530

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920015397A Expired - Fee Related KR950005943B1 (en) 1992-08-26 1992-08-26 Interface circuit between information channel data transceiver and terminal

Country Status (1)

Country Link
KR (1) KR950005943B1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990060650A (en) * 1997-12-31 1999-07-26 윤종용 Data transmission timing adjusting circuit between the digital transmission device and the central processing unit for its control
KR100249618B1 (en) * 1996-12-30 2000-04-01 전주범 Apparatus for inserting gfc bit in atm cell
KR100346632B1 (en) * 1999-03-15 2002-07-26 가부시키가이샤 아드반테스트 Delay device, semiconductor testing device, semiconductor device, and oscilloscope

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100249618B1 (en) * 1996-12-30 2000-04-01 전주범 Apparatus for inserting gfc bit in atm cell
KR19990060650A (en) * 1997-12-31 1999-07-26 윤종용 Data transmission timing adjusting circuit between the digital transmission device and the central processing unit for its control
KR100346632B1 (en) * 1999-03-15 2002-07-26 가부시키가이샤 아드반테스트 Delay device, semiconductor testing device, semiconductor device, and oscilloscope
US6769082B1 (en) 1999-03-15 2004-07-27 Advantest Corporation Delay device, semiconductor testing device, semiconductor device, and oscilloscope

Also Published As

Publication number Publication date
KR950005943B1 (en) 1995-06-07

Similar Documents

Publication Publication Date Title
JPH01106680A (en) Adaptive adjustment of running time of video signal and audio signal to reference signal
KR940005004A (en) Interface circuit between transmission channel data transceiver and terminal
US6128319A (en) Hybrid interface for packet data switching
KR930007133B1 (en) Waiting time gitter dropping circuit of synchronous muliple apparatus
KR100242304B1 (en) Data transmitting method and apparatus for isdn system
KR0121762B1 (en) First-in, first-out memory device for digital data rate matching
JPH0461528A (en) Time division multiplexer/demultiplexer
JPH05218996A (en) Multiplexer
KR20000039227A (en) Apparatus for varying transmission speed of communication signal
KR200314153Y1 (en) Data parallel transmission device of ATM system
JPS6360636A (en) Synchronizing multiplex system
KR100562117B1 (en) Synchronizer for communication between asynchronous transmission unit and synchronous data processing unit
KR20020052628A (en) Apparatus of Converting Data Transfer Speed in the Electronic Switching System
JP2671778B2 (en) Synchronous multiplexer
JPS63111743A (en) Data line terminator
JP2917297B2 (en) Multi-frame synchronization circuit
JPS61206339A (en) Interface speed converting system
JPH052027B2 (en)
JPH0696017A (en) In-device wiring method
KR20030042970A (en) Channel convert chip
JPH0756962B2 (en) Data communication system
JPH02306734A (en) Multiplexer
JPS63169845A (en) External timing system
JPH10327119A (en) Modem
JPS6360637A (en) Demultiplexing method

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19920826

PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 19920826

Comment text: Request for Examination of Application

PG1501 Laying open of application
E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 19950323

Patent event code: PE09021S01D

G160 Decision to publish patent application
PG1605 Publication of application before grant of patent

Comment text: Decision on Publication of Application

Patent event code: PG16051S01I

Patent event date: 19950509

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

Patent event code: PE07011S01D

Comment text: Decision to Grant Registration

Patent event date: 19950904

GRNT Written decision to grant
PR0701 Registration of establishment

Comment text: Registration of Establishment

Patent event date: 19951016

Patent event code: PR07011E01D

PR1002 Payment of registration fee

Payment date: 19951016

End annual number: 3

Start annual number: 1

PR1001 Payment of annual fee

Payment date: 19980601

Start annual number: 4

End annual number: 4

PR1001 Payment of annual fee

Payment date: 19990526

Start annual number: 5

End annual number: 5

PR1001 Payment of annual fee

Payment date: 20000525

Start annual number: 6

End annual number: 6

PR1001 Payment of annual fee

Payment date: 20010525

Start annual number: 7

End annual number: 7

PR1001 Payment of annual fee

Payment date: 20020527

Start annual number: 8

End annual number: 8

PR1001 Payment of annual fee

Payment date: 20030523

Start annual number: 9

End annual number: 9

PR1001 Payment of annual fee

Payment date: 20040521

Start annual number: 10

End annual number: 10

PR1001 Payment of annual fee

Payment date: 20050524

Start annual number: 11

End annual number: 11

PR1001 Payment of annual fee

Payment date: 20060519

Start annual number: 12

End annual number: 12

FPAY Annual fee payment

Payment date: 20070509

Year of fee payment: 13

PR1001 Payment of annual fee

Payment date: 20070509

Start annual number: 13

End annual number: 13

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee