KR940005004A - Interface circuit between transmission channel data transceiver and terminal - Google Patents

Abstract

The present invention relates to a circuit for directly converting B-channel data into an asynchronous serial data format and interfacing with an asynchronous data transmission terminal.

The interfacing circuit separates the data streams of the B1 and B2 channels output from the transceiver for transmitting and receiving the data of the B1 and B2 channels, and inserts the start bits into each of the separated data streams and simultaneously inserts the start bits into the B1. The data of the B2 channel is transferred to the serial data input / output device in synchronization with the B1 and B2 channels, respectively.

The serial data output from the serial data input / output device is transmitted to the transceiver in synchronization with the synchronization signals of the B1 and B2 channels.

With the above configuration, the interface circuit can be easily configured by interfacing the data of the B1 and B2 channels to a terminal for inputting and outputting serial data.

Description

Interface circuit between transmission channel data transceiver and terminal

Since this is an open matter, no full text was included.

2 is a terminal interface circuit diagram according to the present invention;

3 is a B1 channel transmission waveform diagram of FIG.

4 is a B2 channel transmission waveform diagram of FIG.

5 is a data reception clock waveform diagram of the SIO shown in FIG.

Claims (4)

The frame synchronization signal FC and the first and second synchronization signals Fsa and FSb for outputting the Bl and B2 channel data, respectively, are sequentially output in synchronization with the frame synchronization signal FC, and the frame synchronization signal (FS) First and second SIOs 22 receiving DASL 20 for receiving synchronized Bl and B2 channel data and serial data in the form of asynchronous serial data, respectively, and outputting asynchronous serial data in synchronization with the transmission clock. An interface circuit between an information channel data transceiver having a terminal (24) and a terminal, comprising: a frame synchronization signal (FC) outputted from the DASL 20, a first synchronization signal (FSa), and a B1 channel data input thereto; A Bl channel data conversion transmitter 26 for generating a transmission control signal and inserting and transmitting a start bit into the B1 channel data and the first and second synchronization signals FSa output from the DASL 20. From the first and second SIO 22, respectively, under the control of (FSb) Start bit removal transmitters 28 and 36 for removing start bits included in serial data to be transmitted to the B2 channel receiving terminal BX of the DASL 20, and frames outputted from the DASL 20. The duration of the Bl channel data is shifted by the synchronization signal Fc and the clock Bclk to shift the duration of the B2 channel data to generate a B2 channel data stream enable signal and simultaneously to the first sync signal Fsa. Inserts a start bit into a B2 channel data stream transmitter 32 for outputting a transmit enable signal including a start bit signal and 32 channel data output from the DASL 20 in response to the transmit enable signal. And a B2 channel data conversion transmitter 34 for generating a second transmission control signal and transmitting B2 channel data including the start bit to the second SIO 24 by the second transmission control signal. In response to the first and second transmission control signals output from the B1 and B2 channel data conversion transmitters 26 and 34, the inverted clock BCLK of the DASL 20 is transferred to the first SIO 22 and the second SIO. And a clock gate (30) provided for the transmission clock of (24). The method of claim 1. The Bl channel data converting and transmitting unit 26 includes an AND gate G2 that gates the Bl channel data by an inverted frame synchronizing signal FC output from the DASL 20, and a frame synchronizing signal of the DASL 20. The start bit is transmitted in response to the output of the first transmission control signal for controlling the transmission of the Bl data including the start bit by OR of the first synchronization signal (FSa) and the first synchronization signal (FSa), and gating from the AND gate G2. And a transmission gate (G5) for outputting the B1 channel data to the receiving end of the first SIO (22). 3. The B2 channel data stream transmitter 32 outputs a load signal to a head position of a frame by negatively multiplying a frame synchronization signal FC and a clock BCLK output from the DASL 20. PSC for outputting the B2 channel data stream enable signal by shifting the serial data of the B1 channel data to the clock BCLK in series in response to the NAND gate G6 and the NAND gate G6 and the load signal output. (36) A circuit comprising: a NAND gate (G7) for outputting a transmit enable signal including a start signal by performing a negative logic on the PSC (36). The inverter G10 according to claim 2 or 3, wherein the B2 channel data conversion transmitter 34 inverts the output of the NAND gate G7 and outputs it as a start bit generation control signal, and the NAND gate G7. An AND gate G9 for gating and outputting the B2 channel data output from the DASL 20 by a transmission enable signal output from the DASL, a start bit output from the inverter G10, and the DASL 20. A gate G8 for logically combining the second synchronization signal FSb output from the gate and transmitting the second transmission control signal to the clock gate 38, and a start bit in response to the transmission control signal output of the gate G8. And a transmission gate (G11) for outputting the B2 channel data output from the AND gate (G7) to a receiving end of the second SIO (24). ※ Note: The disclosure is based on the initial application.