JPH09181750A - Data processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the transmission delay even in the case of sending data via a serial transmission path. SOLUTION: A CPU 11 and I/O units 12-14 are interconnected by the daisy chain system. That is, the CPU 11 and the I/O unit 12 are connected by read/ write signal lines 17a, 18a, the I/O units 12, 13 are connected by read/write signal lines 17b, 18b, and the I/O units 13, 14 are connected by read/write signal lines 17c, 18c. The CPU 11 makes transmission reception of a data part via transmission use (TXD) and reception use (RXD) serial transmission buses 15, 16 and sends a command for the read/write signal via the read/write signal lines 17a-17c and 18a-18c of the daisy chain system.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing system in which a data processing unit and a data input / output unit are connected via a serial transmission bus.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 3, a data processing unit such as a CPU 1 and a data input / output unit such as I / O units 2 to 4 are serial for transmission (TXD) and reception (RXD). In the data processing system connected via the transmission buses 5 and 6, when the CPU 1 transmits / receives data to / from a plurality of I / O units 2 to 4 via the serial transmission buses 5 and 6, as shown in FIG. Command units C1 to C3 representing "O unit" and "Do you want to receive or send?" And data units D1 to D of "Transmission / reception data"
Both of them are transmitted and received via the serial transmission buses 5 and 6.

[0003]

However, in such a data processing system, when transmitting and receiving data,
Both the command part indicating "to which I / O unit" and "whether you want to receive or send" and the data part of "sent / received data" are transmitted and received via the serial transmission bus. Since it was necessary, there was a problem that the transmission delay became large.

That is, as shown in FIG. 3, for example, a CPU
The unit 1 has a command part and a data part each consisting of 1 byte, and the three I / Os are connected via the serial transmission buses 5 and 6.
When attempting to transmit the data to each of the units 2 to 4, a total of 6 bytes of serial data is required, which increases the transmission time and the transmission delay.

Therefore, the present invention has been made in view of such a problem, and an object thereof is to provide a data processing system having a small transmission delay even when data is transmitted via a serial transmission bus.

[0006]

To achieve the above object, the invention according to claim 1 is a data processing system in which a data processing unit and a plurality of data input / output units are connected via a serial transmission bus. Then, the data processing unit and the plurality of data input / output units are connected by a daisy chain type command signal line, and the data processing unit transmits a command signal through the command signal line to transmit the serial signal. Data is transmitted and received to and from the plurality of data input / output units via a transmission bus.

[0007] According to the second aspect of the present invention, the first aspect is provided.
In the described data processing system, the plurality of data input / output units perform data transmission / reception via the serial transmission bus when the command signal is received via the command signal line, and when the data transmission / reception ends. A command signal is transmitted to the next data input / output unit via the command signal line.

[0008] According to the third aspect of the present invention, the first aspect of the present invention.
Alternatively, in the data processing system according to claim 2, the data processing unit transmits a read / write signal as a command signal, and the command signal line is a read / write signal line to which the read / write signal is transmitted. Characterize.

Therefore, according to the present invention, only data is transmitted and received on the serial transmission bus, and commands such as read / write signals are connected in a daisy chain between the data processing unit and the plurality of data input / output units. The transmission amount on the serial transmission bus is reduced by the command.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a data processing system according to the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of a data processing system according to the present invention.

In an embodiment of this data processing system,
As shown in the figure, one CPU 11 and a plurality of (in the present embodiment, three I / O units 12 to 12) I-O units 12 to.
14 and the CPU 11 and the I / O units 12 to 14 are connected via serial transmission buses 15 and 16 for transmission (TXD) and reception (RXD). This is the same as the configuration of the related art shown in FIG.

In the data processing system of this embodiment, since only read / write signals are handled as commands, the CPU 11 and the I / O units 12-1 are further used.
4 are read / write signal lines 17a to 17c and 18a to 18 which are command signal lines of a daisy chain system.
It is characterized by connecting with c.

That is, specifically, as shown in FIG.
A read signal line 1 is provided between the PU 11 and the I / O unit 12.
7a and the write signal line 18a, and the read signal line 17 is provided between the I / O unit 12 and the I / O unit 13.
b and the write signal line 18b, and the read signal line 17c is provided between the I / O unit 13 and the I / O unit 14.
And a write signal line 18c.

Then, in this embodiment, the CPU 11 is
For transmission with each I / O unit 12-14 (TX
D) and receiving (RXD) serial transmission bus 15,
16 transmits / receives data via the daisy chain type read / write signal lines 17a to 17c, 18
It is configured to transmit a command of a read / write signal via a to 18c.

Further, when each I / O unit 12-14 receives a command of a read / write signal from the unit on the left side of the drawing via the read / write signal lines 17a-17c, 18a-18c, C via serial transmission bus
While transmitting / receiving data to / from the PU 11, when the transmission / reception of data is completed, the read / write signal lines 17a to 17c, 18a to the next I / O unit on the right side of the drawing are transmitted.
It is configured to send a read / write signal via 18c.

Next, the operation of the data processing system of the present embodiment configured as described above will be described with reference to the drawings.

2 (a) to 2 (d), the CPU 11 controls each I
The states of the respective serial transmission buses and signal lines when transmitting data to the / O units 12 to 14 are shown.

FIG. 2A shows a transmission (TX) when the CPU 11 transmits data to each I / O unit 12-14.
3D shows the state of the serial transmission bus 15 of D). In the present embodiment, no command is transmitted on this serial transmission bus 15, and only the data to be transmitted to the I / O units 12 to 14 is transmitted. It is shown that.

Therefore, in this embodiment, as shown in FIG.
As shown in (a), assuming that each data to the I / O units 12 to 14 is 1 byte, the total amount of data transmitted on the serial transmission bus 15 is 3 bytes.

FIG. 2B shows the state of the write signal line 18a when the write signal command is transmitted from the CPU 11 to the I / O unit 12.

That is, the CPU 11 sets the write signal line 18b connected to the I / O unit 12 to "H" at the timing of
Set to IGH "to notify a write command, that is, to transmit data to the I / O unit 12.

Therefore, the I / O unit 12 is shown in FIG.
As shown in (a), the data D1 to the I / O unit 12 transmitted on the transmission (TXD) serial communication bus 15 by the CPU 11 can be received at the timing of.

FIG. 2C shows I / O units 12 to I.
The state of the write signal line 18b for transmitting a write signal command to the / O unit 13 is shown.

That is, the I / O unit 12 receives the data D2 from the CPU 11 at the timing of, and when the reception of the data D1 is completed, the write signal line 18b between the I / O unit 13 and the I / O unit 13 is immediately. To "H
Set to IGH "to notify the I / O unit 13 that data will be transmitted.

Therefore, the I / O unit 13 is shown in FIG.
As shown in (a), the data D2 to the I / O unit 13 transmitted by the CPU 11 on the transmission (TXD) serial communication bus 15 can be received at the timing of.

FIG. 2D shows the I / O units 13 to I.
The state of the write signal line 18c for transmitting a write signal command to the / O unit 13 is shown.

That is, the I / O unit 13 receives the data D2 from the CPU 11 at the timing of, and when the reception of the data D2 is completed, the write signal line 18c with the I / O unit 14 is immediately transmitted at the timing. To "H
Set to IGH "to notify the I / O unit 14 that data will be transmitted.

Therefore, the I / O unit 14 is shown in FIG.
As shown in (a), the data D3 to the I / O unit 14 transmitted from the transmission (TXD) serial communication bus 15 by the CPU 11 can be received at the timing.

Therefore, in this embodiment, as shown in FIG. 2A, even when the CPU 11 transmits data to the I / O units 12 to 14, the transmission serial transmission bus 1 is used.
Only the data to be transmitted is carried on the transmission line 5, and the write command as the command is transmitted via the write signal lines 18a to 18c of the transmission system as shown in FIGS. Since it is sequentially transmitted to the I / O units 12 to 14,
The transmission amount on the transmission serial transmission bus 15 is 3 bytes, which is half that of the conventional case of 6 bytes shown in FIG. 4, and the transmission amount is halved.

The same operation as above is performed for reception (RX
D) Each I / O unit 1 using the serial transmission bus 16
This can also be explained in the case of data transmission from 2 to 14 to the CPU 11, and in this case, the CPU 11 to the read signal line 17
A read command is sent to the I / O unit 12 via
The / O unit 12 receives the read command and receives the data of its own unit (RXD) serial transmission bus 1
6 to the CPU 11, and when the transmission is completed, a read command is sent to the I / O unit 13 via the read signal line 17b, and the I / O unit 13 receives the read command, Data is sent to the CPU 11 via the serial transmission bus 16, and when the transmission is completed, the I / O unit 1 is sent via the read signal line 17c.
This is carried out by repeating the process of sending a read command to No. 4.

Therefore, according to this embodiment, the CPU 11
And the I / O units 12 to 14 between the daisy chain type read / write signal lines 17a to 17c and 18
a to 18c are provided, and the read / write signal lines 17a to
Since the read / write command signal is transmitted by 17c and 18a to 18c, it is not necessary to transmit the read / write command signal on the serial transmission buses 15 and 16, and only the data to be transmitted is transmitted. Since transmission is performed, the amount of transmission on the serial transmission bus is reduced, and it is possible to achieve a high-speed serial transmission bus without transmission delay.

[0033]

As described above, according to the present invention, the CP
A daisy-chain type command signal line is provided between the data processing unit such as U and the data input / output unit such as I / O unit, and the command signal line is used to transmit the command. Since it is not necessary to transmit a command on the transmission bus and only the data to be transmitted is transmitted, the amount of transmission on the serial transmission bus is reduced and a high-speed serial transmission bus with no transmission delay is achieved. It will be possible.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an embodiment of a data processing system according to the present invention.

2 (a) to (d), the CPU has each I / O.
The timing chart which shows the state of the serial transmission bus and the command signal line at the time of transmitting data to a unit.

FIG. 3 is a configuration diagram showing a configuration of a conventional data processing system.

FIG. 4 is an explanatory diagram showing transmission data on a serial transmission bus in a conventional data processing system.

[Explanation of symbols]

 11 CPU (data processing unit) 12 I / O unit (data input / output unit) 13 I / O unit (data input / output unit) 14 I / O unit (data input / output unit) 15 Serial transmission bus for transmission (TXD) 16 Reception serial transmission bus (RXD) 17a to 17b Read signal line (command signal line) 18a to 18b Write signal line (command signal line)

Claims (3)

[Claims] 1. A data processing system in which a data processing unit and a plurality of data input / output units are connected via a serial transmission bus, and a daisy line is provided between the data processing unit and the plurality of data input / output units. Connected by a chain type command signal line, the data processing unit transmits a command signal via the command signal line and transmits / receives data to / from the plurality of data input / output units via the serial transmission bus. A data processing system characterized by: 2. The plurality of data input / output units perform data transmission / reception via the serial transmission bus when a command signal is received via the command signal line, and when the data transmission / reception ends, next data transmission / reception is performed. The data processing system according to claim 1, wherein a command signal is transmitted to the data input / output unit of the above through a command signal line. 3. The data processing unit transmits a read / write signal as a command signal, and the command signal line is a read / write signal line to which a read / write signal is transmitted. Alternatively, the data processing system according to claim 2.