JP2006146430A - Data input/output device, data input/output system and data communication method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To attain data input/output for performing a high speed operation in a simple configuration. <P>SOLUTION: A first data input/output device 10 is configured as an IC chip equipped with a transmission clock terminal 103 for transmitting a clock to a second data input/output device 20, a transmission data output part having an output timing control circuit 104 for outputting transmission data synchronously with the timing of the clock, a transmission data terminal 107 for transmitting the transmission data to the second data input/output device 20, a reception clock terminal 110 for receiving an external clock different from the clock, a reception data inputting part having an input timing control circuit 115 for inputting the reception data synchronizing with the external clock from the second data input/output device 20 and a reception data terminal 116 for receiving the reception data. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a data input / output device that transfers data to and from an external device, and a data input / output system and a data communication method using such a data input / output device.

Japanese Patent Laid-Open No. 2004-260688 discloses the relationship between the clock reference signal output and the common clock signal so that the common clock signal has a higher frequency without being affected by the operation speed of the logic element, the delay due to wiring, and the variation in these values. A technique for creating correction data based on a phase difference is disclosed.
Japanese Patent Laid-Open No. 3-171945

  However, performing a correction circuit, setting, and the like to cope with the delay increases complexity and scale.

  The present invention has been made in view of the above points, and provides a data input / output device, a data input / output system, and a data communication method that enable data input / output capable of high-speed operation with a simple configuration. With the goal.

In order to achieve the above object, one aspect of the data input / output device of the present invention is:
A transmission clock terminal for transmitting a clock to an external device;
A transmission data output unit having an output timing control circuit for outputting transmission data synchronized with the timing of the clock;
A transmission data terminal for transmitting the transmission data output from the transmission data output unit to the external device;
A reception clock terminal for receiving an external clock different from the above clock;
A reception data input unit having an input timing control circuit for inputting reception data synchronized with the external clock received by the reception clock terminal from the external device;
A reception data terminal for receiving the reception data input to the reception data input unit;
It is characterized by comprising.

Also, one aspect of the data input / output system of the present invention is:
In a data input / output system comprising a first data input / output device and a second data input / output device,
The first data input / output device includes:
A clock generator for generating a first clock;
A transmission clock terminal for transmitting the first clock generated by the clock generation unit to the second data input / output device;
A transmission data output unit having an output timing control circuit for outputting first data synchronized with the timing of the first clock generated by the clock generation unit;
A transmission data terminal for transmitting the first data output from the transmission data output unit to the second data input / output device;
A reception clock terminal for receiving a second clock different from the first clock generated by the clock generator;
A reception data input unit having an input timing control circuit for inputting second data synchronized with the second clock received by the reception clock terminal from the second data input / output device;
A reception data terminal for receiving the second data input to the reception data input unit;
With
The second data input / output device is
A clock input terminal connected to the transmission clock terminal of the first data input / output device for receiving the first clock;
A data input terminal connected to the output data terminal of the first data input / output device for receiving the first data;
A data input unit having a timing control circuit for inputting the first data received at the data input terminal in synchronization with the first clock received by the clock input terminal;
Output for outputting the second data to be output to the first data input / output device in synchronization with a second clock generated based on the first clock received at the clock input terminal A data output unit having a timing control circuit;
A data output terminal connected to the reception data terminal of the first data input / output device and for outputting the second data output from the data output unit;
A clock output terminal connected to the reception clock terminal of the first data input / output device for outputting the second clock;
Comprising
It is characterized by that.

Also, one aspect of the data communication method of the present invention is:
A data communication method between a first data input / output device and a second data input / output device, comprising:
When transmitting data from the first data input / output device to the second data input / output device,
In the first data input / output device, the data to be transmitted is set as the first data synchronized with the timing of the first clock generated by the clock generator included in the first data input / output device. 2 to the second data input / output device, and the first clock is also transmitted to the second data input / output device,
In the second data input / output device, the first clock and the first data synchronized with the first clock are received and input,
When transmitting data from the second data input / output device to the first data input / output device,
In the second data input / output device, a second clock is generated based on the received first clock, and data to be transmitted is set as second data synchronized with the timing of the second clock. In addition to transmitting to the first data input / output device above, the second clock is also transmitted to the first data input / output device,
The first data input / output device receives and inputs the second clock and the second data synchronized with the second clock;
It is characterized by that.

  According to the present invention, it is possible to provide a data input / output device, a data input / output system, and a data communication method that enable data input / output capable of high-speed operation with a simple configuration.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

[First Embodiment]
FIG. 1 is a diagram showing a configuration of a data input / output system according to the first embodiment of the present invention.

  The data input / output system includes a first data input / output device 10 that is a data input / output according to the first embodiment of the present invention, and a second data that is also a data input / output according to the first embodiment of the present invention. It comprises an input / output device 20. Here, the first data input / output device 10 functions as a master device, and the second data input / output device 20 functions as a slave device, and each is provided in the form of an IC chip.

  The first data input / output device 10 includes a clock generation unit 101 that generates a first clock CLK1. The first clock CLK1 generated by the clock generator 101 is applied to the transmission clock terminal 103 via the buffer 102, and the second data input / output device is connected from the transmission clock terminal 103 to a wiring on a substrate (not shown). 20 is transmitted. The first clock CLK1 is a clock terminal of the output timing control circuit 104 that forms part of the transmission data output unit, and a clock of the control signal output timing control circuit 105 that forms part of the control signal output unit. Also given to each terminal.

  The output timing control circuit 104 is composed of a flip-flop (F / F), and the data input to the first data input / output device 10 and applied to the data terminal of the F / F It is output in synchronization with the timing of the first clock CLK1 generated by the clock generator 101. Then, the output data is given to the transmission data terminal 107 via the buffer 106 that also constitutes a part of the transmission data output unit. Although not specifically shown, actually, the timing of the first clock CLK1 applied to the transmission clock terminal 103 and the timing described above are considered in consideration of the delay due to the output timing control circuit 104 and the delay due to the wiring capacitance. In order to ensure synchronization with the data supplied to the transmission data terminal 107, a delay element is appropriately arranged to adjust the delay. The data supplied to the transmission data terminal 107 is transmitted from the transmission data terminal 107 as the first data DAT1 to the second data input / output device 20 through wiring on a substrate (not shown).

  Thereby, as shown in FIG. 2A, the first data DATA1 synchronized with the timing of the first clock CLK1 is transmitted from the first data input / output device 10 to the second data input / output device 20. Will be.

  Similarly, the control signal output timing control circuit 105 is also composed of an F / F, and the control signal input to the first data input / output device 10 and applied to the data terminal of the F / F is converted to the clock signal. The signal is output in synchronization with the timing of the first clock CLK1 generated by the generator 101. The outputted control signal is given to the control signal transmission terminal 109 via the buffer 108 that also constitutes a part of the control signal output unit. In this case as well, although not particularly illustrated, an appropriate delay element is used so that the control signal applied to the control signal transmission terminal 109 is surely synchronized with the timing of the first clock CLK1 applied to the transmission clock terminal 103. To adjust the delay. The control signal applied to the control signal transmission terminal 109 is transmitted from the control signal transmission terminal 109 to the second data input / output device 20 as a first control signal DEN1 through a wiring on a substrate (not shown). Is done. Here, the first control signal DEN1 is an enable signal for data communication.

  The first data input / output device 10 also includes a reception clock terminal 110 for receiving the second clock CLK2 sent from the second data input / output device 20 through a wiring on a substrate (not shown). . Here, the second clock CLK2 is asynchronous with the first clock CLK1 generated by the clock generator 101, as shown in FIG. The second clock CLK2 received at the reception clock terminal 110 is supplied to the control signal input timing control circuit 112 constituting a part of the control signal input unit via the buffer 111. The control signal input timing control circuit 112 is constituted by an F / F, and the second clock CLK2 is applied to the clock terminal of the F / F. At the data terminal of the control signal input timing control circuit 112, the second control signal GRNT2 synchronized with the second clock CLK2 received at the control signal receiving terminal 113 constitutes a part of the control signal input unit. It is input via the buffer 114. Here, the second control signal GRNT2 is a data communication permission signal sent from the second data input / output device 20 through a wiring on a substrate (not shown) in accordance with the first control signal DEN1. is there. The F / F constituting the control signal input timing control circuit 112 outputs the second control signal GRNT2 input to the data terminal in accordance with the timing of the second clock CLK2 applied to the clock terminal. To do. As a result, the second control signal GRNT2 synchronized with the timing of the second clock CLK2 can be input to the first data input / output device 10.

  With the above configuration, the first data input / output device 10 can function as a data output device.

  Furthermore, the first data input / output device 10 can function as a data input device. Therefore, in the first data input / output device 10, the input clock control that the second clock CLK 2 received at the reception clock terminal 110 constitutes a part of the reception data input unit via the buffer 111. The circuit 115 is also provided. The input timing control circuit 115 is composed of an F / F, and the second clock CLK2 is applied to the clock terminal of the F / F. At the data terminal of the F / F constituting the input timing control circuit 115, the second data DAT2 synchronized with the second clock CLK2 received at the reception data terminal 116 constitutes a part of the reception data input unit. Input via the buffer 117. The F / F constituting the input timing control circuit 115 outputs the second data DAT2 input to the data terminal in accordance with the timing of the second clock CLK2 applied to the clock terminal. As a result, as shown in FIG. 2A, the second data DATA2 synchronized with the timing of the second clock CLK2 can be input to the first data input / output device 10.

  In this case, the second control signal is not GRNT2, which is a data communication permission signal, but DEN2, which is a data communication enable signal. The first control signal is not DEN1, which is a data communication enable signal, but GRNT1, which is a data communication permission signal.

  The second data input / output device 20 is different from the first data input / output device 10 except that the second data input / output device 20 does not have its own clock generation unit, unlike the first data input / output device 10. The configuration is the same as that of the first data input / output device 10.

  That is, the second data input / output device 20 is connected to the transmission clock terminal 103 of the first data input / output device 10 via a wiring on a substrate (not shown) and receives the first clock CLK1. A clock input terminal 201 is provided. The first clock CLK1 received at the clock input terminal 201 is supplied via the buffer 202 to the timing control circuit 203 constituting a part of the data input unit. The timing control circuit 203 is composed of an F / F, and the first clock CLK1 is applied to the clock terminal of the F / F. The data terminal of the F / F constituting the timing control circuit 203 is a data input terminal 204 connected to the transmission data terminal 107 of the first data input / output device 10 via a wiring on a substrate (not shown). The received first data DAT1 synchronized with the first clock CLK1 is input via the buffer 205 which also constitutes a part of the data input unit. The F / F constituting the timing control circuit 203 outputs the first data DAT1 input to the data terminal in accordance with the timing of the first clock CLK1 applied to the clock terminal. In this way, as shown in FIG. 2A, the first data DATA1 synchronized with the timing of the first clock CLK1 can be input to the second data input / output device 20. .

  The first clock CLK1 output from the buffer 202 is also supplied to a control input timing control circuit 206 constituting a part of the control input unit. The control input timing control circuit 206 is constituted by an F / F, and the first clock CLK1 is applied to the clock terminal of the F / F. The data terminal of the control input timing control circuit 206 is received by the control signal input terminal 207 connected to the control signal transmission terminal 109 of the first data input / output device 10 via a wiring on the substrate (not shown). A first control signal DEN1 synchronized with the first clock CLK1 is input via a buffer 208 that also constitutes a part of the control input unit. The F / F constituting the control input timing control circuit 206 outputs the first control signal DEN1 input to the data terminal according to the timing of the first clock CLK1 applied to the clock terminal. . In this manner, the first control signal DEN1 synchronized with the timing of the first clock CLK1 can be input to the second data input / output device 20.

  With the above configuration, the second data input / output device 20 can function as a data input device.

  Still further, the second data input / output device 20 can function as a data output device. Therefore, in the second data input / output device 20, the first clock CLK1 output from the buffer 202 is transmitted from the transmission clock terminal 103 of the first data input / output device 10 by the wiring capacity or the like. The second clock CLK2 that is asynchronous with the first clock CLK1 is supplied to the clock output terminal 210 via the buffer 209, and the first data is transmitted from the clock output terminal 210 through a wiring (not shown) on the substrate. The data is transmitted to the reception clock terminal 110 of the input / output device 10. The second clock CLK2 is also supplied to the clock terminal of the output timing control circuit 211 that forms part of the data output unit and the clock terminal of the control output timing control circuit 212 that forms part of the control output unit. Given each.

  Here, the output timing control circuit 211 is constituted by an F / F, and the data input to the second data input / output device 20 and applied to the data terminal of the F / F is converted to the second clock CLK2. Output in sync with the timing of. Then, the output data is given to the data output terminal 214 via the buffer 213 that also constitutes a part of the data output unit. Although not specifically shown, actually, the timing of the second clock CLK2 applied to the clock output terminal 210 and the timing described above in consideration of the delay due to the output timing control circuit 211, the delay due to the wiring capacitance, and the like. In order to ensure synchronization with the data supplied to the data output terminal 214, a delay element is appropriately arranged to adjust the delay. Then, the data supplied to the data output terminal 214 is supplied as the second data DAT2 from the data output terminal 214 to the reception data terminal 116 of the first data input / output device 10 through a wiring on the substrate (not shown). It is sent to.

  As a result, as shown in FIG. 2A, the second data DATA2 synchronized with the timing of the second clock CLK2 is transmitted from the second data input / output device 20 to the first data input / output device 10. Will be.

  Similarly, the control output timing control circuit 212 is also composed of an F / F, and the control signal input to the second data input / output device 20 and applied to the data terminal of the F / F is sent to the second data input / output device 20. Is output in synchronization with the timing of the clock CLK2. The output control signal is applied to the control signal output terminal 216 via a buffer 215 that also constitutes a part of the control output unit. In this case as well, although not particularly illustrated, an appropriate delay element is used so that the control signal applied to the control signal output terminal 216 is surely synchronized with the timing of the second clock CLK2 applied to the clock output terminal 210. To adjust the delay. Then, the control signal given to the control signal output terminal 216 is used as the second control signal DEN2 from the control signal output terminal 216 through the wiring on the substrate (not shown), and the control of the first data input / output device 10 is performed. It is transmitted to the signal receiving terminal 113.

  As described above, according to the first embodiment, the first clock CLK1 and the second clock are different from the general communication having the clock transmission unit for both communication and the circuit that inputs the common clock to both. Asynchronous with the clock CLK2. However, the first clock CLK1 and the first data DAT1 are synchronized, and the second clock CLK2 and the second data DAT2 are synchronized so that data is transmitted and received. ing. Therefore, since it is not necessary to synchronize between the two data input / output devices, correction circuits and settings for dealing with delays are unnecessary, and data can be input / output with a simple configuration. In addition, each can input / output data at high speed according to its own clock.

  Further, the data input / output device may have a plurality of systems, and an external I / F can be used in a multi-chip configuration. At this time, the original clock may be present in at least one system and the IC chip of the data input / output device as the master.

  Thereby, since it can utilize as a multichip structure, it becomes possible to respond to various structures for expanding functions and improving performance.

[Second Embodiment]
FIG. 3 is a diagram showing the configuration of the data input / output system according to the second embodiment. The data input / output system according to this embodiment is the same as the first data input / output device 10 that is a data input / output according to the second embodiment of the present invention, and the data input / output according to the second embodiment of the present invention. It consists of a second data input / output device 20. Here, the first data input / output device 10 functions as a master device, and the second data input / output device 20 functions as a slave device, and each is provided in the form of an IC chip.

  The transmission data terminal and the reception data terminal of the first data input / output device 10 are also used as bidirectional transmission / reception data terminals, and the data input terminal and the data output terminal of the second data input / output device 20 are used. It is also used as a bidirectional data input / output terminal. In this case, of the wiring between the two data input / output devices, at least the wiring for data communication is configured as a bidirectional bus.

  That is, in such a data input / output system according to the second embodiment, the first data input / output device 10 has n bidirectional transmission / reception data terminals 118-1 to 118-n. These transmission / reception data terminals 118-1 to 118-n have output timing control circuits 104-1 to 104-n and buffers 106-1 to 106-n having the same configuration as that of the transmission data output unit in the first embodiment. Is connected. In addition, input timing control circuits 115-1 to 115-n and buffers 117-1 to 117-n such as the reception data input unit in the first embodiment are connected. However, in this case, delays 119-1 to 119-n are arranged between the input timing control circuits 115-1 to 115-n and the buffers 117-1 to 117-n. This is because the second clock CLK2 received at the reception clock terminal 110 is supplied to the clock terminals of the F / Fs constituting the input timing control circuits 115-1 to 115-n via the buffer 111 as the clock tree 120. Since the clock generated by the clock tree 120 is used, the time corresponding to the data terminals of the F / Fs constituting the input timing control circuits 115-1 to 115-n is delayed. Is provided.

  Further, the first data input / output device 10 has two bidirectional control signal transmission / reception terminals 121a and 121b. The control signal transmission / reception terminals 121a and 121b are connected to control signal output timing control circuits 105a and 105b and buffers 108a and 108b having the same configuration as the control signal output unit in the first embodiment. Also, control signal input timing control circuits 112a and 112b and buffers 114a and 114b such as the control signal input unit in the first embodiment are connected. In this case, however, delays 122a and 122b for compensating for the delay time due to the clock tree 120 are arranged between the control signal input timing control circuits 112a and 112b and the buffers 114a and 114b.

  On the other hand, the second data input / output device 20 has n bidirectional data input / output terminals 217-1 to 217-n. These data input / output terminals 217-1 to 217-n include output timing control circuits 211-1 to 211-n and buffers 213-1 to 213-n having the same configuration as that of the data output unit in the first embodiment. Is connected. In addition, timing control circuits 203-1 to 203-n and buffers 205-1 to 205-n such as data input units in the first embodiment are connected. However, in this case, delays 218-1 to 218-n are arranged between the timing control circuits 203-1 to 203-n and the buffers 205-1 to 205-n. This is because the first clock CLK1 received at the clock input terminal 201 is sent to the clock tree 219 via the buffer 202 as a clock given to the clock terminals of the F / Fs constituting the timing control circuits 203-1 to 203-n. Since the clock input and generated by the clock tree 219 is used, it is provided to delay the time corresponding to the data terminals of the F / F constituting the timing control circuits 203-1 to 203-n. It is what.

  Further, the second data input / output device 20 has two bidirectional control signal input / output terminals 220a and 220b. The control signal input / output terminals 220a and 220b are connected to control output timing control circuits 212a and 212b and buffers 215a and 215b having the same configuration as that of the control output unit in the first embodiment. Further, control input timing control circuits 206a and 206b and buffers 208a and 208b such as the control input unit in the first embodiment are connected. In this case, however, delays 221a and 221b for compensating for the delay time due to the clock tree 219 are arranged between the control input timing control circuits 206a and 206b and the buffers 208a and 208b.

  Even with such a configuration, the same effects as those of the first embodiment can be obtained. Furthermore, in this embodiment, since n-bit data can be communicated at a time, further speedup can be achieved.

  However, in consideration of transferring the data received by the data communication device on the receiving side to an external device having a low operating speed, for example, storing it in an SDRAM or the like provided outside the IC chip of the data communication device. As shown in FIG. 2B, for example, in the case of the second data input / output device 20, it is preferable to provide an input data buffer 222 in the subsequent stage of the timing control circuits 203-1 to 203-n. The input data buffer 222 is configured to have a capacity of 4 pages, for example, when one page is a 16-byte burst length as an SDRAM communication unit.

  In this case, as shown in FIG. 4, the control signal GRNT2 applied to the data terminal of the control output timing control circuit 212b falls when the number of remaining pages (that is, free capacity) of the input data buffer 222 becomes one page. The control signal GRANT2 is output from the control signal input / output terminal 220b to the first data input / output device 10 in synchronization with the second clock CLK2 that is asynchronous with the first clock CLK1. At this time, the control signal GRANT2 is delayed by the delay 122b after it is received by the control signal transmission / reception terminal 121b of the first data input / output device 10 due to the wiring capacity of the wiring on the substrate (not shown). Then, the first data input / output device 10 is input to the control signal input timing control circuit 112b. Therefore, after the output of the control signal GRANT2 from the second data input / output device 20, the data output from the transmission / reception data terminals 118-1 to 118-n of the first data input / output device 10 is immediately stopped. However, the control signal DEN1 from the control signal transmission / reception terminal 121a is also stopped with a delay.

  When data transfer from the input data buffer 222 to the SDRAM or the like proceeds and the remaining number of pages returns to two pages, the control signal GRNT2 applied to the data terminal of the control output timing control circuit 212b is raised, The control signal GRANT2 is output from the control signal input / output terminal 220b to the first data input / output device 10 in synchronization with the second clock CLK2. As a result, the control signal DEN1 from the control signal transmission / reception terminal 121a of the first data input / output device 10 is output with the above-mentioned delay, and also from the transmission / reception data terminals 118-1 to 118-n. Data output will be resumed.

  As described above, when the number of remaining pages of the input data buffer 222 becomes one page, the data output from the first data input / output device 10 is stopped so that the input data buffer 222 does not overflow. be able to.

  Although only the input data buffer 222 of the second data input / output device 20 has been described here, it is needless to say that a similar input data buffer may be provided in the first data input / output device 10 as well. In FIG. 4, the case where the control signal GRANT2 falls when the number of remaining pages of the input data buffer 222 becomes one page has been described. However, the control signal DEN1 falls after the control signal GRANT2 falls. Any timing can be used as long as the data to be transferred can be secured.

  The data input / output system according to the present embodiment as described above is, for example, a so-called three-plate digital camera having three image capturing units 30-1 to 30-3 that individually capture RGB as shown in FIG. It is preferable to apply to.

  That is, the digital camera displays image data on an image processing unit 40 that performs various image processing such as gamma correction on the image data, SDRAMs 50-1 and 50-2 that store the image data, and a liquid crystal display (not shown). A display I / F 60 and a card I / F 70 for recording image data on a recording medium (not shown).

  Here, the SDRAM 50-1 is used for storing image data processed by the image processing unit 40, for example, and the SDRAM 50-2 is used for synthesizing image data captured by the imaging units 30-1 to 30-3, for example. , And can be used to store image data from the imaging units 30-1 to 30-3. Therefore, in order to transfer the image data captured by the imaging unit 30-1 at high speed, the data input / output unit 10-1 as the first data input / output device 10 according to the present embodiment and the second data according to the present embodiment. A data input / output unit 20-1 is provided as the input / output device 20, and the first data input / output device 10 according to the present embodiment is used to transfer image data captured by the imaging unit 30-3 at high speed. The data input / output unit 10-2 and the data input / output unit 20-2 as the second data input / output device 20 according to the present embodiment are provided.

  The data output from the data input / output unit 10-2 to the data input / output unit 10-1 may be data resulting from the image composition processing on the SDRAM 50-2. The image data is transferred to the image processing unit 40 and image processing is performed.

  With such a configuration, since data can be transferred at high speed, it is possible to provide a digital camera capable of performing from imaging to writing image data to a final recording medium (not shown) at high speed. become.

  Although the present invention has been described above based on the embodiments, the present invention is not limited to the above-described embodiments, and various modifications and applications are naturally possible within the scope of the gist of the present invention.

  For example, in the above embodiment, image data is taken as an example of data to be transferred at high speed, but any data such as audio data may be used.

FIG. 1 is a diagram showing a configuration of a data input / output system according to the first embodiment of the present invention. FIG. 2A is a timing chart for explaining the operation of the data input / output system according to the first embodiment, and FIG. 2B is a data input / output system according to the second embodiment of the present invention. It is a figure for demonstrating the structure of the 2nd data input / output device in the modification. FIG. 3 is a diagram showing a configuration of a data input / output system according to the second embodiment of the present invention. FIG. 4 is a timing chart for explaining the operation of the modified example of the data input / output system according to the second embodiment. FIG. 5 is a diagram showing a configuration of a digital camera to which the data input / output system according to the second embodiment is applied.

Explanation of symbols

    DESCRIPTION OF SYMBOLS 10 ... 1st data input / output device, 10-1, 10-2, 20-1, 20-2 ... Data input / output part, 20 ... 2nd data input / output device, 30-1 to 30-3 ... Imaging 40: Image processing unit, 50-1, 50-2 ... SDRAM, 60: Display I / F, 70 ... Card I / F, 101 ... Clock generation unit, 102, 106, 106-1 to 106-n, 108, 108a, 108b, 111, 114, 114a, 114b, 117, 117-1 to 117-n, 202, 205, 205-1 to 205-n, 208, 208a, 208b, 209, 213, 213-1 to 213-n, 215, 215a, 215b ... buffer, 103 ... transmission clock terminal, 104, 104-1 to 104-n, 211, 211-1 to 211-n ... output timing control circuit, 105, 105a, 105b ... control signal output timing control circuit, 107 ... transmission data terminal, 109 ... control signal transmission terminal, 110 ... reception clock terminal, 112, 112a, 112b ... control signal input timing control circuit, 113 ... control signal reception 115, 115-1 to 115-n, input timing control circuit, 116, reception data terminal, 118-1, 118-n, transmission / reception data terminal, 1191-1 to 119-n, 122a, 122b, 218-1 218-n, 221a, 221b ... delay, 120, 219 ... clock tree, 121a, 121b ... control signal transmission / reception terminal, 201 ... clock input terminal, 203, 203-1 to 203-n ... timing control circuit, 204 ... data Input terminals 206, 206a, 206b ... Control input timing control circuit, 207 ... Control signal input terminal, 210 ... Clock output terminal, 212, 212a, 212b ... Control output timing control circuit, 214 ... Data output terminal, 216 ... Control signal output terminal, 217-1 to 217- n: Data input / output terminals, 220a, 220b: Control signal input / output terminals, 222: Input data buffer.

Claims (14)

A transmission clock terminal for transmitting a clock to an external device;
A transmission data output unit having an output timing control circuit for outputting transmission data synchronized with the timing of the clock;
A transmission data terminal for transmitting the transmission data output from the transmission data output unit to the external device;
A reception clock terminal for receiving an external clock different from the above clock;
A reception data input unit having an input timing control circuit for inputting reception data synchronized with the external clock received by the reception clock terminal from the external device;
A reception data terminal for receiving the reception data input to the reception data input unit;
A data input / output device comprising:   2. The data input / output according to claim 1, wherein the clock and the external clock are asynchronous, and the clock and the transmission data are synchronized with each other. apparatus.   The data input / output device according to claim 1, wherein the transmission data terminal and the reception data terminal are also used as bidirectional data terminals.   2. The data input / output device according to claim 1, wherein at least one of the transmission data and the reception data is image data. A control signal output unit having a control signal output timing control circuit for outputting a first control signal synchronized with the timing of the clock;
A control signal transmission terminal for transmitting the first control signal output from the control signal output unit to the external device;
A control signal input unit having a control signal input timing control circuit for inputting, from the external device, a second control signal synchronized with the external clock received by the reception clock terminal;
A control signal receiving terminal for receiving the second control signal input to the control signal input unit;
Further comprising
The data input / output device according to claim 1.   6. The data input / output device according to claim 5, wherein the control signal transmitting terminal and the control signal receiving terminal are also used as bidirectional control signal terminals. In a data input / output system comprising a first data input / output device and a second data input / output device,
The first data input / output device includes:
A clock generator for generating a first clock;
A transmission clock terminal for transmitting the first clock generated by the clock generation unit to the second data input / output device;
A transmission data output unit having an output timing control circuit for outputting first data synchronized with the timing of the first clock generated by the clock generation unit;
A transmission data terminal for transmitting the first data output from the transmission data output unit to the second data input / output device;
A reception clock terminal for receiving a second clock different from the first clock generated by the clock generator;
A reception data input unit having an input timing control circuit for inputting second data synchronized with the second clock received by the reception clock terminal from the second data input / output device;
A reception data terminal for receiving the second data input to the reception data input unit;
With
The second data input / output device is
A clock input terminal connected to the transmission clock terminal of the first data input / output device for receiving the first clock;
A data input terminal connected to the output data terminal of the first data input / output device for receiving the first data;
A data input unit having a timing control circuit for inputting the first data received at the data input terminal in synchronization with the first clock received by the clock input terminal;
Output for outputting the second data to be output to the first data input / output device in synchronization with a second clock generated based on the first clock received at the clock input terminal A data output unit having a timing control circuit;
A data output terminal connected to the reception data terminal of the first data input / output device and for outputting the second data output from the data output unit;
A clock output terminal connected to the reception clock terminal of the first data input / output device for outputting the second clock;
Comprising
A data input / output system characterized by this.   While the first clock and the second clock are asynchronous, the first clock and the first data, and the second clock and the second data are synchronized, respectively. The data input / output system according to claim 7. The transmission data terminal and the reception data terminal of the first data input / output device are also used as bidirectional transmission / reception data terminals,
The data input terminal and the data output terminal of the second data input / output device are also used as bidirectional data input / output terminals.
The data input / output system according to claim 7.   8. The data input / output system according to claim 7, wherein at least one of the first data and the second data is image data. The first data input / output device includes:
A control signal output unit having a control signal output timing control circuit for outputting a first control signal synchronized with the timing of the first clock;
A control signal transmission terminal for transmitting the first control signal output from the control signal output unit to the second data input / output device;
A control signal input unit having a control signal input timing control circuit for inputting a second control signal synchronized with the second clock received by the reception clock terminal from the second data input / output device;
A control signal receiving terminal for receiving the second control signal input to the control signal input unit;
Further comprising
The second data input / output device is
A control signal input terminal connected to the control signal transmission terminal of the first data input / output device and receiving the first control signal;
A control input unit having a control input timing control circuit for inputting the first control signal received at the control signal input terminal synchronized with the first clock received by the clock input terminal;
A control output unit having a control output timing control circuit for outputting the second control signal synchronized with the timing of the second clock;
A control signal output terminal for transmitting the second control signal output from the control output unit to the first data input / output device;
Further comprising
The data input / output system according to claim 7. The control signal transmission terminal and the control signal reception terminal of the first data input / output device are also used as bidirectional control signal transmission / reception terminals,
The control signal input terminal and the control signal output terminal of the second data input / output device are also used as bidirectional control signal input / output terminals.
The data input / output system according to claim 11. A data communication method between a first data input / output device and a second data input / output device, comprising:
When transmitting data from the first data input / output device to the second data input / output device,
In the first data input / output device, the data to be transmitted is set as the first data synchronized with the timing of the first clock generated by the clock generator included in the first data input / output device. 2 to the second data input / output device, and the first clock is also transmitted to the second data input / output device,
In the second data input / output device, the first clock and the first data synchronized with the first clock are received and input,
When transmitting data from the second data input / output device to the first data input / output device,
In the second data input / output device, a second clock is generated based on the received first clock, and data to be transmitted is set as second data synchronized with the timing of the second clock. In addition to transmitting to the first data input / output device above, the second clock is also transmitted to the first data input / output device,
The first data input / output device receives and inputs the second clock and the second data synchronized with the second clock;
A data communication method characterized by the above. The second data input / output device includes an input data buffer for buffering the input first data;
When the first data is buffered by a predetermined amount of data smaller than the amount of data that can be buffered by the input data buffer, the second data input / output device to the first data input / output device. Transmitting a signal instructing to stop transmission of the first data,
The data communication method according to claim 13.

Images