KR100885053B1 - Data Capture Circuit for Semiconductor Test Device - Google Patents

Abstract

The data capture circuit of the semiconductor test apparatus includes a phase adjuster, a clock selector, and a data capture unit. The phase adjuster adjusts phases of the first strobe signal and the second strobe signal in response to the phase control signal. The clock selector selects one of the external strobe signal and the first strobe signal in response to the clock select signal, and outputs the selected strobe signal. The clock selector outputs one of the first selected strobe signal and the second strobe signal in response to the clock selection signal. Select and output the second selected strobe signal. The data capture unit captures the semiconductor test data in synchronization with the first and second sections of the first and second selection strobe signals, respectively, and captures the data captured in synchronization with the first section and the data captured in synchronization with the second section. Output to separate output lines.

Description

Data Capture Circuit for Semiconductor Test Device {Data Capture Circuit for Semiconductor Test Device}

The present invention relates to a semiconductor test device, and more particularly, to a data capture circuit of a semiconductor test device.

Recently, with the development of semiconductor technology, the operating speed of semiconductors is increasing. For example, DRAM is developing into a semiconductor that operates at higher speeds, such as DDR2 and DDR3. In general, during the production process of the semiconductor memory includes testing the normal operation of the memory. However, as the operating speed of the memory becomes faster, the operating speed of the test equipment for testing the memory also needs to be increased according to the operating speed of the memory device.

1 is a block diagram illustrating a data exchange process between two systems having different operating speeds.

Referring to FIG. 1, a circuit for mediating a data exchange between systems 110 and 120 having different operating speeds may be needed. For example, when the first system 110 operates internally at 1.6 GBps and the second system 120 operates internally at 800 MBps, data may be directly generated due to the difference in data transfer rates between the two systems 110 and 120. Transmission is difficult

Even when testing a semiconductor device using a semiconductor test equipment, it is necessary to test the read / write operation of data at the normal operating speed of the semiconductor device. Test equipment may be redesigned to test semiconductor devices. Therefore, as the speed of semiconductor devices increases, the cost is increased due to the redesign of test equipment.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a data capture circuit of a semiconductor test apparatus for transferring data between systems at different operating speeds.

A data capture circuit of a semiconductor test apparatus according to an embodiment of the present invention for achieving the object of the present invention includes a phase adjuster, a clock selector, a data capture unit. The phase adjuster adjusts phases of the first strobe signal and the second strobe signal in response to the phase control signal. The clock selector selects one of an external strobe signal and the first strobe signal in response to a clock selection signal, and outputs the first strobe signal in response to the clock selection signal. The clock selection signal selects one of the first and second strobe signals. One of the signals is selected and output as the second selection strobe signal. The data capture unit captures semiconductor test data in synchronization with first and second sections of each of the first and second selection strobe signals, and captures data captured in synchronization with the first section and in synchronization with the second section. The output data to separate output lines.

The bandwidth of the semiconductor test data may be greater than an integer multiple of the bandwidth of data captured in synchronization with the first period of the first and second selection strobe signals. In addition, the bandwidth of the semiconductor test data may be greater than an integer multiple of the bandwidth of data captured in synchronization with the second period of the first and second selection strobe signals.

The first period of the first and second selection strobe signals may be rising edges, and the second period of the first and second selection strobe signals may be falling edges.

The data capture unit may include first to fourth flip-flop blocks. The first flip-flop block captures and outputs first bits of the test data in response to a first period of the first selection strobe signal. The second flip-flop block captures and outputs the first bits of the test data in response to the second period of the first selection strobe signal. The third flip-flop block captures and outputs second bits of the test data in response to the first period of the second selection strobe signal. The fourth flip-flop block captures and outputs the second bits of the test data in response to the second period of the second selection strobe signal.

The phase controller adjusts phases of the first and second selection strobe signals so that the first and second periods of the first and second selection strobe signals are synchronized with each other in a period where no data transition of the semiconductor test data occurs. The phase of the test data may be delayed more than 90 degrees.

The phase adjuster may include first and second delay locked loops. The first delay locked loop may adjust the phase of the first strobe signal in response to the phase adjustment signal. The second delay locked loop may adjust the phase of the second strobe signal in response to the phase control signal.

The clock selector may include first and second multiplexers. The first multiplexer may select one of an external strobe signal and the first strobe signal in response to the clock selection signal to output the first selection strobe signal. The second multiplexer may select one of the first selection strobe signal and the second strobe signal in response to the clock selection signal to output the second selection strobe signal.

When the first multiplexer selects the first strobe signal and the second multiplexer selects the second strobe signal, the first bits and the second bits may be independently tested.

The first bits may be lower 4 bits of the test data, and the second bits may be upper 4 bits of the test data.

The data capture circuit of the semiconductor test apparatus may include a first strobe signal capture unit configured to capture the first strobe signal in synchronization with a first section and a second section of the external strobe signal, and a first section of the first selected strobe signal; The electronic device may further include a second strobe signal capture unit configured to capture the second strobe signal in synchronization with a second section.

The data capture circuit of the semiconductor test apparatus according to an embodiment of the present invention may transfer data between systems having different operating speeds.

With respect to the embodiments of the present invention disclosed in the text, specific structural to functional descriptions are merely illustrated for the purpose of describing embodiments of the present invention, embodiments of the present invention may be implemented in various forms and It should not be construed as limited to the embodiments described in.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to a specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the drawings, similar reference numerals are used for similar elements.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, a low noise amplifier and a signal amplifying method according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same elements in the drawings, and duplicate descriptions of the same elements are omitted.

2 is a block diagram illustrating a data capture circuit of a semiconductor test apparatus according to an embodiment of the present invention.

2, the data capture circuit 200 of the semiconductor test apparatus includes a phase adjuster 210, a clock selector 220, and a data capture unit 230.

The phase controller 210 adjusts phases of the first strobe signal STB1 and the second strobe signal STB2. The phase adjuster 210 may use the first and second delay locked loops DLL1 and DLL2 to adjust phases of the first strobe signal STB1 and the second strobe signal STB2. A buffer BUF1 and a BUF2 for buffering the first strobe signal STB1 and the second strobe signal STB2 input to the two delay locked loops DLL1 and DLL2 may be included. The phase adjuster 210 has rising edges on the first and second strobe signals STB1 and STB2, respectively, in a section in which no data transition occurs between the first bits DQ1 and the second bits DQ2 of the semiconductor test data. The phases of the first and second strobe signals STB1 and STB2 are adjusted to synchronize the and falling edges so that the data capture unit 230 does not generate an error when data is captured.

The clock selector 220 selects a strobe signal for capturing the first bits DQ1 and the second bits DQ2 of the semiconductor test data. The clock selector 220 may include a first multiplexer MUX1 and a second multiplexer MUX2. The first multiplexer selects one of the first strobe signal STB1 and the external strobe signal STBE in response to the clock selection signal SEL to output the first selection strobe signal SLSTB1. The second multiplexer MUX2 selects one of the first selection strobe signal SLSTB1 and the second strobe signal selected by the first multiplexer MUX1 in response to the clock selection signal SEL to select the second selection strobe. The signal SLSTB2 is output. Accordingly, the first selection strobe signal SLSTB1 and the second selection strobe signal SLSTB2 may be the same signal or different signals.

The data capture unit 230 captures the first bits DQ1 and the second bits DQ2 of the semiconductor test data in synchronization with the first selection strobe signal SLSTB1 and the second selection strobe signal SLSTB2, respectively. .

In one embodiment, the data capture unit 230 may be implemented using a plurality of flip-flops. In this case, the data capture unit 230 may include a first flip-flop block FB1, a second flip-flop block FB2, and a first flip-flop block. The third flip-flop block FB3 and the fourth flip-flop block FB4 may be included. The first flip-flop block FB1 captures the first bits DQ1 in synchronization with the rising edge that is the first period of the first select strobe signal, and the second flip-flop block FB2 captures the first select strobe signal. The first bits DQ1 are captured in synchronization with the falling edge that is the second period, and the third flip-flop block FB3 captures the second bits DQ2 in synchronization with the rising edge that is the first period of the second selection strobe signal. ), And the fourth flip-flop block FB4 captures the second bits DQ2 in synchronization with the falling edge which is the second period of the second selection strobe signal SLSTB2.

In one embodiment, the first interval is the every rising edge of the strobe signals, and the second interval is the every falling edge of the strobe signals. However, the first section and the second section may be modified according to the embodiment. When the clock frequency of the strobe signal is further increased, the rising edges of each cycle may be alternately used as the first interval and the second interval.

Data captured by the first and second flip-flop blocks FB1 and FB2 are simultaneously output through output lines separated from each other in synchronization with the falling edge of the first selection strobe signal SLSTB1. In addition, the data captured by the third and fourth flip-flop blocks FB3 and FB4 are simultaneously output through output lines separated from each other in synchronization with the falling edge of the second selection strobe signal SLSTB2. When the first and second selection strobe signals SLSTB1 and SLSTB2 are selected by the clock selector 220 as the same signal, the data captured by the first to fourth flip-flops may be simultaneously output.

3 is a circuit diagram illustrating a data capture circuit of a semiconductor test apparatus according to an embodiment of the present invention.

Referring to FIG. 3, the data capture circuit 200 of the semiconductor test apparatus includes a phase adjuster 210, a clock selector 220, and a data capture unit 230.

The phase adjuster 210 adjusts phase by using the first and second delay locked loops DLL1 and DLL2, and the phase control signal PHSET and the reference clock REFCLK for adjusting the degree of phase adjustment are first and second. 2 delay locked loops (DLL1, DLL2) are applied.

The clock selector 220 connects the first and second multiplexers MUX1 and MUX2 in series so that the first multiplexer MUX1 is one of the first strobe signal STB1 and the external strobe signal STBE. The second multiplexer MUX2 selects one of the signal selected by the first multiplexer MUX1 and the second strobe signal STB2 and outputs the selected second strobe signal SLSTB2.

The data capture unit 230 includes a first flip-flop block FB1, a second flip-flop block FB2, a third flip-flop block FB3, and a fourth flip-flop block FB4. The first bits DQ1 and the second bits DQ2 are captured in synchronization with the first selection strobe signal SLSTB1 and the second selection strobe signal SLSTB2, respectively.

The first bits DQ1 of the semiconductor test data may be lower 4 bits, and the second bits DQ2 may be upper 4 bits. When the first bits DQ1 and the second bits DQ2 are captured in synchronization with different strobe signals, four bits of data can be independently tested, so that two X4 mode data can be tested at one time.

The semiconductor test data capture circuit includes a first strobe signal in synchronization with an external strobe signal STBE as well as a data capture unit 230 for capturing test data composed of the first bits DQ1 and the second bits DQ2. The apparatus may further include a first strobe signal capture unit 240 for capturing the STB1 and a second strobe signal capture unit 250 for capturing the second strobe signal in synchronization with the first selection strobe signal SLSTB1.

4 is a block diagram illustrating a first flip-flop block FB1 and a second flip-flop block FB2 for capturing one of the first bits of semiconductor test data.

Referring to FIG. 4, when one bit DQ1 [0] of the first bits DQ1 of the semiconductor test data is continuously transmitted, the first flip-flop FF1 at the rising edge of the first strobe signal STB1. ) Is inputted to the second flip-flop FF2 and is synchronized with the second flip-flop FF2 at the falling edge of the first strobe signal STB1. The falling edge of the first strobe signal STB1 is captured and output to the third flip-flop FF3. Therefore, at the falling edge of the first strobe signal STB1, data captured at the rising edge and the falling edge are simultaneously output through the separate output lines FOUT [0] and SOUT [0].

TABLE 1

SEL0 SEL1 Operation mode 0 0 X4 0 One X8 One One External strobe

Table 1 shows an operation mode of the semiconductor test apparatus according to the clock selection signal in one embodiment. Referring to Table 1, the clock select signals SEL0 and SEL1 are 2-bit signals. When the clock select signal has a value of "00", the first multiplexer MUX1 selects the first strobe signal STB1 and the second multiplexer selects the second strobe signal STB2 to enter the X4 mode. It can work. In this case, two data in X4 mode can be tested simultaneously. When the clock selection signal has a value of "01", the first multiplexer MUX1 and the second multiplexer MUX2 may select the first strobe signal STB1 to operate in the X8 mode. When the clock select signal has a value of "11", the first multiplexer MUX1 and the second multiplexer MUX2 select the external strobe signal.

FIG. 5 is a timing diagram illustrating timings of semiconductor test data and data output to captured and separated output lines.

Referring to FIG. 5, one bit DQ1 [0] of the first bits DQ1 of the semiconductor test data is captured at the rising edge EG1 and the falling edge EG2 of the first strobe signal STB, respectively. . The phase of the first strobe signal STB1 may be further delayed by a certain amount PHD in order to capture data without error in a section in which no data transition of the test data DQ1 occurs. In one embodiment, the phase is further delayed by about 90 degrees.

The data D1 captured at the rising edge EG1 of the first strobe signal STB1 is output to the output line FOUT1 [0] in synchronization with the falling edge of the strobe signal STB, and at the falling edge EG2. The captured data D2 is output to another output line SOUT1 [0] in synchronization with the falling edge of the first strobe signal STB1. This operation is repeated each time the rising and falling edges of the strobe signal STB are repeated. Therefore, the bandwidth of the captured data output to a separate output line can be reduced by half than the bandwidth of the semiconductor test data transmitted to the data capture circuit.

As a result, even devices for testing low operating speeds can test semiconductor devices operating at higher operating speeds. For example, you can test a 1.6GBps memory device using a test device implemented for testing 800MBps of memory using an FPGA, etc., so you do not have to create a new platform and the cost of redesign Can be reduced.

The data capture circuit of the semiconductor test apparatus according to an embodiment of the present invention may transfer data between systems having different operating speeds.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. I will be able.

1 is a block diagram illustrating a data exchange process between two systems having different operating speeds.

2 is a block diagram illustrating a data capture circuit of a semiconductor test apparatus according to an embodiment of the present invention.

3 is a circuit diagram illustrating a data capture circuit of a semiconductor test apparatus according to an embodiment of the present invention.

4 is a block diagram illustrating a first flip-flop block and a second flip-flop block to capture one of the first bits of semiconductor test data.

FIG. 5 is a timing diagram illustrating timings of semiconductor test data and data output to captured and separated output lines.

Claims (12)

A phase adjuster configured to adjust phases of the first strobe signal and the second strobe signal in response to the phase control signal; In response to a clock selection signal, one of an external strobe signal and the first strobe signal is selected and output as a first selection strobe signal, and one of the first selection strobe signal and the second strobe signal in response to the clock selection signal. A clock selector configured to select and output a second selected strobe signal; And Capture semiconductor test data in synchronization with the first and second sections of each of the first and second selection strobe signals, and capture the data captured in synchronization with the first section and the data captured in synchronization with the second section. And a data capture unit for outputting output lines separated from each other. The method of claim 1, And the bandwidth of the semiconductor test data is an integer multiple of the bandwidth of the data captured in synchronization with the first interval of the first and second selection strobe signals. The method of claim 1, The bandwidth of the semiconductor test data is an integer multiple times greater than the bandwidth of the data captured in synchronization with the second period of the first and second selection strobe signal. The method of claim 1, And the first section of the first and second selection strobe signals is a rising edge and the second section of the first and second selection strobe signals is a falling edge. The method of claim 1, wherein the data capture unit A first flip-flop block for capturing and outputting first bits of the semiconductor test data in response to a first period of the first selection strobe signal; A second flip-flop block that captures and outputs the first bits of the semiconductor test data in response to a second period of the first selection strobe signal; A third flip-flop block configured to capture and output second bits of the semiconductor test data in response to a first period of the second selection strobe signal; And And a fourth flip-flop block for capturing and outputting the second bits of the semiconductor test data in response to the second period of the second selection strobe signal. The method of claim 1, wherein the phase control unit The phases of the first and second selection strobe signals may be phased so that the first and second periods of the first and second selection strobe signals are synchronized with each other in a period where no data transition of the semiconductor test data occurs. A data capture circuit of a semiconductor test device, characterized in that it is delayed more than phase. The method of claim 6, wherein the phase control unit And delaying the phases of the first and second selection strobe signals by 90 degrees more than the phases of the semiconductor test data. The method of claim 6, wherein the phase control unit A first delay locked loop for adjusting a phase of a first strobe signal in response to the phase adjustment signal; And And a second delay locked loop for adjusting a phase of a second strobe signal in response to the phase control signal. The method of claim 1, wherein the clock selector A first multiplexer for selecting one of an external strobe signal and the first strobe signal in response to the clock selection signal and outputting the selected signal as the first selection strobe signal; And And a second multiplexer configured to select one of the first selection strobe signal and the second strobe signal in response to the clock selection signal, and output the second selection multiplexer signal as the second selection strobe signal. Capture circuit. The method of claim 9, When the first multiplexer selects the first strobe signal and the second multiplexer selects the second strobe signal, the first bits of the semiconductor test data and the second bits of the semiconductor test data are selected. A data capture circuit of a semiconductor test device, characterized in that the test independently. The method of claim 5, And the first bits are the lower four bits of the semiconductor test data, and the second bits are the upper four bits of the semiconductor test data. The method of claim 1, A first strobe signal capture unit configured to capture the first strobe signal in synchronization with a first section and a second section of the external strobe signal; And And a second strobe signal capture unit configured to capture the second strobe signal in synchronization with the first and second sections of the first selection strobe signal.

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