CN1555168A - Damage-free switching method for main and spare synchronous digital series device timing source - Google Patents
Damage-free switching method for main and spare synchronous digital series device timing source Download PDFInfo
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- CN1555168A CN1555168A CNA2003101217826A CN200310121782A CN1555168A CN 1555168 A CN1555168 A CN 1555168A CN A2003101217826 A CNA2003101217826 A CN A2003101217826A CN 200310121782 A CN200310121782 A CN 200310121782A CN 1555168 A CN1555168 A CN 1555168A
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Abstract
A harmless switching method for SETS function modules in a SDH system includes: mutually sending clock and frame location pulse between master and alternative modules for controlling state signals to control the one-from-two logic circuit to make the phase and frequency of the output system clocks and system frame location pulses of the two modules completely the same, each own voltage-control oscillator traces the same timing source. A returned button is set in them for controlling the alternative turning to the master by triggering it manually and the original master module is activated to realize switching. The alternative module output clock and the frame timing pulse are at ordinary output state not controlled by three states output. The module switch time scale is selected in the sphere of frame head so that the frame location pulse is continuous and a line interface module processes the clock sent by the master, alternative timing souses function module smoothly after one-from-two logic circuit.
Description
Technical field
The present invention relates to provide the method for steady timing signal, relate to the method that in synchronous digital hierarchy (SDH) system, synchronous digital hierarchy timing source (SETS) functional module (other modules that perhaps comprise this generic module) be can't harm switching particularly in synchronous digital hierarchy (SDH) system.
Background technology
Be the normal operation of SDH system, two synchronous digital hierarchy timing source modules (SETS) generally be provided in system, one of them as primary module and another as being equipped with module, primary module and be equipped with module and backup each other.In the course of work of SDH system, in case operation troubles appears in the SETS primary module, system start-up is in the module that is equipped with of Hot Spare state, realizes active and standby automatic switchover.When needs carry out system maintenance, or the attendant needs artificial plug SETS primary module and is equipped with module when the software and hardware of upgrading module, also has primary module and is equipped with the switching problem of module.For LIM, have an instantaneous interruption from the clock signal of SETS, along with the length difference of break period, the performance of SDH system is also made a world of difference.Sometimes the bigger shake that only can produce timing signal, produce the little error code of circuit sometimes, big error code, even the main alarm of section layer, thereby the optical fiber transmission network that causes twin nuclei carries out ring switching so that keep communication, and this has had a strong impact on the stability and the reliability of transmission network.
In traditional SDH system design, the Redundancy Design of SETS functional module as shown in Figure 1, the system reference timing source comprises outer regularly (T3) among the figure, circuit is (T1) and branch road timing (T2) regularly.The active and standby situation of module working state signal representation module, " 0 " expression is main, and " 1 " expression is equipped with.(some system considers from the angle that reduces system noise and module dissipation the control signal that this type of condition indicative signal is regularly exported as this module on the one hand, close the timing output of module fully), on the other hand, this condition indicative signal also carries out the regularly control signal of selection as LIM.
In some SETS systems as shown in Figure 2, with the primary module fixed-site, LIM only provides a condition indicative signal line by fixing SETS primary module for simplified design, and standby SETS functional module is to drawing on this index signal line.Have only this moment under the not on the throne or situation about losing efficacy of primary module, be equipped with module and just start working.
For two kinds of SETS main backup module set-up modes illustrated in figures 1 and 2, synchronization timing output-controlled in cross complaint condition line and ternary control logic door.
LIM is generally taked interface mode as shown in Figure 3, wherein by primary module status signal and the logical circuit that is equipped with two alternatives of module status signal controlling from primary module clock/be equipped with and select a tunnel the module clock, from primary module frame pulse/be equipped with and select a tunnel the module frame pulse as system-frame pulse in the module as system clock in the module.
In sum, the factor that influences the clock interruption in the SDH system has following several respects: the first, and the bound-time of cross complaint condition line is with constantly in the active and standby SETS functional module; The second, the bound-time of active and standby SETS functional module output state index line (generally the state index line by cross complaint produces) is with constantly; The 3rd, when switching, the timing signal (clock signal and frame alignment pulse signal) that is equipped with the SETS functional module arrives the time and the moment of LIM; The 4th, the intrinsic response time of alternative logical circuit in the LIM.
And the more common way in this area realizes the SETS functional module by special chip, has mainly solved following problem: the clock after accomplishing to switch when active and standby SETS functional module is switched with switch before clock with homophase frequently; Has the jitter suppression effect; Support several SETS patterns: free oscillation keeps and locking; Other auxiliary monitoring functions.But produced following problem again simultaneously: autgmentability is restricted; Because the analog phase-locked look broader bandwidth, the noise that produces for the prime digital phase-locked loop can't suppress, and the clock of output need be trembled processing in the sheet through in the past, and not only the placement-and-routing to PCB has relatively high expectations, and is a very big lifting aspect cost.
Summary of the invention:
The object of the invention provides a kind of lossless switching method of active and standby synchronous digital series device timing source, this method can solve existing problem in the prior art, shorten main timing source module in the synchronous digital hierarchy (SDH) system and be equipped with change action spent between the timing source module time, select the phase place of the best time of switching between the active and standby timing source module, the system clock of guaranteeing the output before and after switching of timing source functional module and 8KHz frame alignment pulse signal identical, realize LIM to the smoothing processing of clock signal of system so that have the maintenance of interruption effect.
A kind of lossless switching method that is used for the active and standby synchronous digital series device timing source module of SDH transmission system provided by the invention comprises the steps: voltage controlled oscillator clock in the primary module is exported to primary module, is equipped with the alternative logical circuit in the module, also will be equipped with simultaneously the interior voltage controlled oscillator clock of module and export to primary module, be equipped with the alternative logical circuit in the module, send clock mutually to carry out between the main backup module; Under the free-running operation pattern, control alternative logical circuit in the active and standby synchronous digital series device timing source module with the cross complaint status signal, make primary module select the output clock of voltage controlled oscillator in this module, make simultaneously to be equipped with the output clock that module is also selected the primary module voltage controlled oscillator, in full accord with the output system clock and the system-frame position pulse that guarantee active and standby two modules; Under locking mode, primary module be equipped with module in separately voltage controlled oscillator follow the tracks of identical timing source, so that two clock signals of the input of the alternative logical circuit in main backup module are with the frequency homophase, when primary module and be equipped with when switching mutually between the module, two functional modules have only very little variation in the clock frequency of switching moment maintenance output, do not meet switching so that realize not having; Cross complaint frame alignment pulse signal is provided between active and standby module, control the frame alignment pulse homophase of active and standby module output and in handoff procedure the frame alignment pulse do not change phase place; Alternative is carried out in the frame alignment pulse handle, simultaneously the main backup module switching instant is chosen as data frame head scope, assurance frame alignment pulse is not interrupted.
In timing source main backup module lossless switching method of the present invention, it is uncontrolled that the timing of module is fully exported, and keeps forever being in output state; Disturb for reducing beat, also reduced the frequency of system clock; Before main backup module is carried out direct-cut operation, send the switching enabling signal by remote network management or local diverter switch, realize the main backup module soft handover, reduce because the break period that change action causes timing signal (clock and frame alignment pulse).
By the lossless switching method of synchronous digital hierarchy master/slave device timing source, can be implemented in the handoff procedure that the output of timing source clock is not interrupted, clock phase remains unchanged.
Description of drawings
Fig. 1 is a kind of schematic diagram of synchronous digital series device timing source main backup module configuration of prior art;
Fig. 2 is the schematic diagram of the synchronous digital series device timing source main backup module configuration of another kind of prior art;
Fig. 3 is the LIM schematic diagram of prior art;
Fig. 4 is the schematic diagram of the employed synchronous digital series device timing source of the inventive method main backup module configuration;
Fig. 5 uses the schematic diagram of diverter switch of the inventive method and the signal of generation;
Fig. 6 is a clock source signals sequential chart of using the inventive method;
Fig. 7 uses the schematic diagram that the functional module structure in the clock source module of the inventive method is formed.
Embodiment
Below in conjunction with accompanying drawing, the embodiment of the inventive method is elaborated.
In the specific implementation process of the inventive method, in following concrete mode active and standby timing source module is used: at first, the alternative logical circuit is controlled by " cross complaint condition line ", primary module is selected the output clock of voltage controlled oscillator (38.88MHz) in this module, is equipped with the clock that module selects primary module to send here; The output system clock and the system-frame position pulse that guarantee two modules under normal holotype are in full accord; Secondly, under locking mode, because primary module and the voltage controlled oscillator (38.88MHz) that is equipped with in the module are separately followed the tracks of identical timing source, thereby at the input of alternative logical circuit, two clock signals have the characteristics with the frequency homophase; At primary module be equipped with when switching mutually between the module, for the system clock of two modules outputs, process is seamless, and eliminating that clock in the handoff procedure interrupts is (detailed description is hereinafter arranged) of being realized by the functional module in the LIM; For the system-frame position pulse of two module outputs, in module, passed through the processing of " functional module " owing to produce the clock of frame alignment pulse, process is seamless, and is not interrupt; The 3rd, the effect of cross complaint frame pulse is to make the system-frame position pulse homophase of the output of the system-frame position pulse of module output fully and primary module; For the frame alignment pulse of assurance system output does not have interruption, except the clock that requires to produce this pulse does not interrupt, also guarantee that by cross complaint frame alignment pulse position pulse phase place in handoff procedure does not change, since we control switching the time be engraved in the frame head place, promptly in the SDH information flow, be in first row of SOH, after the interface of A1 and A2, so cross complaint frame alignment pulse is in the frame alignment pulse-break that frame head optional position in addition can not cause system's output; At last, to handle through alternative the system-frame position pulse in the LIM, this is handled as shown in Figure 3, without smoothing processing the time, will inevitably produce interruption, because being chosen in the frame head place of data, we carry out change action, make switching position far away from the position of system-frame position pulse, two positions lag behind system-frame position pulse 1088ns (this value can be different because of different SDH systems) through being measured as the data frame head on sequential, thereby the processing of alternative gate can not cause the interruption of this position pulse.
In order to reduce the time of handoff procedure, take two kinds of methods: first method, it is not controlled that the timing of module is fully exported, and is in normal output state.At this moment, consider that the output signal of module can bring beat to disturb to system fully, we take to reduce the way of the frequency (being designed to 38.88MHz) of system clock, reduce system interference.Second method carries out the transition to the hard handover approach of directly pulling out primary module the soft handoff of controlling or switch by this locality the control that goes into operation by remote network management.For carrying out the soft handover of local control, a recoverable button need be set on the panel of SETS functional module, manual activation is in the button one or many on the module fully that is equipped with state, being equipped with module, to activate this module by the cross complaint condition line be primary module, the original primary module of deexcitation simultaneously, the purpose of arrival soft handover.The module that extract deexcitation this moment realizes direct-cut operation indirectly.
Because the randomness of manual operation button, in the process that button is pressed, repeatedly trailing edge may appear, and central processing unit (CPU) control section only responds a trailing edge action in the module, in case receive the switching command of manual pushbutton, the switching of activestandby state promptly take place.Other trailing edge for for the triggering of primary module is invalid, thereby avoided repeatedly triggering.
In addition, because operation primary module button can cause two of instantaneous appearance to be standby transient state, the button that operation is equipped with module can cause two transient states that are main usefulness, and from the time length that clock interrupts, the former time will be grown.Therefore, we are designed to not respond the button control of primary module, and only response is equipped with the button control of module.
What deserves to be mentioned is, owing to safeguard on-the-spot variation, often near the attendant, there is not manipulable webmaster, therefore directly pull out primary module and realize that the phenomenon of switching is quite common, adopt said method that direct-cut operation is carried out the transition to soft handover, both satisfied the current demand of attendant's direct-cut operation, will be controlled at switching time in the time range of soft handover simultaneously.
Because master/backup clock output is not controlled, handoff procedure is in fact by module status index signal line traffic control.We are by the active and standby system-frame position pulse that send mutually, and the control change action takes place at the boundary of frame, is unlikely to influence the bit stream of payload part.
Fig. 6 has represented to select the sequential chart of system-frame position pulse signal, clock signal of system in switching instant and the handoff procedure.SDH information flow wherein comprises net load and administration overhead, and administration overhead has comprised section overhead and path overhead again; Dotted portion is represented the clock change procedure in the LIM, reaches after of short duration shake and the same homophase frequently of former master's clock.
The SETS functional module has guaranteed that handoff procedure is seamless quick switching after by above processing, switch the time be engraved in the border (overhead byte place) of frame, the interruption in clock source unavoidably appears in LIM when carrying out clock selecting, thereby we provide smoothing function module cheaply, and the clock frequency deviation before and after guaranteeing to select is controlled in system's permissible range and (actually reaches 10～20ppm).
Introduce the concrete structure and the working method of " functional module " among Fig. 4 below in detail, Fig. 7 is the concrete structure schematic diagram of this functional module.Utilize the little characteristics of crystal oscillator frequency control range, need not phase frequency detector, only need to consider to adopt single phase discriminator to get final product.When crystal oscillator is on input reference clock, utilize the good characteristics of standard of crystal oscillator, control voltage is near the centered level; And when input reference clock interrupted, the output of XOR gate was in centered level, and crystal oscillator its control change in voltage when having or not with reference to input clock is very little like this, so the variation of its frequency is also very little, specifically in the number range of ± 10ppm.When system clock switches, the variation tendency of the output clock frequency of crystal oscillator is ± the 10ppm number range in, the time that makes clock switch is very short, so the variation of the output clock frequency of crystal oscillator is very little, thereby has created condition for the seamless switching of clock.
Utilize active and standby timing source configuration mode shown in Figure 4, utilize the inventive method, finished on the SDH of 10G bandwidth synchronous multiplexing equipment and switched experiment, switching reaches and does not occur error code or disruption more than 30 times repeatedly.Use the equipment of conventional scheme that tangible improvement has been arranged.
Claims (7)
1. a lossless switching method that is used for the active and standby synchronous digital series device timing source module of SDH transmission system is characterized in that this method comprises the steps:
Voltage controlled oscillator clock in the primary module or the clock that is derived from this oscillator are exported to primary module, are equipped with the alternative logical circuit in the module, the clock that also will be equipped with simultaneously voltage controlled oscillator clock in the module or be derived from this oscillator is exported to primary module, is equipped with the alternative logical circuit in the module, send clock mutually to carry out between the main backup module;
Control alternative logical circuit in the active and standby synchronous digital series device timing source module with the cross complaint status signal, make primary module select the output clock of voltage controlled oscillator in this module, make simultaneously to be equipped with the output clock that module is also selected the primary module voltage controlled oscillator, in full accord with the output system clock and the system-frame position pulse that guarantee active and standby two modules;
Under locking mode, primary module be equipped with module in separately voltage controlled oscillator follow the tracks of identical timing source, so that two clock signals of the input of the alternative logical circuit in main backup module are with the frequency homophase, when primary module and be equipped with when switching mutually between the module, two functional modules have only very little variation in the clock frequency that switching moment maintenance exports LIM to, do not meet switching so that realize not having;
Utilize functional module that the clock that produces cross complaint frame alignment pulse signal and system-frame pulse signal in the active and standby module is carried out smoothing processing, so that eliminate the minor variations of clock frequency in handoff procedure;
Cross complaint frame alignment pulse signal is provided between active and standby module, and makes this pulse signal be in the optional position beyond the frame head, control the frame alignment pulse homophase of active and standby module output and in handoff procedure the frame alignment pulse do not change phase place;
Alternative is carried out in the frame alignment pulse handle, simultaneously the main backup module switching instant is chosen as data frame head scope, the frame alignment pulse that guarantees to be in the fixed position beyond the frame head is interrupted at handoff procedure.
2. according to the method for claim 1, it is uncontrolled to it is characterized in that making the timing of module fully to export, and keeps forever being in output state.
3. according to the method for claim 1, it is characterized in that reducing the frequency of system clock, making this frequency is 38.88MHz or low frequency more.
4. according to the method for claim 1, it is characterized in that sending the switching enabling signal by remote network management or local diverter switch, realize the main backup module soft handover before the main backup module implementation direct-cut operation.
5. according to the method for claim 1, the clock signal that it is characterized in that main backup module output instantaneous interruption can occur after through the alternative circuit in the LIM, by functional module in the LIM clock signal is carried out smoothing processing, can not interrupt to guarantee the clock behind the alternative circuit.
6. according to the method for claim 1, it is characterized in that functional module is realized by single phase discriminator cheaply in this module and general crystal oscillator the smoothing processing of clock signal.
7. according to the method for claim 1, it is characterized in that this method can also be used for the harmless switching that SDH transmission system comprises other module of synchronous digital series device timing source module.
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| CNB2003101217826A CN100369441C (en) | 2003-12-24 | 2003-12-24 | Damage-free switching method for main and spare synchronous digital series device timing source |
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| CNB2003101217826A CN100369441C (en) | 2003-12-24 | 2003-12-24 | Damage-free switching method for main and spare synchronous digital series device timing source |
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100428647C (en) * | 2005-05-27 | 2008-10-22 | 华为技术有限公司 | Method for keeping uniform of main/stand-by clock of communication system |
| CN101577635B (en) * | 2009-05-22 | 2011-04-20 | 北京荣达千里科技有限公司 | Undamaged switching method of frameless signal |
| CN101345596B (en) * | 2007-07-09 | 2011-11-02 | 大唐移动通信设备有限公司 | Exception handling method and apparatus of synchronization digital sequence network |
| CN1819499B (en) * | 2006-01-06 | 2011-12-14 | 烽火通信科技股份有限公司 | Synchronous circuit processing method by master spare low-order pointer |
| CN101043449B (en) * | 2006-03-21 | 2011-12-28 | 卓联半导体有限公司 | Timing source |
| CN101667906B (en) * | 2008-09-03 | 2012-01-11 | 中兴通讯股份有限公司 | Method and system for switching main and backup clocks |
| CN103200032A (en) * | 2013-03-15 | 2013-07-10 | 卡斯柯信号有限公司 | Safe and reliable host and backup generator tripping system |
| CN104854531A (en) * | 2012-12-13 | 2015-08-19 | 相干逻辑公司 | Reconfiguration of clock generation circuitry |
| CN104967791A (en) * | 2015-07-07 | 2015-10-07 | 广州魅视电子科技有限公司 | Distributed audio and video transmission control system |
| WO2016184148A1 (en) * | 2015-10-29 | 2016-11-24 | 中兴通讯股份有限公司 | Clock switching method, apparatus and base station |
| CN113064342A (en) * | 2021-03-16 | 2021-07-02 | 重庆两江卫星移动通信有限公司 | Digital multi-beam signal processing system and time synchronization method |
| CN113556201A (en) * | 2021-08-03 | 2021-10-26 | 中国科学院国家授时中心 | Multi-reference clock switching device and method based on beat digital frequency measurement |
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| JPH0546422A (en) * | 1991-08-20 | 1993-02-26 | Fujitsu Ltd | Current/standby switching system |
| CN1155359A (en) * | 1994-06-21 | 1997-07-23 | Dsc通讯有限公司 | Apparatus and method for clock alignment and switching |
| CN1151627C (en) * | 1999-12-29 | 2004-05-26 | 上海贝尔有限公司 | Synchronous clock supply device |
| CN1156995C (en) * | 2000-07-11 | 2004-07-07 | 深圳市中兴通讯股份有限公司 | Jitter-free change-over method and device for main and stand-by units capable of being hot plugged and unplugged in digital communication system |
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| CN100428647C (en) * | 2005-05-27 | 2008-10-22 | 华为技术有限公司 | Method for keeping uniform of main/stand-by clock of communication system |
| CN1819499B (en) * | 2006-01-06 | 2011-12-14 | 烽火通信科技股份有限公司 | Synchronous circuit processing method by master spare low-order pointer |
| CN101043449B (en) * | 2006-03-21 | 2011-12-28 | 卓联半导体有限公司 | Timing source |
| CN101345596B (en) * | 2007-07-09 | 2011-11-02 | 大唐移动通信设备有限公司 | Exception handling method and apparatus of synchronization digital sequence network |
| CN101667906B (en) * | 2008-09-03 | 2012-01-11 | 中兴通讯股份有限公司 | Method and system for switching main and backup clocks |
| CN101577635B (en) * | 2009-05-22 | 2011-04-20 | 北京荣达千里科技有限公司 | Undamaged switching method of frameless signal |
| CN104854531B (en) * | 2012-12-13 | 2018-05-18 | 相干逻辑公司 | Clock generating circuit reconfigures |
| CN104854531A (en) * | 2012-12-13 | 2015-08-19 | 相干逻辑公司 | Reconfiguration of clock generation circuitry |
| CN103200032A (en) * | 2013-03-15 | 2013-07-10 | 卡斯柯信号有限公司 | Safe and reliable host and backup generator tripping system |
| CN103200032B (en) * | 2013-03-15 | 2016-08-17 | 卡斯柯信号有限公司 | A kind of safe and reliable active and standby cut machine system |
| CN104967791A (en) * | 2015-07-07 | 2015-10-07 | 广州魅视电子科技有限公司 | Distributed audio and video transmission control system |
| WO2016184148A1 (en) * | 2015-10-29 | 2016-11-24 | 中兴通讯股份有限公司 | Clock switching method, apparatus and base station |
| CN113064342A (en) * | 2021-03-16 | 2021-07-02 | 重庆两江卫星移动通信有限公司 | Digital multi-beam signal processing system and time synchronization method |
| CN113064342B (en) * | 2021-03-16 | 2022-02-01 | 重庆两江卫星移动通信有限公司 | Digital multi-beam signal processing system and time synchronization method |
| CN113556201A (en) * | 2021-08-03 | 2021-10-26 | 中国科学院国家授时中心 | Multi-reference clock switching device and method based on beat digital frequency measurement |
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